CN114124594A

CN114124594A - Data transmission method and system, and chip

Info

Publication number: CN114124594A
Application number: CN202010902743.3A
Authority: CN
Inventors: 潘德灿; 马永吉; 王小东
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2022-03-01
Also published as: WO2022042396A1

Abstract

The application provides a data transmission method, a system and a chip, wherein the data transmission method comprises the following steps: receiving a write access request of an on-chip bus; wherein, the on-chip bus write access request comprises: valid data; acquiring configuration information of a packaging head; according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data.

Description

Data transmission method and system, and chip

Technical Field

The embodiment of the application relates to the field of integrated circuit design, in particular to a data transmission method, a data transmission system and a chip.

Background

The most widely and mature application of inter-chip data transmission (or inter-chip direct data access) is a high-speed serial computer expansion bus (PCIE) interface, but the PCIE interface only supports point-to-point access, is inflexible in topology, only supports inter-chip data transmission on a board, and is mainly applied to an X86 computer system. In addition, the PCIE interface has a high operating frequency, the interface is complex to implement and debug, and the single channel bandwidth is limited.

With the wider application of the ethernet technology, the ethernet transmission bandwidth is higher and higher, the ethernet of the chip interface is more and more obvious, and it is an important trend to use the ethernet messages for inter-chip data transmission and has great advantages. The data transmission between the chips is carried out based on the Ethernet packet, and a flexible topological structure can be constructed by utilizing the flexible routing characteristic of the Ethernet packet and relying on an independent exchange chip on a board or between boards or an exchange accelerator embedded in the chip. The traditional method for inter-chip data transmission based on the Ethernet packet is too complex in implementation process, so that the complexity of chip design is increased, more resources are consumed by a chip, the area of the chip is larger, the power consumption of the chip is larger, and the cost of the chip is increased.

Disclosure of Invention

The embodiment of the application provides a data transmission method, a data transmission system and a chip.

In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a first chip, and the method includes:

receiving a write access request of an on-chip bus; wherein, the on-chip bus write access request comprises: valid data;

acquiring configuration information of a packaging head;

according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data.

In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a second chip, and the method includes:

receiving a first Ethernet packet; wherein the first ethernet packet comprises: a package header and valid data;

when the package head includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; the access address is the address of the valid data in the memory of the second chip;

and obtaining effective data from the first Ethernet packet according to the effective data length, and writing the obtained effective data into the access address.

In a third aspect, an embodiment of the present application provides a chip, including: at least one Ethernet transmission module; each ethernet transmission module comprises: the on-chip bus write access request receiving submodule, the configuration information obtaining submodule and the Ethernet packet packaging and sending submodule;

the on-chip bus write access request receiving submodule is used for receiving an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data;

the configuration information acquisition submodule is used for acquiring the configuration information of the packaging head;

the Ethernet package encapsulation sending submodule is used for encapsulating the effective data into a first Ethernet package according to the configuration information of the encapsulation head and sending the first Ethernet package; wherein the first ethernet packet comprises: a package header and valid data.

In a fourth aspect, an embodiment of the present application provides a chip, including: at least one ethernet receiving module; each ethernet reception module comprises: the Ethernet packet receiving submodule and the data writing submodule;

the Ethernet packet receiving submodule is used for receiving a first Ethernet packet; wherein the first ethernet packet comprises: a package header and valid data;

a data write submodule for when the pack head includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; the access address is the address of the valid data in the memory of the second chip; and obtaining effective data from the first Ethernet packet according to the effective data length, and writing the obtained effective data into an address range.

In a fifth aspect, an embodiment of the present application provides a chip, including: at least one ethernet sending module of any kind above, and at least one ethernet receiving module of any kind above.

In a sixth aspect, an embodiment of the present application provides a data transmission system, including:

the first chip is used for receiving an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data; acquiring configuration information of a packaging head; according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data;

and the third chip is used for receiving the first Ethernet packet, writing the first Ethernet packet into a randomly allocated address in the memory, classifying the first Ethernet packet and then queuing the first Ethernet packet into a queue specified by the central processing unit.

In a seventh aspect, an embodiment of the present application provides a data transmission system, including:

the first chip is used for receiving an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data, a valid data length, and an access address; the access address is the address of the valid data in the memory of the second chip; acquiring configuration information of a packaging head; according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data; the packaging head includes: the user-defined head, the user-defined head includes: effective data length and access address;

the second chip is used for receiving the first Ethernet packet; wherein the first ethernet packet comprises: a package header and valid data; when the package head includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; and obtaining effective data from the first Ethernet packet according to the effective data length, and writing the obtained effective data into the range address.

According to the Data transmission method provided by the embodiment of the application, when the effective Data needs to be sent, the effective Data is directly encapsulated into the first Ethernet packet and sent out, the effective Data does not need to be written into a Double Data Rate (DDR) first, and the bandwidth of the DDR is effectively reduced; a Central Processing Unit (CPU) is not required to participate in the process of transmitting the effective data, namely, extra CPU core resources are not required to be occupied; therefore, the complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is reduced.

According to the data transmission method provided by the embodiment of the application, when the first Ethernet packet is received, the effective data is directly obtained from the first Ethernet packet and written into the corresponding access address, the first Ethernet packet does not need to be analyzed and classified, and the logic is simpler to realize, so that the complexity of chip design is reduced, the area and the power consumption of a chip are effectively reduced, and the cost of the chip is also reduced.

Drawings

FIG. 1 is a block diagram of a conventional inter-chip data interchange system;

fig. 2 is a flowchart of a data transmission method according to an embodiment of the present application;

fig. 3 is a flowchart of a data transmission method according to another embodiment of the present application;

FIG. 4 is a block diagram of a chip according to another embodiment of the present application;

FIG. 5 is a block diagram of a chip according to another embodiment of the present application;

fig. 6 is a block diagram of a data transmission system according to another embodiment of the present application;

fig. 7 is a block diagram of a data transmission system according to another embodiment of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present application, the following describes the data transmission method, system, and chip provided in the present application in detail with reference to the accompanying drawings.

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The embodiments and features of the embodiments of the present application may be combined with each other without conflict.

As used herein, the term "and/or" includes any and all combinations of at least one of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of at least one other feature, integer, step, operation, element, component, and/or group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a block diagram of a conventional inter-chip data interchange system. As shown in fig. 1, the process that the data processed by the subsystem (SUBSYS) of the chip 1 needs to be transmitted to the MEMory (MEM) of the chip 2 is as follows:

the SUBSYS of the chip 1 writes the processed Data into a Double Data Rate (DDR) according to an instruction of a Central Processing Unit (CPU), and the ethernet packet transmission accelerator (ETH _ TX _ ACC) reads Data to be transmitted from an address corresponding to the DDR according to the instruction of the CPU, and encapsulates the read Data into an ethernet packet and transmits the ethernet packet to the chip 2.

The chip 2 receives the ethernet packet sent by the chip 1, the ethernet packet receiving accelerator (ETH _ RX _ ACC) writes the received packet into a randomly allocated address in the memory, analyzes and classifies the packet and then enters a queue designated by the CPU, the CPU takes out a packet queue identifier (ID, Identity) from the queue, and reads the packet according to the packet queue ID for processing.

The inter-chip data transmission process mainly has the following problems:

(1) assuming that the traffic demand of data transmission is 50Gbps, chip 1 needs to reserve a DDR bandwidth of 125Gbps (gigabits per second) for a data transmission channel (evaluated according to 40% DDR utilization rate) in design, assuming that the frequency of one DDR controller is 3200 megahertz (MHz), and the bit width of data is 32 bits (bit), at least one DDR controller (not shown in fig. 1) needs to be additionally designed and corresponding DDR particles are reserved, which will undoubtedly increase the complexity of chip design, increase chip area, increase chip power consumption, and thus increase the cost of chip application (for example, the cost of chip is higher when the chip area is larger, the number of heat dissipation devices is more when the chip power consumption is larger, and additional DDR particles are needed).

(2) In the data mutual transmission process, the chip 1 needs the whole-process participation of the CPU, that is, the CPU needs to issue a sending command to the ETH _ TX _ ACC, construct a description or a message header structure and the like needed for message sending. Considering that the data traffic transmitted between the chips is relatively large, at least one CPU core is required to complete the work, so that the chip 1 needs to reserve one CPU core for the data transmission channel in design, and the increase of the CPU core is introduced, which leads to the increase of complexity of chip design, the increase of chip area, and the increase of chip power consumption, thereby leading to the increase of chip cost.

(3) After the chip 2 receives the message, the ETH _ RX _ ACC is required to analyze and classify the message, and complex logic is introduced, so that the complexity of chip design is increased, the chip area is increased, and the chip power consumption is increased, thereby increasing the chip cost.

Fig. 2 is a flowchart of a data transmission method according to an embodiment of the present application.

In a first aspect, referring to fig. 2, an embodiment of the present application provides a data transmission method, which is applied to a first chip, where it is to be noted that the first chip refers to a chip that needs to perform inter-chip data transmission, and may specifically be any type of chip, such as a baseband processing chip, a CPU chip, and the like.

The method comprises the following steps:

step 200, receiving a write access request of an on-chip bus; wherein, the on-chip bus write access request comprises: valid data.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (e.g., the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is data obtained after processing the data and needs to be transmitted to the second chip.

It should be noted that after the data processing module processes the data, it generally initiates multiple on-chip bus write access requests for the processed data, that is, effective data in each initiated on-chip bus write access request is only a small part of the processed data, the data processing module can initiate the on-chip bus write access request at regular time, after receiving the on-chip bus write access request, if the on-chip bus write access request is not ready to be processed, the on-chip bus write Access request may be temporarily stored into a Random Access Memory (RAM), since the valid data in the on-chip bus write access request is only a small portion of the processed data, therefore, temporarily storing on-chip bus write access requests in the RAM does not take up too much memory space, i.e. does not require that too much memory space is reserved for the transmission of data.

It should be noted that the size of the valid data in each initiated on-chip bus write access request may be set at will according to the actual situation, and may be set to be an integer multiple of the bus bit width in general.

In some exemplary embodiments, most of the currently mainstream chip designs are based on an Advanced Reduced Instruction Set (RISC) core, and an Advanced eXtensible Interface (AXI) bus is used for on-chip interconnection, so that an on-chip bus write access request can be initiated through the AXI bus, thereby combining the AXI bus with an ethernet transmission technology, and realizing efficient, simple and flexible direct data interconnection.

It should be noted that, with the development of the technology, if the on-chip interconnect uses another type of bus (non-AXI bus), the on-chip bus write access request may also be initiated through another type of bus. The embodiment of the present application does not specifically limit what type of bus is used to receive the write access request, and the specific type of bus is not used to limit the protection scope of the embodiment of the present application.

In some exemplary embodiments, the on-die bus write access request includes only valid data.

In further exemplary embodiments, the on-die bus write access request comprises: valid data, valid data length and access address; the access address is an address of valid data in the memory of the second chip, such as an AXI bus write access request.

It should be noted that, if the on-chip bus write access request does not include the valid data length and the access address, the receiving chip needs to use the existing receiving chip to implement the reception of the first ethernet packet, and if the second chip provided in the embodiment of the present application is used to implement the reception, the writing of the valid data cannot be implemented, because the valid data length and the access address are not present in the first ethernet packet, the second chip cannot know where the valid data should be written in the memory; if the write access request includes the valid data length and the access address, the receiving chip may be implemented by using the second chip proposed in the embodiment of the present application.

Step 201, obtaining configuration information of a packaging head.

In some exemplary embodiments, if the write access request includes a valid data length and an access address, the encapsulation header includes: the user-defined head, the user-defined head includes: a valid DATA length DATA _ LEN and an access address DST _ ADDR; if the valid DATA length DATA _ LEN and the access address DST _ ADDR are not included in the write access request, the encapsulation header also does not include a custom header.

In some exemplary embodiments, the custom header further comprises: the reserved field RESERVE. The reserved field may be used to adjust the length of the custom header or fill in other information that needs attention.

It should be noted that the specific positions of the effective DATA length DATA _ LEN and the access address DST _ ADDR in the custom header may be set at will, and the bit width occupied in the custom header may also be set at will.

In some exemplary embodiments, the encapsulation head further comprises at least one of:

an ethernet header, an Internet Protocol (IP) header, a User Datagram Protocol (UDP) header, and a Transmission Control Protocol (TCP) header.

In some exemplary embodiments, the IP may be Internet Protocol Version four (IPV4, Internet Protocol Version 4) or Internet Protocol Version six (IPV6, Internet Protocol Version 6).

In some exemplary embodiments, the configuration information of the package header may be acquired from a CPU of the first chip.

In some exemplary embodiments, the custom head may be carried at any layer. For example, the custom header may be carried over L2 (i.e., data link layer) or L3 (i.e., network layer) or L4 (i.e., transport layer).

Specifically, if the custom header is carried at L2, the format of the encapsulation header is: ethernet head + custom head; then, the configuration information of the encapsulation header includes: configuration information of the Ethernet header and configuration information of the custom header;

if the custom header is carried at L3, the format of the encapsulation header is: ethernet head + IP head + user-defined head; then, the configuration information of the encapsulation header includes: configuration information of Ethernet head, configuration information of IP head and configuration information of self-defined head;

if the custom header is carried at L4, the format of the encapsulation header is: ethernet head + IP head + UDP head or TCP head + custom head; then the configuration information of the encapsulation header includes: configuration information of Ethernet header, configuration information of IP header, configuration information of UDP header or configuration information of TCP header, and configuration information of custom header.

In some exemplary embodiments, the configuration information of the ethernet header includes: media Access Control (MAC) destination address, MAC source address, ethernet type (EtherType) field;

the configuration information of the IP header includes: IP header type (e.g., 4 for IPV4, 6 for IPV6), IP header length, and specific IP header field contents, which are not described in detail herein; configuring the format and content of an IPV4 header to conform to an RFC791 protocol, wherein a Total Length (Total Length) field and a header checksum (HeaderChecksum) field are configured to be 0, and are updated by an Ethernet sending module in the first chip; the format and the content of the configured IPV6 header conform to the RFC8200 protocol, where the load length (PayloadLength) is configured to be 0, and is updated by the ethernet sending module in the first chip;

the format and the content of the configured UDP header conform to the RFC768 protocol, wherein Length (Length) and Checksum (Checksum) fields are configured to be 0 and are updated by an Ethernet sending module in the first chip;

the configuration information of the TCP header conforms to the RFC793 protocol;

the configuration information of the custom header includes: the length of the self-header, the reserved field, DATA _ LEN and DST _ ADDR, where DATA _ LEN and DST _ ADDR are configured as 0, are updated by the ethernet transmit module in the first chip.

Step 202, encapsulating the valid data into a first ethernet packet according to the configuration information of the encapsulation header, and sending the first ethernet packet; wherein the first ethernet packet comprises: a package header and valid data.

Specifically, if the custom header is carried at L2, the format of the first ethernet packet is: ethernet head + custom head + valid data;

if the custom header is carried at L3, the format of the first Ethernet packet is: ethernet head + IP head + user-defined head + effective data;

if the custom header is carried at L4, the format of the first Ethernet packet is: ethernet header + IP header + UDP header or TCP header + custom header + payload data.

In some exemplary embodiments, encapsulating the valid data into the first ethernet packet according to the configuration information of the encapsulation header includes:

selecting at least one of an ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first ethernet packet according to the access address, encapsulating the selected at least one of the ethernet header, the IP header, the UDP header, or the TCP header and the custom header, and the valid data into the first ethernet packet.

In some exemplary embodiments, selecting at least one of an ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first ethernet packet according to the access address comprises:

and searching at least one of an Ethernet header, an IP header, a UDP header or a TCP header which is used for encapsulating the first Ethernet packet and corresponds to the address range where the access address is located in the preset corresponding relation between the at least one of the Ethernet header, the IP header, the UDP header or the TCP header which is used for encapsulating the first Ethernet packet and the address range.

It should be noted that the MAC address and the IP address in at least one of the ethernet header, the IP header, the UDP header, or the TCP header used for encapsulating the first ethernet packet corresponding to different address ranges are different.

It should be noted that, because the MAC address and the IP address of different chips are different, however, the MAC address and the IP address of a chip cannot be known when the first ethernet packet is encapsulated inside the chip, the address ranges of the memories of different chips can be set to non-overlapping areas, so that different chips can be distinguished.

In some exemplary embodiments, if the first chip does not include the first switching module, and the first chip and the second chip do not include a switching chip therebetween, transmitting the first ethernet packet includes: the first ethernet packet is sent to a Media Access Control (MAC) layer, and the MAC layer performs corresponding processing on the first ethernet packet to obtain a second ethernet packet (e.g., adding a Cyclic Redundancy Check (CRC), adding a preamble, adding a padding byte, etc.), and sends the second ethernet packet to the second chip through the first ethernet transmission interface of the first chip. In this way, the reason why the switch chip or the first switch module is not required to implement the transmission of the first ethernet packet is for the case of the topologically simple point-to-point data transmission.

In further exemplary embodiments, if the first chip includes the first switching module and no switching chip is included between the first chip and the second chip, transmitting the first ethernet packet includes: the first Ethernet packet is sent to a first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to an MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the second chip through a first Ethernet transmission interface of the first chip.

In other exemplary embodiments, if a switching chip is included between the first chip and the second chip and the first chip does not include the first switching module, transmitting the first ethernet packet includes: and the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the switching chip through the first Ethernet transmission interface of the first chip.

The switch chip sends the second ethernet packet to the second chip.

In some exemplary embodiments, the first ethernet transmission interface of the first chip may be a standard 50 or 25 or 10 or 5Gbps ethernet transmission interface, and may also be an ethernet transmission interface with other rates, where the specific rate of the first ethernet transmission interface is not limited in this embodiment of the application, and the size of the specific rate is also not used to limit the protection scope of the embodiment of the application.

According to the Data transmission method provided by the embodiment of the application, when the effective Data needs to be sent, the effective Data is directly encapsulated into the first Ethernet packet and sent out, the effective Data does not need to be written into a Double Data Rate (DDR) first, and the bandwidth of the DDR is effectively reduced; the CPU is not needed to participate in the process of transmitting the effective data, namely, extra CPU core resources are not needed to be occupied; therefore, the complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is reduced.

Fig. 3 is a flowchart of a data transmission method according to another embodiment of the present application.

In a second aspect, referring to fig. 3, another embodiment of the present application provides a data transmission method, which is applied to a second chip, where it is to be noted that the second chip refers to a chip that needs to perform inter-chip data transmission, and may specifically be any type of chip, such as a baseband processing chip, a CPU chip, and the like.

The method comprises the following steps:

step 300, receiving a first Ethernet packet; wherein the first ethernet packet comprises: a package header and valid data.

In some exemplary embodiments, if the second chip does not include the second switch module, and the first chip and the second chip do not include a switch chip therebetween, the received first ethernet packet refers to a first ethernet packet obtained after being received through the second ethernet transmission interface of the second chip and being correspondingly processed by the MAC layer of the second chip, and the ethernet packet received by the second ethernet transmission interface of the second chip is a second ethernet packet sent by the first chip.

In some exemplary embodiments, if the second chip includes the second switch module, and the switch chip is not included between the first chip and the second chip, the received first ethernet packet refers to a first ethernet packet received through the second ethernet transmission interface of the second chip, corresponding processing is performed through the MAC layer of the second chip, and the first ethernet packet obtained after transmission is performed through the second switch module of the second chip, and the ethernet packet received through the second ethernet transmission interface of the second chip is a second ethernet packet sent by the first chip.

In some exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the second chip does not include the second switch module, the received first ethernet packet refers to a first ethernet packet obtained after the first ethernet packet is received through the second ethernet transmission interface of the second chip and is subjected to corresponding processing by the MAC layer of the second chip, and the ethernet packet received by the second ethernet transmission interface of the second chip is a second ethernet packet sent by the switch chip between the first chip and the second chip.

In some exemplary embodiments, the second ethernet transmission interface of the second chip may be a standard 50 or 25 or 10 or 5Gbps ethernet transmission interface, and may also be an ethernet transmission interface with other rates, where the specific rate of the second ethernet transmission interface is not limited in this embodiment of the application, and the size of the specific rate is also not used to limit the protection scope of this embodiment of the application.

In some example embodiments, after receiving the first ethernet packet, if it is not time to process the first ethernet packet, the first ethernet packet may be temporarily stored into the RAM.

In some exemplary embodiments, the encapsulation head may or may not include a custom head.

In some exemplary embodiments, the custom header comprises: a valid DATA length DATA _ LEN and an access address DST _ ADDR.

ethernet header, IP header, UDP header, TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV 6.

Step 301, when the encapsulation head includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; the access address is the access address of the valid data in the memory.

In some example embodiments, when the encapsulation header does not include the custom header, the received first ethernet packet may be dropped directly.

In some exemplary embodiments, before obtaining the valid data length and the access address from the first ethernet packet, the method further comprises: acquiring position offset information of a custom header in a first Ethernet packet;

obtaining the valid data length and the access address from the first ethernet packet comprises: and acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information. Specifically, the custom header may be obtained from the first ethernet packet according to the position offset information, and the effective length and the access address may be obtained from the custom header.

In some exemplary embodiments, the position offset information refers to an offset of the custom header from a start position of an encapsulation header of the first ethernet packet.

In some exemplary embodiments, the position offset information of the custom header in the first ethernet packet may be acquired from the CPU.

Step 302, obtaining effective data from the first ethernet packet according to the effective data length, and writing the obtained effective data into the access address.

In some exemplary embodiments, obtaining the valid data from the first ethernet packet according to the valid data length includes: and intercepting the data with the length of the effective data from the payload data of the first Ethernet packet to obtain the effective data.

In some exemplary embodiments, most of currently mainstream chip designs are based on an ARM core, and an AXI bus is used for on-chip interconnection, so that the obtained valid data can be written into an access address through the AXI bus, thereby realizing the combination of the AXI bus and an ethernet transmission technology, and realizing efficient, simple and flexible direct data mutual transmission.

It should be noted that, with the development of the technology, if the on-chip interconnect uses another type of bus (non-AXI bus), the obtained valid data may also be written into the access address through another type of bus. The embodiment of the present application does not specifically limit what type of bus is used to write the obtained valid data into the access address, and the specific type of bus is not used to limit the protection scope of the embodiment of the present application.

Fig. 4 is a block diagram of a chip according to another embodiment of the present disclosure.

In a third aspect, referring to fig. 4, another embodiment of the present application provides a chip, including: at least one Ethernet transmission module; each ethernet transmission module comprises: the on-chip bus write access request receiving submodule 401, the configuration information obtaining submodule 402 and the Ethernet packet encapsulation sending submodule 403;

the on-chip bus write access request receiving submodule 401 is configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data;

a configuration information obtaining sub-module 402, configured to obtain configuration information of the package header;

an ethernet packet encapsulation sending submodule 403, configured to encapsulate the valid data into a first ethernet packet according to the configuration information of the encapsulation header, and send the first ethernet packet; wherein the first ethernet packet comprises: a package header and valid data.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (e.g., the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is data obtained after processing the data and needs to be transmitted to the second chip. That is, the chip further includes:

and the data processing module 404 is configured to perform corresponding processing on the data to obtain valid data, and initiate a write access request of the on-chip bus.

It should be noted that, after the data processing module 404 processes the data, it generally initiates a plurality of times of write access requests of the on-chip bus for the processed data, that is, effective data in each initiated write access request of the on-chip bus is only a small part of the processed data, the data processing module 404 can initiate the write access request of the on-chip bus at regular time, after receiving the write access request of the on-chip bus, if it is too late to process the write access request of the on-chip bus, the write access request of the on-chip bus can be temporarily stored in the RAM of the on-chip bus write access request receiving sub-module 401, because the effective data in the write access request of the on-chip bus is only a small part of the processed data, it does not occupy too much storage space to temporarily store the write access request of the on-chip bus into the RAM of the request receiving sub-module 401, i.e. not much memory space needs to be reserved for the transmission of data.

It should be noted that the size of the valid data in the write access request of the on-chip bus initiated each time may be set at will according to the actual situation, and may be set to be an integer multiple of the bit width of the bus connecting the data processing module 404 and the ethernet sending module in general.

In some exemplary embodiments, because most of currently mainstream chip designs are based on an ARM core, and an AXI bus is used for on-chip interconnection, an on-chip bus write access request can be initiated through the AXI bus, that is, the data processing module 404 and the ethernet sending module are interconnected through the AXI bus, so that the AXI bus and the ethernet transmission technology are combined, and efficient, simple and flexible direct data interconnection is realized.

It should be noted that, with the development of the technology, if the on-chip interconnection uses another type of bus (non-AXI bus), the data processing module 404 and the ethernet sending module may also be connected by another type of bus. The embodiment of the present application does not limit what type of bus is used to connect the data processing module 404 and the ethernet sending module, and the specific type of bus is not used to limit the protection scope of the embodiment of the present application.

In further exemplary embodiments, the on-die bus write access request comprises: valid data and an address range of the valid data in the memory of the second chip.

In further exemplary embodiments, the write access request includes: valid data.

ethernet header, IP header, UDP header, TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV 6.

In some exemplary embodiments, the configuration information of the ethernet header includes: MAC destination address, MAC source address, ethernet type (EtherType) field;

the configuration information of the IP header includes: IP header type (e.g., 4 for IPV4, 6 for IPV6), IP header length, and specific IP header field contents, which are not described in detail herein; configuring the format and content of an IPV4 header to conform to an RFC791 protocol, wherein a Total Length field and a HeaderChecksum field are configured to be 0, and updating is performed by an Ethernet sending module in a first chip; the configured format and content of the IPV6 header conform to the RFC8200 protocol, where the payload length is configured as 0, and is updated by the ethernet sending module in the first chip;

the format and the content of the configured UDP header conform to the RFC768 protocol, wherein the fields of Length and Checksum are configured to be 0, and are updated by an Ethernet sending module in the first chip;

In some exemplary embodiments, the first ethernet packet encapsulation sending sub-module 403 is specifically configured to implement the following steps of encapsulating valid data into the first ethernet packet according to the configuration information of the encapsulation header:

In some exemplary embodiments, the first ethernet packet encapsulation sending sub-module 403 is specifically configured to implement the selection of at least one of an ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first ethernet packet according to the access address in the following manner:

In some exemplary embodiments, if the first chip does not include the first switch module, and the first chip and the second chip do not include a switch chip therebetween, the ethernet packet encapsulation sending sub-module 403 is specifically configured to implement sending the first ethernet packet by: and the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the second chip through the first Ethernet transmission interface of the first chip. In this way, the reason that no switching chip or switching module is required to implement the transmission of the first ethernet packet is for the case of topologically simple point-to-point data transmission. That is, the chip further includes:

and a first ethernet transmission interface 405, configured to send the second ethernet packet output by the MAC layer to the second chip.

In other exemplary embodiments, if the first chip includes the first switch module and the first chip and the second chip do not include a switch chip therebetween, the ethernet packet encapsulation sending sub-module 403 is specifically configured to implement sending the first ethernet packet by: the first Ethernet packet is sent to a first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to an MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the second chip through a first Ethernet transmission interface of the first chip. That is, the chip further includes:

a first switching module 406, configured to send the first ethernet packet output by the ethernet packet encapsulation sending sub-module 403 to the MAC layer, where the MAC layer performs corresponding processing on the first ethernet packet to obtain a second ethernet packet;

In other exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the first chip does not include the first switch module, the ethernet packet encapsulation sending sub-module 403 is specifically configured to implement sending the first ethernet packet by: and the MAC layer performs corresponding processing on the Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the switching chip through the first Ethernet transmission interface of the first chip. That is, the chip further includes:

and a first ethernet transmission interface 405, configured to send the second ethernet packet output by the MAC layer to the switch chip.

The switch chip sends the second ethernet packet to the second chip.

According to the chip provided by the embodiment of the application, when the effective Data needs to be sent, the effective Data is directly packaged into the first Ethernet packet and sent out, the effective Data does not need to be written into a Double Data Rate (DDR) first, and the bandwidth of the DDR is effectively reduced; the CPU is not needed to participate in the process of transmitting the effective data, namely, extra CPU core resources are not needed to be occupied; therefore, the complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is reduced.

It should be noted that all modules and sub-modules on the chip are implemented by Hardware, and may specifically be implemented by a Hardware Description Language (such as Verilog or Very High-Speed Integrated Circuit Hardware Description Language (VHDL)), and the specific implementation Circuit is not limited in this embodiment of the present application, and is not used to limit the protection scope of this embodiment of the present application.

Fig. 5 is a block diagram of a chip according to another embodiment of the present disclosure.

In a fourth aspect, referring to fig. 5, another embodiment of the present application provides a chip, including: at least one ethernet receiving module; each ethernet reception module comprises: an Ethernet packet receiving submodule 501 and a data writing submodule 502;

the ethernet packet receiving submodule 501 is configured to receive a first ethernet packet; wherein the first ethernet packet comprises: a package header and valid data;

a data write submodule 502 for writing data into the package header when the package header includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; the access address is the address of valid data in the memory; and obtaining effective data from the first Ethernet packet according to the effective data length, and writing the obtained effective data into the access address.

In some exemplary embodiments, if the second chip does not include the second switch module, and the first chip and the second chip do not include a switch chip therebetween, the received first ethernet packet refers to a first ethernet packet obtained after being received through the second ethernet transmission interface of the second chip and being correspondingly processed by the MAC layer of the second chip, and the ethernet packet received by the second ethernet transmission interface of the second chip is a second ethernet packet sent by the first chip. That is, the chip further includes:

the second ethernet transmission interface 503 is configured to receive the second ethernet packet sent by the first chip, send the received second ethernet packet to the MAC layer, perform corresponding processing by the MAC layer to obtain a first ethernet packet, and send the first ethernet packet to the ethernet packet receiving sub-module 501.

In some exemplary embodiments, if the second chip includes the second switch module, and the switch chip is not included between the first chip and the second chip, the received first ethernet packet refers to a first ethernet packet received through the second ethernet transmission interface of the second chip, corresponding processing is performed through the MAC layer of the second chip, and the first ethernet packet obtained after transmission is performed through the second switch module of the second chip, and the first ethernet packet received through the second ethernet transmission interface of the second chip is a second ethernet packet sent by the first chip. That is, the chip further includes:

a second ethernet transmission interface 503, configured to receive a second ethernet packet sent by the first chip, send the received second ethernet packet to the MAC layer, obtain a first ethernet packet after the MAC layer performs corresponding processing, and send the first ethernet packet to the second switching module 504;

the second switching module 504 is configured to send the first ethernet packet to the ethernet packet receiving sub-module 501.

In some exemplary embodiments, if a switch chip is included between the first chip and the second chip, and the second chip does not include the second switch module, the received first ethernet packet refers to a first ethernet packet obtained after the first ethernet packet is received through the second ethernet transmission interface of the second chip and is subjected to corresponding processing by the MAC layer of the second chip, and the ethernet packet received by the second ethernet transmission interface of the second chip is a second ethernet packet sent by the switch chip between the first chip and the second chip. That is, the chip further includes:

the second ethernet transmission interface 503 is configured to receive the second ethernet packet sent by the switch chip, send the received second ethernet packet to the MAC layer, perform corresponding processing by the MAC layer to obtain a first ethernet packet, and send the first ethernet packet to the ethernet packet receiving sub-module 501.

In some exemplary embodiments, the second ethernet transmission interface 503 of the second chip may be a standard 50 or 25 or 10 or 5Gbps ethernet transmission interface, and may also be an ethernet transmission interface with other rates, where the specific rate of the second ethernet transmission interface 503 is not limited in this embodiment of the application, and the size of the specific rate is also not used to limit the protection scope of this embodiment of the application.

In some exemplary embodiments, after the ethernet packet receiving submodule 501 receives the first ethernet packet, if the ethernet packet receiving submodule 501 has no time to process the first ethernet packet, the first ethernet packet may be temporarily stored in the RAM of the ethernet packet receiving submodule 501.

It should be noted that the specific positions of the valid DATA length DATA _ LEN and the address range DST _ ADDR in the custom header may be set at will, and the bit width occupied in the custom header may also be set at will.

ethernet header, IP header, UDP header, TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV 6.

In some example embodiments, when the encapsulation header does not include a custom header, the data write submodule 502 may directly discard the received first ethernet packet.

In some exemplary embodiments, the chip further comprises:

a position offset information obtaining module 505, configured to obtain position offset information of the custom header in the first ethernet packet;

the data writing sub-module 502 is specifically configured to obtain the effective data length and the access address from the first ethernet packet by using the following manners: and acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information. Specifically, the custom header may be obtained from the first ethernet packet according to the position offset information, and the effective length and the access address may be obtained from the custom header.

In some exemplary embodiments, most of currently mainstream chip designs are based on an ARM core, and an AXI bus is used for on-chip interconnection, so that data can be connected and written into the sub-module 502 and the memory through the AXI bus, thereby realizing the combination of the AXI bus and an ethernet transmission technology, and realizing efficient, simple and flexible direct data mutual transmission.

It should be noted that, with the development of the technology, if other types of buses are used for on-chip interconnection, the data write sub-module 502 and the memory may also be connected through other types of buses. In the embodiment of the present application, there is no limitation on what type of bus is used to connect the data write submodule 502 and the memory, and the specific type of bus is not used to limit the protection scope of the embodiment of the present application.

According to the chip provided by the embodiment of the application, when the first Ethernet packet is received, the effective data is directly obtained from the first Ethernet packet and written into the corresponding access address, the first Ethernet packet does not need to be analyzed and classified, and the logic is simpler to realize, so that the complexity of chip design is reduced, the area and the power consumption of the chip are effectively reduced, and the cost of the chip is also reduced.

It should be noted that all modules and sub-modules on the chip are implemented by hardware, and may specifically be implemented by using a hardware description language (such as Verilog or VHDL), and the specific implementation circuit is not limited in this embodiment of the present application, and is not used to limit the protection scope of this embodiment of the present application.

In a fifth aspect, another embodiment of the present application provides a chip, including: at least one ethernet sending module of any kind above, and at least one ethernet receiving module of any kind above.

Fig. 6 is a block diagram of a data transmission system according to another embodiment of the present application.

In a sixth aspect, referring to fig. 6, another embodiment of the present application provides a data transmission system, including:

a first chip 601, configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data; acquiring configuration information of a packaging head; according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data;

the third chip 602 is configured to receive the first ethernet packet, write the first ethernet packet into a randomly allocated address in the memory, classify the first ethernet packet, and then queue the first ethernet packet in a queue designated by the central processing unit.

In some exemplary embodiments, the on-chip bus write access request may be initiated by any other data processing module (e.g., the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is data obtained after processing the data and needs to be transmitted to the second chip. That is, the first chip 601 is also used to:

and correspondingly processing the data to obtain effective data, and initiating an on-chip bus write access request.

It should be noted that after the first chip 601 processes data, it generally initiates multiple times of intra-chip bus write access requests for the processed data, that is, valid data in each initiated intra-chip bus write access request is only a small part of the processed data, the first chip 601 may initiate the intra-chip bus write access request at regular time, after receiving the on-chip bus write access request, if the on-chip bus write access request is not ready to be processed, the on-chip bus write access request may be temporarily stored in the RAM of the first chip 601, since the valid data in the on-chip bus write access request is only a small portion of the processed data, therefore, temporarily storing the on-chip bus write access request in the RAM of the first chip 601 does not take up much memory space, i.e. does not require much memory space to be reserved for the transmission of data.

It should be noted that, with the development of the technology, if other types of buses are used for the on-chip interconnection, the data processing module 404 and the ethernet sending module may also be connected through other types of buses. The embodiment of the present application does not limit what type of bus is used to connect the data processing module 404 and the ethernet sending module, and the specific type of bus is not used to limit the protection scope of the embodiment of the present application.

In further exemplary embodiments, the on-die bus write access request comprises: valid data, valid data length, and access address.

In some exemplary embodiments, the encapsulation head comprises at least one of:

ethernet header, IP header, UDP header, TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV 6.

In some exemplary embodiments, if the first chip does not include the first switch module, and the first chip and the third chip do not include a switch chip therebetween, the first chip 601 is specifically configured to implement sending the first ethernet packet by: and the MAC layer performs corresponding processing on the Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the third chip through the first Ethernet transmission interface of the first chip. In this way, the reason that no switching chip or switching module is required to implement the transmission of the first ethernet packet is for the case of topologically simple point-to-point data transmission.

In other exemplary embodiments, if the first chip includes the first switch module and the first chip and the third chip do not include a switch chip therebetween, the first chip 601 is specifically configured to implement sending the first ethernet packet by: and the first Ethernet packet is sent to a first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to an MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to a third chip through a first Ethernet transmission interface of the first chip.

In other exemplary embodiments, if the first chip and the third chip include the switch chip 603 therebetween and the first chip does not include the first switch module, the first chip 601 is specifically configured to implement sending the first ethernet packet by: the first ethernet packet is sent to the MAC layer, and the MAC layer performs corresponding processing on the ethernet packet to obtain a second ethernet packet, and sends the second ethernet packet to the switch chip 603 through the first ethernet transmission interface of the first chip.

And a switch chip 603 for transmitting the second ethernet packet to the third chip.

In a seventh aspect, referring to fig. 7, another embodiment of the present application provides a data transmission system, including:

a first chip 701, configured to receive an on-chip bus write access request; wherein, the on-chip bus write access request comprises: valid data, a valid data length, and an access address; acquiring configuration information of a packaging head; according to the configuration information of the encapsulation head, the effective data is encapsulated into a first Ethernet packet, and the first Ethernet packet is sent; wherein the first ethernet packet comprises: a package header and valid data; the packaging head includes: the user-defined head, the user-defined head includes: effective data length and access address;

a second chip 701, configured to receive a first ethernet packet; wherein the first ethernet packet comprises: a package header and valid data; when the package head includes: the user-defined head, the user-defined head includes: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; and obtaining effective data from the first Ethernet packet according to the effective data length, and writing the obtained effective data into the access address.

In some exemplary embodiments, the write access request may be initiated by any other data processing module (e.g., the aforementioned SUBSYS) in the first chip after processing the data, and the valid data is data obtained after processing the data and needs to be transmitted to the second chip. That is, the first chip 601 is also used to:

and correspondingly processing the data to obtain effective data, and initiating a write access request.

ethernet header, IP header, UDP header, TCP header.

In some exemplary embodiments, the IP may be IPV4 or IPV 6.

In some exemplary embodiments, the first chip 601 is specifically configured to implement the following method for encapsulating the valid data into the first ethernet packet according to the configuration information of the encapsulation header:

In some exemplary embodiments, the first chip 601 is specifically configured to implement the selection of at least one of an ethernet header, an IP header, a UDP header, or a TCP header for encapsulating the first ethernet packet according to the access address in the following manner:

In some exemplary embodiments, if the first chip does not include the first switch module, and the first chip and the second chip do not include a switch chip therebetween, the first chip 601 is specifically configured to implement sending the first ethernet packet by: and the MAC layer performs corresponding processing on the Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the second chip through the first Ethernet transmission interface of the first chip. In this way, the reason that no switching chip or switching module is required to implement the transmission of the first ethernet packet is for the case of topologically simple point-to-point data transmission.

In other exemplary embodiments, if the first chip includes the first switch module and the first chip and the second chip do not include a switch chip therebetween, the first chip 601 is specifically configured to implement sending the first ethernet packet by: the first Ethernet packet is sent to a first switching module of the first chip, the first switching module of the first chip sends the first Ethernet packet to an MAC layer, the MAC layer performs corresponding processing on the first Ethernet packet to obtain a second Ethernet packet, and the second Ethernet packet is sent to the second chip through a first Ethernet transmission interface of the first chip.

In other exemplary embodiments, if the first chip and the second chip include the switch chip 603 therebetween and the first chip does not include the first switch module, the first chip 601 is specifically configured to implement sending the first ethernet packet by: the first ethernet packet is sent to the MAC layer, and the MAC layer performs corresponding processing on the ethernet packet to obtain a second ethernet packet, and sends the second ethernet packet to the switch chip 603 through the first ethernet transmission interface of the first chip.

And a switch chip 603 configured to send the second ethernet packet to the second chip for the second ethernet packet.

In some exemplary embodiments, after the second chip 701 receives the first ethernet packet, if the second chip 701 has no time to process the first ethernet packet, the first ethernet packet may be temporarily stored in the RAM of the second chip 701.

In some example embodiments, when the encapsulation header does not include the custom header, the second chip 701 may directly discard the received first ethernet packet.

In some exemplary embodiments, the second chip 701 is further configured to:

acquiring position offset information of a custom header in a first Ethernet packet;

the second chip 701 is specifically configured to obtain the effective data length and the access address from the first ethernet packet by using the following manners: and acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information. Specifically, the custom header may be obtained from the first ethernet packet according to the position offset information, and the effective length and the access address may be obtained from the custom header.

According to the Data transmission system provided by the embodiment of the application, when the effective Data needs to be sent, the effective Data is directly encapsulated into the first Ethernet packet and sent out, the effective Data does not need to be written into a Double Data Rate (DDR) first, and the bandwidth of the DDR is effectively reduced; the CPU is not needed to participate in the process of transmitting the effective data, namely, extra CPU core resources are not needed to be occupied; therefore, the complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is reduced. When the first Ethernet packet is received, the effective data is directly obtained from the first Ethernet packet and written into the corresponding access address, the first Ethernet packet does not need to be analyzed and classified, and the logic is simple, so that the complexity of chip design is reduced, the area and power consumption of the chip are effectively reduced, and the cost of the chip is also reduced.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the application as set forth in the appended claims.

Claims

1. A data transmission method is applied to a first chip and comprises the following steps:

receiving a write access request of an on-chip bus; wherein the on-chip bus write access request comprises: valid data;

acquiring configuration information of a packaging head;

packaging the effective data into a first Ethernet packet according to the configuration information of the packaging head, and sending the first Ethernet packet; wherein the first Ethernet packet comprises: the encapsulation header and the valid data.

2. The data transfer method of claim 1, wherein the on-die bus write access request further comprises: an access address and a valid data length; the access address is the address of the effective data in the memory of the second chip;

the packaging head includes: a custom head, the custom head comprising: the effective data length and the access address.

3. The data transmission method of claim 2, wherein the custom header further comprises: fields are reserved.

4. The data transmission method of claim 2, wherein the encapsulation head further comprises at least one of:

ethernet head, Internet protocol head, user datagram protocol head, transmission control protocol head.

5. A data transmission method is applied to a second chip, and comprises the following steps:

when the packaging head includes: a custom head, the custom head comprising: when the effective data length and the access address are available, the effective data length and the access address are obtained from the first Ethernet packet; the access address is the address of the effective data in the memory of the second chip;

6. The data transmission method according to claim 5, wherein before the obtaining the valid data length and the access address from the first ethernet packet, the method further comprises: acquiring position offset information of the custom header in the first Ethernet packet;

the obtaining the valid data length and the access address from the first ethernet packet includes: and acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information.

7. A chip, comprising: at least one Ethernet transmission module; each of the ethernet transmission modules includes: the on-chip bus write access request receiving submodule, the configuration information obtaining submodule and the Ethernet packet packaging and sending submodule;

the on-chip bus write access request receiving submodule is used for receiving an on-chip bus write access request; wherein the on-chip bus write access request comprises: valid data;

the configuration information acquisition submodule is used for acquiring configuration information of the packaging head;

the ethernet packet encapsulation sending submodule is configured to encapsulate the valid data into a first ethernet packet according to the configuration information of the encapsulation header, and send the first ethernet packet; wherein the first Ethernet packet comprises: the encapsulation header and the valid data.

8. The chip of claim 7, wherein the on-die bus write access request further comprises: an access address and a valid data length; the access address is the address of the effective data in the memory of the second chip;

9. A chip, comprising: at least one ethernet receiving module; each of the ethernet reception modules includes: the Ethernet packet receiving submodule and the data writing submodule;

the data writing submodule is used for:

10. The chip of claim 9, wherein the ethernet receive module further comprises: a position offset information acquisition submodule;

the position offset information obtaining submodule is used for obtaining the position offset information of the custom header in the first Ethernet packet;

the data writing submodule is specifically configured to implement the following method to obtain the effective data length and the access address from the first ethernet packet: and acquiring the effective data length and the access address from the first Ethernet packet according to the position offset information.

11. A chip, comprising: at least one ethernet transmit module according to any of claims 7-8 and at least one ethernet receive module according to any of claims 9-10.

12. A data transmission system comprising:

a first chip to:

acquiring configuration information of a packaging head;

packaging the effective data into a first Ethernet packet according to the configuration information of the packaging head, and sending the first Ethernet packet; wherein the first Ethernet packet comprises: the encapsulation header and the valid data;

a third chip to:

receiving a first Ethernet packet, writing the first Ethernet packet into a randomly allocated address in a memory, classifying the first Ethernet packet, and then queuing the first Ethernet packet into a queue appointed by a central processing unit.

13. A data transmission system comprising:

a first chip to:

receiving a write access request of an on-chip bus; wherein the on-chip bus write access request comprises: valid data, a valid data length, and an access address; the access address is the address of the effective data in the memory of the second chip;

acquiring configuration information of a packaging head;

packaging the effective data into a first Ethernet packet according to the configuration information of the packaging head, and sending the first Ethernet packet; wherein the first Ethernet packet comprises: the encapsulation header and the valid data; the packaging head includes:

a custom head, the custom head comprising: the effective data length and the access address;

a second chip to:

receiving a first Ethernet packet;

acquiring the effective data length and the access address from the first Ethernet packet;