CN110334040A - A kind of spaceborne solid-state memory system - Google Patents
A kind of spaceborne solid-state memory system Download PDFInfo
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- CN110334040A CN110334040A CN201910613513.2A CN201910613513A CN110334040A CN 110334040 A CN110334040 A CN 110334040A CN 201910613513 A CN201910613513 A CN 201910613513A CN 110334040 A CN110334040 A CN 110334040A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Abstract
The invention belongs to Onboard Solid technical field, in particular to a kind of spaceborne solid-state memory system, comprising: the master cpu module that is arranged on CPU, the storage control module being arranged on FPGA and FLASH array；The FLASH array includes several FLASH memories；Configuration-direct for generating configuration-direct according to the data address in the instruction of the earth station's transmitting received and FLASH array, and is sent to storage control module by the master cpu module；The storage control module for receiving the data source packet of payload generation, and is carried out RS Error Correction of Coding, the data source packet after Error Correction of Coding is stored in several FLASH memories；According to the configuration-direct received, data source packet after extracting the corresponding Error Correction of Coding being stored in FLASH memory, and RS decoding processing carried out to the data source packet after Error Correction of Coding, and decoding treated data source packet by several transmission transmitters is transmitted back to earth station.
Description
Technical field
The invention belongs to aerospace craft electronic system, Onboard Solid, Aeronautics and Astronautics electronic data processing, deposit
Storage and transmission technique field, in particular to a kind of spaceborne solid-state memory system.
Background technique
Currently, the storage medium of mainstream is NAND type FLASH on spacecraft.It has the advantages that protrude as follows: data are non-
Volatibility, power failure data are not lost；Small power consumption, it is not powered to keep data for a long time；Service life is long, and erasable number is up to 100,000
It is secondary；Density is big, and single-chip can reach 1GB or more, single closed assembly module capacity 8GB or more.Just because of these advantages, it is wide
It is general to be applied in the development of Onboard Solid.
The function of spaceborne Solid State Storage Controller has:
1. receiving the science data of external payload input and the satellite engineering parameter from upper layer house keeping computer；
2. the data received are wrapped according to corresponding telemetering source bag data format composition data source respectively, later to data source
Packet carries out RS Error Correction of Coding；
3. the data source packet after coding is pressed load data, Star Service engineering parameter partition cache, and independently it is deposited into FLASH
In fixed partition in memory；
4. generating the operation signals such as reading and writing, the erasing of FLASH memory；
5. detecting the information of the errors such as memory block inside programming, erasing, the page and block of error are marked, and by outer
It interrupts forms of application and notifies software in time in portion；
6. can be started by software command for operations such as on-demand playback, the erasings of the specified memory block FLASH；
7. having the register for indicating hardware effort state and interrupt status, and it can be read from particular address by software
Content；
8. playback of data passes through RS error-correcting decoding, and exports to multiple connection module；
9. producing " block allocation table " (BAT) of reflection all pieces of memory block service condition, and can be by software from specifiedly
It reads location.
Spaceborne solid-state memory system function is complicated and reliability requirement is high, and existing technology, which generallys use, refers to every CPU
Corresponding register is all established in order in FPGA, and FPGA completes command communication by reading register.Therefore, spaceborne solid-state storage
The design on hardware and software of system is all extremely complex, increases the complexity and cost of system.With spaceborne solid-state memory system
The continuous improvement of integrated level and complexity, the prior art will lead to the design of spaceborne solid-state memory system, integrated, test and after
The difficulty of phase edition upgrading further increases.In addition, the prior art is unable to complete to different FLASH chip producers, difference FLASH
Chip capacity, and different closed assembly configuration NAND type FLASH storage array support.
Summary of the invention
It is an object of the present invention to which to solve drawbacks described above existing for existing spaceborne solid-state memory system, the present invention is mentioned
A kind of spaceborne solid-state memory system is gone out, APB can not be used for each functional module in spaceborne solid-state memory system by overcoming
Bus supports the online configurable functionality of parameter come the technical issues of be managed collectively and dispatched.Overcome simultaneously existing
The technical problems such as lengthy and tedious complexity, poor universality existing for spaceborne solid-state memory system, difficult upgrading, difficult maintenance, at high cost, to mention
For a kind of standardization, spaceborne solid-state memory system configurable, at low cost and general.
To achieve the goals above, the invention proposes a kind of spaceborne solid-state memory system, which includes: that setting exists
Master cpu module on CPU, the storage control module being arranged on FPGA and FLASH array；The FLASH array includes
Several FLASH memories；
The master cpu module, for according to the data in the instruction of the earth station's transmitting received and FLASH array
Location generates configuration-direct, and configuration-direct is sent to storage control module；
The storage control module for receiving the data source packet of payload generation, and is carried out RS Error Correction of Coding,
Data source packet after Error Correction of Coding is stored in several FLASH memories；
Data according to the configuration-direct received, after extracting the corresponding Error Correction of Coding being stored in FLASH memory
Source packet, and RS decoding processing is carried out to the data source packet after Error Correction of Coding, and decoding treated data source packet is passed by number
Transmitter is transmitted back to earth station.
One of as an improvement of the above technical solution, pass through advanced peripheral bus between CPU, FPGA, FLASH array
Connection, and the communication between three is realized by advanced peripheral bus；HPI interface is used between the CPU and FPGA.
One of as an improvement of the above technical solution, the storage control module specifically includes: combining input submodule is deposited
Storage operation submodule, multiple connection output sub-module and APB bridge submodule；
The combining input submodule, for receive the multipath high-speed parallel data generated from extraneous payload and
Satellite engineering parameter from upper layer house keeping computer；Received multipath high-speed parallel data is grouped, every group of data sheet
Only composition data source packet, and RS Error Correction of Coding is carried out to data source packet, the data source packet after Error Correction of Coding is cached, is obtained
Data source packet after caching；And the data source packet after caching is exported to storage and operates submodule；Wherein, the data source packet
Include the data of payload generation and the satellite engineering parameter packet from Star Service；
The storage operates submodule, for initializing to the FLASH memory in FLASH array；It is also used to pair
The data address in data source packet after caching is configured, data write-in, organizes BAT table, data erasing, marked invalid, number
According to playback operation, data source packet after being operated, and the data source packet after operation is stored to several FLASH memories；Root
According to the configuration-direct received, data source packet after extracting the corresponding Error Correction of Coding being stored in FLASH memory, and to entangling
Data source packet after miscoding carries out RS decoding processing, and will decoding treated that data source packet is sent to multiple connection output submodule
Block；
The multiple connection output sub-module, for the data source packet progress data buffer storage that will decode that treated, and with document number,
Timing code collectively constitutes data framing, output to several transmission transmitters；
The APB bridge submodule, for completing the communication between CPU and FPGA.
One of as an improvement of the above technical solution, the storage operation submodule specifically includes: APB administrative unit is closed
Road input unit, RAM cache unit, FLASH control unit, BAT RAM cache unit and multiple connection output unit；
The APB administrative unit, for being managed to each unit in storage control submodule；
The combining input unit, for carrying out RS Error Correction of Coding to data source packet, the data source after obtaining Error Correction of Coding
Data source packet after Error Correction of Coding is sent into asynchronous FIFO and cached by packet, and the data source packet after caching is sent to RAM caching
Unit；
The RAM cache unit, for carrying out secondary caching to the data source packet after caching, by the data after secondary caching
Source packet is sent to FLASH control unit；
The FLASH control unit, for several FLASH memories to be carried out with initialization and parameter configuration, storage respectively
Data source packet after Error Correction of Coding；It is also used to tissue BAT (Block Assignment Table, block allocation table) information, by BAT
Information is sent to BAT RAM cache unit；Write-in, playback, erasing and the mark of data source packet after being also used to execute Error Correction of Coding
Remember invalid operation, the data source packet after being operated；
The BAT RAM cache unit for storing the BAT information of FLASH control unit transmission, and is sent it to
APB administrative unit；
The multiple connection output unit, the data source packet after the Error Correction of Coding for exporting to FLASH control unit carry out RS
Decoding caches the data source packet write-in asynchronous FIFO after decoding.
One of as an improvement of the above technical solution, the FLASH control unit specifically includes: initialization and parameter configuration
Subelement, data write-in subelement, tissue BAT table subelement, data erasing subelement, marked invalid subelement and data readback
Subelement；
The initialization and parameter configuration subelement, for several FLASH memories in NAND FLASH array point
Not carry out initialization scan, generate corresponding FLASH bad block message, and to the configurable parameter of storage system carry out configuration and
Data address in data source packet after caching is configured；
Subelement is written in the data, for being written in the data source packet after caching according to configured data address
Data；
The tissue BAT table subelement, for the FLASH bad block message generated in & parameter configuration subelement will to be initialized
Blocking allocation table information, i.e. BAT information are formed, and the BAT information is sent to BAT RAM cache unit；
The data wipe subelement, will when writing full FLASH memory for the data in the data source packet after caching
The data initially write are wiped；
The marked invalid subelement is found a certain in FLASH memory for being written or wiping in data procedures
When block can not be written or wipe data, this part is labeled as invalid block；When executing write-in or erasing operation next time, will skip
This part；
The data readback subelement, the configuration-direct for being sent according to master cpu module extract corresponding be stored in
Data source packet after Error Correction of Coding in FLASH memory, and the data source packet after Error Correction of Coding is exported to multiple connection and exports list
Member.
One of as an improvement of the above technical solution, the outside of the storage control module is additionally provided with external interface, is used for
Communication is attached with corresponding hardware；
The external interface includes: that Data Input Interface, storage control interface, transmission frame output interface, CAN communication connect
Mouth, AD telemetry-acquisition interface, master cpu unit interface, OC instruct output interface, digital dock interface；
The Data Input Interface receives the number generated from extraneous payload for receiving chip by LVDS
According to；Chip is received by asynchronous RS422, receives the satellite engineering parameter packet from Star Service；By payload generate data and
Satellite engineering parameter packet from Star Service, composition data source packet；
The storage control interface is used for according to status bus, control bus and data/address bus, by the number after Error Correction of Coding
Several FLASH memories into FLASH array are stored according to source packet；
The transmission frame output interface, for being exported data framing to several transmission transmitters by LVDS chip；
The CAN communication interface, for receiving the number teletype command and timecode information of house keeping computer transmission；It is also used to connect
Receive the parameter configuration instruction that master cpu module is sent.
One of as an improvement of the above technical solution, the FLASH control unit further include: parameter configuration layer；For propping up
Hold different FLASH chip producers, different FLASH chip capacity, and the NAND type FLASH storage array of different closed assembly configurations.
The parameter configuration layer includes: parameter configuration instruction resolution unit and parameter configuration unit；
The parameter configuration instructs resolution unit, for parsing the configuration information for being stored in the data source packet of FLASH；
The parameter configuration storage unit, for the parameter configuration instruction after storing and resolving.
The beneficial effect of the present invention compared with the prior art is:
(1) compatibility is high, supports different FLASH chip producers, different FLASH chip capacity, and different closed assembly configurations
NAND type FLASH storage array；
(2) integrated level is high, reduces the workload and complexity of CPU software and FPGA software；
(3) Project Realization is simple, at low cost.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of spaceborne solid-state memory system of the invention；
Fig. 2 is a kind of concrete structure schematic diagram of spaceborne solid-state memory system of the invention；
Fig. 3 is a kind of external interface schematic diagram of spaceborne solid-state memory system of the invention；
Fig. 4 is a kind of parameter configuration layer parameter configuration-direct resolution unit state of spaceborne solid-state memory system of the invention
Figure；
Fig. 5 is a kind of schematic diagram of the parameter configuration layer parameter configuration unit of spaceborne solid-state memory system of the invention.
Specific embodiment
Now in conjunction with attached drawing, the invention will be further described.
As illustrated in fig. 1 and 2, the invention proposes a kind of spaceborne solid-state memory system, which includes: to be arranged in CPU
Master cpu module, setting on (Central Processing Unit, central processing unit) is in FPGA (Field
Programmable Gate Array, field programmable gate array) on storage control module and NAND type FLASH
Array；
The master cpu module, for according to the data in the instruction of the earth station's transmitting received and FLASH array
Location generates configuration-direct, and configuration-direct is sent to storage control module；
The storage control module for receiving the data source packet of payload generation, and is carried out RS (Reed-
Solomon code, Reed Solomon code) Error Correction of Coding, the data source packet after Error Correction of Coding is stored in several FLASH and is deposited
In reservoir；
Data according to the configuration-direct received, after extracting the corresponding Error Correction of Coding being stored in FLASH memory
Source packet, and RS decoding processing carried out to the data source packet after Error Correction of Coding, and will decoding treated that data source packet is exported to number
Transmission transmitter, mode, is transmitted back to earth station by wireless communication.
The FLASH array includes several FLASH memories；It is total by advanced peripheral between CPU, FPGA, FLASH array
Line (Advanced Peripheral Bus, APB bus) connection, and the communication between three is realized by advanced peripheral bus；
HPI interface is used between the CPU and FPGA.
The storage control module specifically includes: combining input submodule, storage operation submodule, multiple connection output sub-module
With APB bridge submodule；
The combining input submodule, for receive the multipath high-speed parallel data generated from extraneous payload and
Satellite engineering parameter from upper layer house keeping computer；Received multipath high-speed parallel data is grouped, every group of data sheet
Only composition data source packet, and RS Error Correction of Coding is carried out to data source packet, the data source packet after Error Correction of Coding is sent into asynchronous FIFO
It is cached, the data source packet after being cached；And the data source packet after caching is exported to storage and operates submodule；
The storage operates submodule, for initializing to the FLASH memory in FLASH array；It is also used to pair
The data address in data source packet after caching is configured, data write-in, organizes BAT table, data erasing, marked invalid, number
According to playback operation, data source packet after being operated, and the data source packet after operation is stored to several FLASH memories；Root
According to the configuration-direct received, data source packet after extracting the corresponding Error Correction of Coding being stored in FLASH memory, and to entangling
Data source packet after miscoding carries out RS decoding processing, and will decoding treated that data source packet is sent to multiple connection output submodule
Block；
Wherein, storage operation submodule specifically includes: APB administrative unit, combining input unit, RAM cache unit,
FLASH control unit, BAT RAM cache unit and multiple connection output unit；
The APB administrative unit, for being managed to each unit in storage control submodule.Wherein, each unit is made
It is Slave carry in APB bus, APB administrative unit generates address decoding gating signal, to gate corresponding Slave.Work as receipts
To master cpu module send configuration-direct when, gate corresponding Slave, and the configuration-direct is written to each functional unit
In pre-define register in.Subsequent each functional unit reads the instruction in corresponding registers by internal APB bus；It is also used to
Receive the BAT information exported from BAT RAM cache unit.
The combining input unit, for carrying out RS Error Correction of Coding to data source packet, the data source after obtaining Error Correction of Coding
Data source packet after Error Correction of Coding is sent into asynchronous FIFO and cached by packet, and the data source packet after caching is sent to RAM caching
Unit；
The RAM cache unit, for carrying out secondary caching to the data source packet after caching, by the data after secondary caching
Source packet is sent to FLASH control unit；
The FLASH control unit stores Error Correction of Coding for carrying out initialization and parameter configuration to FLASH memory
Data source packet afterwards；It is also used to tissue BAT (Block Assignment Table, block allocation table) information, BAT information is sent
To BAT RAM cache unit；Write-in, playback, erasing and the marked invalid behaviour of data source packet after being also used to execute Error Correction of Coding
Make, the data source packet after being operated；
Wherein, the FLASH control unit specifically includes: initialization with parameter configuration subelement, data write-in subelement,
Organize BAT table subelement, data erasing subelement, marked invalid subelement and data readback subelement；
The initialization and parameter configuration subelement, for several FLASH memories in NAND FLASH array point
Not carry out initialization scan, generate corresponding FLASH bad block message, and to the configurable parameter of storage system carry out configuration and
Data address in data source packet after caching is configured；
Subelement is written in the data, for being written in the data source packet after caching according to configured data address
Data；
The tissue BAT table subelement, for the FLASH bad block message generated in & parameter configuration subelement will to be initialized
Blocking allocation table information, i.e. BAT information are formed, and the BAT information is sent to BAT RAM cache unit；
The data wipe subelement, will when writing full FLASH memory for the data in the data source packet after caching
The data initially write are wiped；
The marked invalid subelement is found a certain in FLASH memory for being written or wiping in data procedures
When block can not be written or wipe data, this part is labeled as invalid block；When executing write-in or erasing operation next time, will skip
This part；
The data readback subelement, the configuration-direct for being sent according to master cpu module extract corresponding be stored in
Data source packet after Error Correction of Coding in FLASH memory, and the data source packet after Error Correction of Coding is exported to multiple connection and exports list
Member；
Wherein, the FLASH control unit further include: parameter configuration layer；Configurable and general sexual function is matched by parameter
Layer is set to realize, for supporting different FLASH chip producers, different FLASH chip capacity, and the NAND of different closed assembly configurations
Type FLASH storage array.The parameter configuration layer includes: parameter configuration instruction resolution unit and parameter configuration storage unit；
The parameter configuration instruction of specific configurable parameter and storage system is shown in Table 1.Parameter configuration instruction length be
16bit, including internal time parameter, operand bit, FLASH memory quantity, block number, number of pages and page size etc..
1 parameter configuration of table instructs (ssr_cfg)
The parameter configuration instructs resolution unit, as shown in Figure 4.Matched for parsing by the parameter that master cpu module is sent
Set instruction；Specifically, referred to using the finite state machine (FSM) with arbitration circuit come the parameter configuration sent to master cpu module
Order is parsed.When beginning, reset state machine is in idle condition (idle), at this time with no authorized signal.Match when receiving parameter
After setting instruction (ssr_cfg), ssr_cfg the 0th is instructed to parameter configuration and is parsed, and generates 1 grade of authorization signal 1xx,
State transition will complete the configuration for " page size " in storage control module to gnt1 under gnt1 state immediately.When
After parameter configuration operation under gnt1 state executes completion, 2 grades of authorization signal x1x are generated, state transition to gnt2 carries out
The configuration of " number of pages in block " in FLASH memory generates next stage authorization signal after completing, reciprocal with this, joins until 7
Number configuration-direct is all parsed, and the initialization of FLASH array is completed.
The parameter configuration storage unit, as shown in Figure 5.For the parameter configuration instruction after storing and resolving；Specifically, often
Primary parameter configuration operation is all that a register is controlled by a multiple selector to realize to the configuration ginseng after parsing
Several storages.Authorization signal is connected to the enable end of multiple selector, and when this grade of authorization signal arrives, enable end is set to 1.
Which configuration parameter is deposited into register by the content decision that multiple selector is instructed according to parameter configuration.
For parameter configuration instruction bit0~bit6 (gnt1~gnt5), only in storage control module operatively
Location is related, therefore, sets maximum value in configuration parameter for the default action address of page programming and page playback.It is write carrying out data
During entering with playback, each configuration parameter registers can be successively accessed according to priority first, are posted when having read configuration parameter
After storage, the high address taken less than in the operation such as read-write can be shielded on the basis of reading configuration parameter.
The configuration of internal time parameter and operand bit (gnt6~gnt7) wants more complex, therefore, in exploitation, adopts
The code in unit each in storage control module about time parameter and operand bit is packaged with the thought of code block
It (is placed among the same process) at a code block, and a code block is generated to every kind of configuration parameter situation.Joined
When number configuration, the configuration parameter in parameter configuration register is read first, it is corresponding according to parameter instruction selection is read later
Code is executed, and the configuration to storage control module internal time parameter and operand bit is completed.When the parameter configuration is complete
Cheng Houhui generates shielded signal, and the code block that do not use under the parameter is shielded.Storage control module carries out a new round
It when operation, no longer needs to traverse the code block under every kind of configuring condition, but directly reads the parameter in parameter configuration register, hold
The corresponding code block of row.Since configuration parameter is stored in register, no longer needed to when system carries out subsequent operation
Parameter configuration instruction is parsed.The complexity of storage control had not only been reduced in this way but also by parameter configuration operation to storage speed
The influence of rate falls below minimum.
The BAT RAM cache unit for storing the BAT information of FLASH control unit transmission, and is sent it to
APB administrative unit, master cpu module send parameter configuration and instruct to APB administrative unit, and APB administrative unit is according to master cpu mould
The parameter configuration instruction that block is sent configures corresponding FLASH memory with received BAT information, stores corresponding data source
Packet；
The multiple connection output unit, the data source packet after the Error Correction of Coding for exporting to FLASH control unit carry out RS
Decoding caches the data source packet write-in asynchronous FIFO after decoding.
Specifically, when the data volume of the data source packet after the caching reaches FLASH one page size, start FLASH
Page programming, to after the caching for reaching FLASH one page data source packet carry out data address configuration, data write-in, tissue BAT table,
Data erasing, marked invalid operation, are deposited into NAND FLASH array, then operated by data readback, are stored into NAND
Data source packet in FLASH array is loaded onto multiple connection output subelement；
The multiple connection output sub-module, for the data source packet progress data buffer storage that will decode that treated, and with document number,
Timing code collectively constitutes data framing, output to several transmission transmitters；
The APB bridge submodule has been also used to for each submodule in storage control module to be managed and dispatched
At the communication between CPU and FPGA.Wherein, the communication of the two is completed between FPGA and CPU by APB bridge.
As shown in figure 3, the outside of the storage control module is additionally provided with external interface, for carrying out with corresponding hardware
Connection communication；
The external interface includes: that Data Input Interface, storage control interface, transmission frame output interface, CAN communication connect
Mouth, AD telemetry-acquisition interface, master cpu unit interface, OC instruct output interface, digital dock interface；
The Data Input Interface receives the number generated from extraneous payload for receiving chip by LVDS
According to；Chip is received by asynchronous RS422, receives the satellite engineering parameter packet from Star Service；By payload generate data and
Satellite engineering parameter packet from Star Service, composition data source packet；
The storage control interface is used for according to status bus, control bus and data/address bus, by the number after Error Correction of Coding
Several FLASH memories into FLASH array are stored according to source packet；
The transmission frame output interface, for being exported data framing to several transmission transmitters by LVDS chip；
The CAN communication interface, for receiving the number teletype command and timecode information of house keeping computer transmission；It is also used to connect
Receive the parameter configuration instruction that master cpu module is sent；
The AD telemetry-acquisition interface, for by completing to the temperature of CPU and the temperature of FPGA to AD circuit control management
The telemetry-acquisition of degree, and it is forwarded to master cpu module；
The master cpu module interface, inquired for realizing the input of combining multiple connection storage dependent instruction word, status word,
BAT table is read, storage is read and write, Solid State Storage Controller work ginseng is inputted, interrupted etc.；
The OC instructs output interface, for generating OC control instruction according to the instruction of master cpu module, generates after parsing
Corresponding OC command pulse is sent to peripheral OC chip to control modulation power source to number transmission transmitter and add power-off.
It should be noted last that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting.Although ginseng
It is described the invention in detail according to embodiment, those skilled in the art should understand that, to technical side of the invention
Case is modified or replaced equivalently, and without departure from the spirit and scope of technical solution of the present invention, should all be covered in the present invention
Scope of the claims in.
Claims (7)
1. a kind of spaceborne solid-state memory system, which is characterized in that the system includes: the master cpu module being arranged on CPU, sets
Set storage control module and FLASH array on FPGA；The FLASH array includes several FLASH memories；
The master cpu module, for raw according to the data address in the instruction of the earth station's transmitting received and FLASH array
Storage control module is sent at configuration-direct, and by configuration-direct；
The storage control module for receiving the data source packet of payload generation, and is carried out RS Error Correction of Coding, will be entangled
Data source packet after miscoding is stored in several FLASH memories；
According to the configuration-direct received, data source packet after extracting the corresponding Error Correction of Coding being stored in FLASH memory,
And RS decoding processing is carried out to the data source packet after Error Correction of Coding, and decoding treated data source packet is passed through into number transmission transmitter
It is transmitted back to earth station.
2. spaceborne solid-state memory system according to claim 1, which is characterized in that CPU, FPGA, FLASH array it
Between by advanced peripheral bus connect, and by advanced peripheral bus realization three between communication；Between the CPU and FPGA
Using HPI interface.
3. spaceborne solid-state memory system according to claim 1, which is characterized in that the storage control module is specifically wrapped
It includes: combining input submodule, storage operation submodule, multiple connection output sub-module and APB bridge submodule；
The combining input submodule, for receiving the multipath high-speed parallel data from extraneous payload generation and coming from
The satellite engineering parameter of upper layer house keeping computer；Received multipath high-speed parallel data is grouped, every group independent group of data
RS Error Correction of Coding is carried out at data source packet, and to data source packet, the data source packet after Error Correction of Coding is cached, is cached
Data source packet afterwards；And the data source packet after caching is exported to storage and operates submodule；
The storage operates submodule, for initializing to the FLASH memory in FLASH array；It is also used to caching
The data address in data source packet afterwards is configured, data write-in, BAT table, data erasing, marked invalid, data is organized to return
Operation is put, the data source packet after being operated, and the data source packet after operation is stored to several FLASH memories；According to connecing
The configuration-direct received, the data source packet after extracting the corresponding Error Correction of Coding being stored in FLASH memory, and error correction is compiled
Data source packet after code carries out RS decoding processing, and will decoding treated that data source packet is sent to multiple connection output sub-module；
The multiple connection output sub-module, for the data source packet progress data buffer storage that will decode that treated, and with document number, time
Code collectively constitutes data framing, output to several transmission transmitters；
The APB bridge submodule, for completing the communication between CPU and FPGA.
4. spaceborne solid-state memory system according to claim 3, which is characterized in that the storage operation submodule specifically wraps
Include: APB administrative unit, combining input unit, RAM cache unit, FLASH control unit, BAT RAM cache unit and multiple connection are defeated
Unit out；
The APB administrative unit, for being managed to each unit in storage control submodule；
The combining input unit, for carrying out RS Error Correction of Coding to data source packet, the data source packet after obtaining Error Correction of Coding will
Data source packet after Error Correction of Coding is sent into asynchronous FIFO and is cached, and the data source packet after caching is sent to RAM cache unit；
The RAM cache unit, for carrying out secondary caching to the data source packet after caching, by the data source packet after secondary caching
It is sent to FLASH control unit；
The FLASH control unit stores error correction for several FLASH memories to be carried out with initialization and parameter configuration respectively
Data source packet after coding；It is also used to tissue BAT information, BAT information is sent to BAT RAM cache unit；It is also used to execute
Write-in, playback, erasing and the marked invalid operation of data source packet after Error Correction of Coding, the data source packet after being operated；
The BAT RAM cache unit for storing the BAT information of FLASH control unit transmission, and sends it to APB pipe
Manage unit；
The multiple connection output unit, the data source packet after the Error Correction of Coding for exporting to FLASH control unit carry out RS decoding,
Data source packet write-in asynchronous FIFO after decoding is cached.
5. spaceborne solid-state memory system according to claim 4, which is characterized in that the FLASH control unit is specifically wrapped
It includes: initialization and parameter configuration subelement, data write-in subelement, tissue BAT table subelement, data erasing subelement, label
Invalid subelement and data readback subelement；
It is described initialization with parameter configuration subelement, for several FLASH memories in NAND FLASH array respectively into
Row initialization scan generates corresponding FLASH bad block message, and configure and to slow to the configurable parameter of storage system
The data address in data source packet after depositing is configured；
Subelement is written in the data, for the data in data source packet according to configured data address, after caching is written；
The tissue BAT table subelement, for the FLASH bad block message generated in & parameter configuration subelement composition will to be initialized
Blocking allocation table information, i.e. BAT information, and the BAT information is sent to BAT RAM cache unit；
The data erasing subelement will be initial when writing full FLASH memory for the data in the data source packet after caching
The data of write-in are wiped；
The marked invalid subelement finds a certain piece of nothing in FLASH memory for being written or wiping in data procedures
When method write-in or erasing data, this part is labeled as invalid block；When executing write-in or erasing operation next time, this will be skipped
Block；
The data readback subelement, the configuration-direct for being sent according to master cpu module extract corresponding be stored in
Data source packet after Error Correction of Coding in FLASH memory, and the data source packet after Error Correction of Coding is exported to multiple connection and exports list
Member.
6. spaceborne solid-state memory system according to claim 5, which is characterized in that the FLASH control unit further include:
Parameter configuration layer；The parameter configuration layer includes: parameter configuration instruction resolution unit and parameter configuration unit；
The parameter configuration instructs resolution unit, for parsing the configuration information for being stored in the data source packet of FLASH；
The parameter configuration storage unit, for the parameter configuration instruction after storing and resolving.
7. spaceborne solid-state memory system according to claim 1, which is characterized in that the outside of the storage control module is also
Equipped with external interface, for being attached communication with corresponding hardware；
The external interface includes: Data Input Interface, storage control interface, transmission frame output interface, CAN communication interface, AD
Telemetry-acquisition interface, master cpu unit interface, OC instruct output interface, digital dock interface；
The Data Input Interface receives the data generated from extraneous payload for receiving chip by LVDS；It is logical
It crosses asynchronous RS422 and receives chip, receive the satellite engineering parameter packet from Star Service；By the data of payload generation and come from star
The satellite engineering parameter packet of business, composition data source packet；
The storage control interface is used for according to status bus, control bus and data/address bus, by the data source after Error Correction of Coding
Packet stores several FLASH memories into FLASH array；
The transmission frame output interface, for being exported data framing to several transmission transmitters by LVDS chip；
The CAN communication interface, for receiving the number teletype command and timecode information of house keeping computer transmission；It is also used to receive master
Control the parameter configuration instruction that CPU module is sent.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037810A (en) * | 2021-02-23 | 2021-06-25 | 航天恒星科技有限公司 | Large-capacity data storage system applied to space high-speed network |
| CN113722770A (en) * | 2021-08-18 | 2021-11-30 | 上海励驰半导体有限公司 | End-to-end protection method and system based on hierarchical data integrity |
| CN113741813A (en) * | 2021-08-19 | 2021-12-03 | 上海卫星工程研究所 | System, method, medium and device for realizing on-demand playback of load data |
| CN114936172A (en) * | 2022-05-24 | 2022-08-23 | 国网河南省电力公司内乡县供电公司 | Unmanned aerial vehicle airborne data management system capable of realizing load data management |
| CN115687228A (en) * | 2023-01-03 | 2023-02-03 | 中国科学院国家空间科学中心 | Satellite-borne solid-state storage system and method based on PCIe bus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060294357A1 (en) * | 2005-06-24 | 2006-12-28 | Choo Eugene K | System and method for rapid boot of secondary operating system |
| CN103885421A (en) * | 2014-03-26 | 2014-06-25 | 上海航天电子通讯设备研究所 | Standard bus controller |
| CN105608048A (en) * | 2015-12-21 | 2016-05-25 | 北京时代民芯科技有限公司 | Dynamic reconfiguration circuit and reconfiguration method of satellite-borne DSP (Digital Signal Processor) software task |
| CN106557346A (en) * | 2016-11-24 | 2017-04-05 | 中国科学院国家空间科学中心 | A kind of primary particle inversion resistant star-carried data processing system and method |
-
2019
- 2019-07-09 CN CN201910613513.2A patent/CN110334040B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060294357A1 (en) * | 2005-06-24 | 2006-12-28 | Choo Eugene K | System and method for rapid boot of secondary operating system |
| CN103885421A (en) * | 2014-03-26 | 2014-06-25 | 上海航天电子通讯设备研究所 | Standard bus controller |
| CN105608048A (en) * | 2015-12-21 | 2016-05-25 | 北京时代民芯科技有限公司 | Dynamic reconfiguration circuit and reconfiguration method of satellite-borne DSP (Digital Signal Processor) software task |
| CN106557346A (en) * | 2016-11-24 | 2017-04-05 | 中国科学院国家空间科学中心 | A kind of primary particle inversion resistant star-carried data processing system and method |
Non-Patent Citations (2)
| Title |
|---|
| 董振兴: "星载固态存储文件化管理方案应用研究", 《中国优秀博士学位论文全文数据库信息科技辑》 * |
| 许志宏: "面向星载一体化综合电子系统的固态存储技术研究", 《中国优秀博士学位论文全文数据库工程科技II辑》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037810A (en) * | 2021-02-23 | 2021-06-25 | 航天恒星科技有限公司 | Large-capacity data storage system applied to space high-speed network |
| CN113722770A (en) * | 2021-08-18 | 2021-11-30 | 上海励驰半导体有限公司 | End-to-end protection method and system based on hierarchical data integrity |
| CN113741813A (en) * | 2021-08-19 | 2021-12-03 | 上海卫星工程研究所 | System, method, medium and device for realizing on-demand playback of load data |
| CN113741813B (en) * | 2021-08-19 | 2024-03-29 | 上海卫星工程研究所 | Load data-on-demand playback realization system, method, medium and equipment |
| CN114936172A (en) * | 2022-05-24 | 2022-08-23 | 国网河南省电力公司内乡县供电公司 | Unmanned aerial vehicle airborne data management system capable of realizing load data management |
| CN115687228A (en) * | 2023-01-03 | 2023-02-03 | 中国科学院国家空间科学中心 | Satellite-borne solid-state storage system and method based on PCIe bus |
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