CN107291655B

CN107291655B - SoC bootstrap IP circuit with APB bus interface

Info

Publication number: CN107291655B
Application number: CN201710446920.XA
Authority: CN
Inventors: 张磊; 汪健; 刘彬; 徐叔喜
Original assignee: North Electronic Research Institute Anhui Co., Ltd.
Current assignee: Anhui North Microelectronics Research Institute Group Co ltd
Priority date: 2017-06-14
Filing date: 2017-06-14
Publication date: 2020-10-09
Anticipated expiration: 2037-06-14
Also published as: CN107291655A

Abstract

The invention discloses an SoC bootstrap IP circuit with an APB bus interface, which comprises a QSPI serial interface controller, an APB conversion logic interface and a Flash conversion logic interface; converting an address line, a write data line, a read data line, a write signal and a read signal of a control end of a standard QSPI serial interface controller into an APB bus interface signal through an APB conversion logic interface; and the QSPI serial interface controller converts an external interface clock, chip selection, data transmission and data reception into Flash interface signals through a Flash conversion logic interface. The IP is used for realizing SoC chip bootstrap, the inside can be directly connected through an APB bus, the outside can be directly connected with a serial Flash, and the QSPI is not required to be controlled to be connected with the Flash through an external controller, so that the use is simple and convenient.

Description

SoC bootstrap IP circuit with APB bus interface

Technical Field

The invention belongs to the field of IP design in a semiconductor integrated circuit, and particularly relates to an IP special integrated circuit with an APB bus interface, which is designed by adopting a QSPI method to realize SoC bootstrap.

Background

The bootstrap is a process of automatically running and loading a program stored in an off-chip Flash memory into a program register in a chip when the SoC chip is started, the bootstrap is a first step of normal operation of the SoC chip, and whether the success of the bootstrap determines whether the whole system operation environment can be normally constructed or not. At present, the SoC chip generally adopts SPI (Serial Peripheral interface) or QSPI (quad Serial Peripheral interface) to perform bootstrap by an external Flash memory, the SPI is a Serial interface bus proposed by Motorola, and is a high-speed, full-duplex, synchronous communication bus, and only four ports are provided outside, but only one Serial interface of the SPI performs data communication, and the transmission rate is slower, while the QSPI is a four-way Serial interface, and the transmission rate is four times of the SPI, and the SoC chip has increasingly used a QSPI external Flash device to perform bootstrap. And after the SoC chip is powered on, automatically moving data from the external Flash memory through the QSPI external interface and loading the data into the SoC chip. The QSPI external interfaces are clock ss _ clk, chip selection ss _ oe [3:0], data transmission ss _ txd [3:0] and data reception ss _ rxd [3:0], and the serial Flash external interfaces are data input DI, data output DO, write inclusion WP and HOLD signal HOLD. It can be seen that the QSPI interface signal cannot be directly connected to the Flash memory, and is also controlled by an external controller, which is very inconvenient to use.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide the SoC bootstrap IP circuit with the APB bus interface, which is simple and convenient to use and does not need to control the QSPI to be connected with Flash through an external controller.

In order to solve the technical problem, the invention provides an SoC bootstrap IP circuit with an APB bus interface, which is characterized by comprising a QSPI serial interface controller, an APB conversion logic interface and a Flash conversion logic interface;

converting an address line address [7:0], a write data line wdata [7:0], a read data line rdata [7:0], a write signal write and a read signal read of a control end of a standard QSPI serial interface controller into APB bus interface signals through an APB conversion logic interface;

and converting an external interface clock ss _ clk, a chip selection ss _ oe [3:0], a data transmission ss _ txd [3:0] and a data reception ss _ rxd [3:0] of the QSPI serial interface controller into Flash interface signals through a Flash conversion logic interface.

The QSPI serial interface controller is directly connected with an SoC internal bus through an APB bus interface and directly connected with a serial Flash through a Flash interface.

An output clock ss _ clk of the QSPI serial interface controller is connected to a clock end SCLK of the Flash conversion logic interface, a chip selection ss _ oe is converted and output to a chip selection CS end according to logic control, a data sending ss _ txd and a data receiving ss _ rxd are respectively connected to a bidirectional port data input DI, a data output DO, a write inclusion WP and a HOLD signal HOLD according to a protocol of the Flash interface, and the sequence of a four-bit data line and the Flash interface is distributed.

The APB bus interface signals include a clock input PCLK, a reset input PRESETN, a write signal input PWRITE, an enable control input PENABLE, a bus select input PSEL, a write data bus input PWDATA [31:0], a write address bus input PADDR [7:0], and a read data bus output PRDATA [31:0 ].

The Flash interface signals include data input DI, data output DO, write contain WP, and HOLD signal HOLD.

The serial Flash is erased, programmed or read through the Flash conversion logic interface,

and directly accessing the Dual and the Quad SPI Flash through the Flash conversion logic interface.

The invention achieves the following beneficial effects:

the invention designs an SoC bootstrap IP circuit with an APB (advanced Peripheral bus) bus interface, wherein an APB bus is one of AMBA bus structures proposed by ARM company, and becomes a standard on-chip bus structure at present. The designed IP circuit takes a QSPI serial interface as a core, is internally connected with an SoC and designed into a common APB bus interface, and is externally connected with Flash and designed into a common serial Flash interface, such as Flash chips of GigaDevice company and Winbond company. The IP is used for realizing SoC chip bootstrap, the inside can be directly connected through an APB bus, the outside can be directly connected with a serial Flash, and the QSPI is not required to be controlled to be connected with the Flash through an external controller, so that the use is simple and convenient.

Drawings

FIG. 1 is an APB bus interface transition diagram;

FIG. 2 is a Flash interface conversion diagram;

fig. 3 is a SoC bootstrapped IP circuit with an APB bus interface.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

As shown in fig. 1, fig. 2 and fig. 3, the present invention designs an SoC bootstrap IP circuit with an APB bus interface, the IP circuit uses a QSPI serial interface controller as a core, and an external interface has a standard APB bus interface: the clock input PCLK, reset input PRESETN, write signal input PWRITE, enable control input PENABLE, bus select input PSEL, write data bus input PWDATA [31:0], write address bus input PADDR [7:0], read data bus output PRDATA [31:0], which may be directly connected to the SoC internal bus via the APB bus. In addition, the interface connected with the serial Flash externally has data input DI, data output DO, write inclusion WP and a HOLD signal HOLD, and can be directly connected with the serial Flash through the serial Flash interface without any conversion control.

As the standard QSPI control end only has an address line address [7:0], a write data line wdata [7:0], a read data line rdata [7:0], a write signal write and a read signal read, which cannot be directly connected with the SoC on-chip bus, the signals are converted into standard APB bus interface signals, and input data, a write enable signal, output data and the like are respectively converted into corresponding interface signals of the QSPI according to an APB bus protocol. As shown in fig. 1.

In addition, the QSPI external interfaces are a clock ss _ clk, a chip selection ss _ oe [3:0], a data transmission ss _ txd [3:0] and a data reception ss _ rxd [3:0], and if the QSPI external interfaces are connected with a serial Flash, conversion control is needed. In the patent, firstly, a QSPI output clock ss _ clk is connected to a clock terminal SCLK of a Flash circuit, then a chip selection ss _ oe of the QSPI is converted and output to a chip selection CS terminal according to logic control, a data sending ss _ txd and a data receiving ss _ rxd are respectively connected to a bidirectional port data input DI, a data output DO, a write contained WP and a HOLD signal HOLD according to a protocol of a Flash interface, and the sequence of a four-bit data line and the Flash interface is distributed. As shown in fig. 2.

QSPI is a four serial peripheral interface controller, can visit Dual or Quad SPI Flash device, in this patent, through adding APB conversion logic interface and Flash conversion logic interface control, can directly link to each other with SoC internal bus when using this IP circuit, can directly meet with serial Flash when connecting the Flash device to the external, and do not need any conversion control, can directly carry on operations such as erasing and writing, programming, reading to the Flash device, and can directly visit the operation to Dual and Quad SPI Flash device. As shown in fig. 3.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. An SoC bootstrap IP circuit with an APB bus interface is characterized by comprising a QSPI serial interface controller, an APB conversion logic interface and a Flash conversion logic interface;

converting an external interface clock ss _ clk, a chip selection ss _ oe [3:0], a data transmission ss _ txd [3:0] and a data reception ss _ rxd [3:0] of a QSPI serial interface controller into Flash interface signals through a Flash conversion logic interface;

the QSPI serial interface controller is directly connected with an SoC internal bus through an APB bus interface and directly connected with a serial Flash through a Flash interface;

an output clock ss _ clk of the QSPI serial interface controller is connected to a clock end SCLK of the Flash conversion logic interface, a chip selection ss _ oe [3:0] is converted and output to a chip selection CS end of the Flash conversion logic interface according to logic control, a data sending ss _ txd [3:0] and a data receiving ss _ rxd [3:0] are respectively connected to a bidirectional port data input DI, a data output DO, a write contained WP and a HOLD signal HOLD according to a protocol of the Flash interface, and the QSPI serial interface controller distributes the sequence of a four-bit data line and the Flash interface;

the APB bus interface signals include a clock input PCLK, a reset input PRESETN, a write signal input PWRITE, an enable control input PENABLE, a bus select input PSEL, a write data bus input PWDATA [31:0], a write address bus input PADDR [7:0], and a read data bus output PRDATA [31:0 ];

2. The SoC bootstrap IP circuit with APB bus interface of claim 1, wherein the serial Flash is erased, programmed or read through the Flash conversion logic interface.

3. The SoC bootstrap IP circuit with the APB bus interface as claimed in claim 1, characterized in that the Dual Flash and the Quad SPI Flash are directly accessed through the Flash conversion logic interface.