CN107291655A

CN107291655A - A kind of SoC bootstrapping IP circuits of band APB EBIs

Info

Publication number: CN107291655A
Application number: CN201710446920.XA
Authority: CN
Inventors: 张磊; 汪健; 刘彬; 徐叔喜
Original assignee: North Electronic Research Institute Anhui Co., Ltd.
Current assignee: Anhui North Microelectronics Research Institute Group Co ltd
Priority date: 2017-06-14
Filing date: 2017-06-14
Publication date: 2017-10-24
Anticipated expiration: 2037-06-14
Also published as: CN107291655B

Abstract

The invention discloses a kind of SoC of band APB EBIs bootstrapping IP circuits, including QSPI serial interface controllers, APB conversion logics interface and Flash conversion logic interfaces；Address wire, write data line, read data line, write signal and the read signal of the QSPI serial interface controller control ends of standard are converted to by APB bus interface signals by APB conversion logics interface；QSPI serial interface controller external interfaces clock, piece are selected by Flash conversion logics interface, data are sent and data receiver is converted to Flash interface signals.Realize that SoC chip is booted using the IP, inside directly can be connected by APB buses, and outside can be directly connected to serial Flash, easy to use without controlling QSPI to be connected with Flash by peripheral control unit.

Description

A kind of SoC bootstrapping IP circuits of band APB EBIs

Technical field

Realized the invention belongs to IP design fields in semiconductor integrated circuit, more particularly to using QSPI methods to SoC certainly Lift, design a kind of IP application specific integrated circuits of band APB EBIs.

Background technology

Bootstrapping is exactly the program automatic running loading that piece outer flash storage is will be stored in when SoC chip starts The process of program register in piece, bootstrapping is the first step of SoC chip normal work, and the success or not of bootstrapping determines whole Can individual system running environment normally build.Current SoC chip typically uses SPI（Serial Peripheral Interface）Or QSPI (Quad Serial Peripheral Interface) external flash storage is booted, SPI It is a kind of serial interface bus that Motorola is proposed, it is a kind of high speed, full duplex, synchronous communication bus, outside Have four ports, but SPI only have all the way serial line interface enter row data communication, transmission rate is slow, and QSPI is that four roads are serial Interface, transmission rate is four times of SPI, and SoC chip is more and more booted using the external Flash devices of QSPI. After electricity in SoC chip, by QSPI external interfaces, automatic moving data is loaded into SoC pieces from outside flash storage. QSPI external interfaces are clock ss_clk, piece selects ss_oe [3:0], data send ss_txd [3:0] and data receiver ss_rxd [3:0], serial Flash external interface is data input DI, data output DO, writes comprising WP and keep signal HOLD.It can see Go out, QSPI interface signals can not be joined directly together with flash storage, also need to be controlled by peripheral control unit, using very Inconvenience.

The content of the invention

The technical problems to be solved by the invention are to overcome defect of the prior art there is provided a kind of with APB EBIs SoC bootstrapping IP circuits, it is not necessary to by peripheral control unit control QSPI be connected with Flash, it is easy to use.

In order to solve the above technical problems, the present invention provides a kind of SoC bootstrapping IP circuits of band APB EBIs, its feature It is, including QSPI serial interface controllers, APB conversion logics interface and Flash conversion logic interfaces；

By APB conversion logics interface by the address wire address [7 of the QSPI serial interface controller control ends of standard:0]、 Write data line wdata [7:0], read data line rdata [7:0], write signal write and read signal read are converted to APB buses and connect Message number；

QSPI serial interface controller external interface clocks ss_clk, piece are selected by ss_oe [3 by Flash conversion logics interface: 0], data send ss_txd [3:0] and data receiver ss_rxd [3:0] Flash interface signals are converted to.

QSPI serial interface controllers are joined directly together by APB EBIs with SoC internal bus, pass through Flash interfaces Directly connect with serial Flash.

The output clock ss_clk of QSPI serial interface controllers is connected to the clock end of Flash conversion logic interfaces SCLK, piece selects ss_oe according to logic control conversion output to chip selection cs end, and data send ss_txd and data receiver ss_rxd and pressed Agreement according to Flash interfaces is respectively connecting to bidirectional interface data input DI, data output DO, writes comprising WP and keeps signal HOLD, and distribute order of the four figures according to line and Flash interfaces.

APB bus interface signals include clock input PCLK, reset input PRESETN, write signal input PWRITE, enable Control input PENABLE, bus selection input PSEL, write data bus input PWDATA [31:0], write address bus is inputted PADDR[7:0] and read data bus output PRDATA [31:0].

Flash interface signals include data input DI, data output DO, write comprising WP and keep signal HOLD.

Erasable, programming or reading operation are carried out to serial Flash by the Flash conversion logics interface,

Dual and Quad SPI Flash are directly conducted interviews operation by the Flash conversion logics interface.

The beneficial effect that the present invention is reached：

A kind of SoC bootstrapping IP circuits with APB (Advanced Peripheral Bus) EBI of present invention design, APB is total Line is one of AMBA bus structures that ARM companies propose, turns into a kind of on-chip bus structure of standard at present.The IP electricity of design Road is connected using QSPI serial line interfaces as core, internally with SoC is designed as conventional APB EBIs, is externally connected with Flash Conventional serial Flash interface is calculated as, the Flash chip of such as GigaDevice companies, Winbond companies can be joined directly together. Realize that SoC chip is booted using the IP, inside directly can be connected by APB buses, and outside can be directly connected to serially Flash, and no longer need to control QSPI with Flash to be connected by peripheral control unit, it is easy to use.

Brief description of the drawings

Fig. 1 is APB EBI transition diagrams；

Fig. 2 is Flash interface conversion figures；

Fig. 3 is the SoC bootstrapping IP circuits with APB EBIs.

Embodiment

The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention Technical scheme, and can not be limited the scope of the invention with this.

As shown in Figure 1, Figure 2 and Figure 3, a kind of SoC bootstrapping IP circuits of band APB EBIs of present invention design, IP electricity Road is using QSPI serial interface controllers as core, and external interface has standard APB EBIs：Clock input PCLK, reset input PRESETN, write signal input PWRITE, enable control input PENABLE, bus selection input PSEL, write data bus input PWDATA[31:0], write address bus input PADDR [7:0], read data bus output PRDATA [31:0], APB buses are passed through It can be joined directly together with SoC internal bus.The interface being externally connected in addition with serial Flash has data input DI, data output DO, write comprising WP and keep signal HOLD, directly can be connected by serial Flash interface with serial Flash, without any turn Change control.

Because the QSPI control ends of standard only have address wire address [7:0], write data line wdata [7:0] data, are read Line rdata [7:0], write signal write, read signal read, it is impossible to be directly joined directly together with SoC bus on chips, therefore these are believed The APB bus interface signals of standard number are converted to, mainly according to APB bus protocols by input data, write enable signal, output number According to etc. be respectively converted into QSPI the corresponding interface signals.As shown in Figure 1.

In addition, QSPI external interfaces are clock ss_clk, piece selects ss_oe [3:0], data send ss_txd [3:0] sum According to reception ss_rxd [3:0], if with serial Flash to connect, need to carry out conversion and control.In this patent, first will QSPI outputs clock ss_clk is connected to the clock end SCLK of Flash circuits, and QSPI piece then is selected into ss_oe according to logic control System conversion output sends agreements of the ss_txd and data receiver ss_rxd according to Flash interfaces to chip selection cs end, and by data Bidirectional interface data input DI, data output DO are respectively connecting to, writes comprising WP and keeps signal HOLD, and distributes four figures evidence The order of line and Flash interfaces.As shown in Figure 2.

QSPI is a four SPI controllers, Dual or Quad SPI Flash devices can be conducted interviews, In this patent, by adding APB conversion logics interface and Flash conversion logic Interface Controllers, using can be with during the IP circuits Directly it is connected with SoC internal bus, directly can connects during external connection Flash devices with serial Flash, without any turn Control is changed, the operation such as erasable, programming, reading can be directly carried out to Flash devices, and to Dual and Quad SPI Flash devices Part all can directly conduct interviews operation.As shown in Figure 3.

Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed Also it should be regarded as protection scope of the present invention.

Claims

1. a kind of SoC bootstrapping IP circuits of band APB EBIs, it is characterized in that, including QSPI serial interface controllers, APB turns Change logic interfacing and Flash conversion logic interfaces；

2. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, QSPI serial line interface controls Device processed is joined directly together by APB EBIs with SoC internal bus, is directly connected by Flash interfaces with serial Flash.

3. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, QSPI serial line interface controls The output clock ss_clk of device processed is connected to the clock end SCLK of Flash conversion logic interfaces, and piece selects ss_oe according to logic control Conversion output to chip selection cs end, data send ss_txd and are connected respectively according to the agreement of Flash interfaces with data receiver ss_rxd To bidirectional interface data input DI, data output DO, write comprising WP and holding signal HOLD, and distribute four figures according to line and Flash The order of interface.

4. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, APB EBIs letter Number include clock input PCLK, reset input PRESETN, write signal input PWRITE, enable control input PENABLE, bus Selection input PSEL, write data bus input PWDATA [31:0], write address bus input PADDR [7:0] and read data bus Export PRDATA [31:0].

5. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, Flash interface signals Including data input DI, data output DO, write comprising WP and holding signal HOLD.

6. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, pass through the Flash Conversion logic interface carries out erasable, programming or reading operation to serial Flash.

7. the SoC bootstrapping IP circuits of band APB EBIs according to claim 1, it is characterized in that, pass through the Flash Conversion logic interface directly conducts interviews operation to Dual and Quad SPI Flash.