CN105892359A - Multi-DSP parallel processing system and method - Google Patents
Multi-DSP parallel processing system and method Download PDFInfo
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- CN105892359A CN105892359A CN201610273044.0A CN201610273044A CN105892359A CN 105892359 A CN105892359 A CN 105892359A CN 201610273044 A CN201610273044 A CN 201610273044A CN 105892359 A CN105892359 A CN 105892359A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention provides a multi-DSP parallel processing system and method, and the system is provided with an N-stage signal processing board which improves the signal processing capability. The type of an FPGA is XC6VLX130T, and the type of the DSPs is ADSP-TS201. The data communication between the DSPs is completed through a high-speed link. The system achieves high parallelism, and is strong in data transmission capability. An SDRAM connected with the DSPs are greatly high in data throughout, and the data transmission is achieved through a parallel interface. The rate of data transmission is high.
Description
Technical field
The present invention relates to signal processing technology field, particularly relate to a kind of multi-DSP parallel procession system and
Its processing method.
Background technology
Along with the development of Radar Technology, increasing Radar Signal Processing will complete at numeric field, greatly
Bandwidth high resolution, the employing of multi-signal processing mode so that the real time signal processing process to data
Speed is greatly improved.(designer determines algorithm flow for application background to tradition task based access control, determines phase
The system structure answered, then structure is divided into module carries out circuit design) radar signal processor more come
More expose its function singleness, poor universality, the shortcoming of software algorithm scaling difficulty.
Superelevation disposal ability, prominent data exchange capability, good Universal and scalability becomes
Feature for Modern Radar Signal datatron.Digital Signal Processing (DSP) chip have disposal ability strong,
Apply feature flexibly, frequently as the core processor of radar signal processor, but along with to processing energy
Improving constantly of the requirement of power, monolithic DSP can not meet the most far away requirement.Therefore, this area is needed badly
The data handling system that a kind of fast operation, disposal ability are strong.
Summary of the invention
(1) to solve the technical problem that
In order to solve the problems referred to above that prior art exists, the invention provides a kind of many DSP and locate parallel
Reason system and processing method thereof.
(2) technical scheme
The invention provides a kind of multi-DSP parallel procession system, including: N level signal-processing board, phase
Adjacent two-stage signal is processed and is connected by data-interface between plate；Wherein, every grade of signal-processing board includes one
FPGA and M sheet DSP, described FPGA receive the data of upper level signal-processing board transmission, institute
State M sheet DSP and data carried out parallel processing, described FPGA will process after data transmission under
One stage signal processes plate, wherein, 1≤N≤100,2≤M≤10.
Preferably, described M takes 4, and the link port of described FPGA and four DPS connects, each
Sheet DSP is all connected by the link port of link port with other three DSP；Described FPGA will receive
The data arrived are by link port transmission to DSP1, and data are given by described DSP1 by link port transmission
DSP2, DSP3 and DSP4, data are carried out also by described DSP1, DSP2, DSP3 and DSP4
Row processes, and the data after described DSP2, DSP3 and DSP4 will process are transferred to described DSP1,
Data after DSP1, DSP2, DSP3 and DSP4 are processed by described DSP1 are transferred to described FPGA,
Data after described FPGA will process are transmitted to next stage signal-processing board.
Preferably, described FPGA selects XC6VLX130T；And/or described DSP selects
ADSP-TS201。
Preferably, described FPGA connects a piece of FLASH chip, is used for storing FPGA program；
And/or described DSP4 connects a piece of FLASH chip, it is used for storing DSP program and systematic parameter；
Described FLASH chip selects M29W640FT60ZA6；And/or described DSP3 and DSP4 is respectively
External one group of SDRAM, respectively expands 4G off-chip memory space, is used for storing ephemeral data.
Preferably, described FPGA connects has a transmission parallel port and to receive parallel port, at upper level signal
The parallel port that sends of reason plate connects the reception parallel port of next stage signal-processing board, and FPGA is by receiving parallel port
The data of reception upper level signal-processing board transmission, the data after processing are by transmission also port transmission extremely
Next stage signal-processing board.
Preferably, described FPGA connects an Asynchronous Serial Interface, and described Asynchronous Serial Interface is with outside
Equipment connects, and carries out the storage of video data；And/or described FPGA connects one 422 interfaces, it is achieved
And the serial communication between PC；And/or described FPGA connects a PCIE interface and/or a network interface,
Data after processing are sent to host computer.
Preferably, described FPGA connects power supply chip, it is achieved the following electric sequence of DSP: DSP
Core voltage VDD-A power at first, power on after IO voltage, VDD-DRAM finally powers on.
Preferably, also including CY2308-1H clock module, input clock signal is divided into 8 by it
The identical clock signal of phase frequency, wherein four tunnel clock signals are supplied to DSP, wherein two-way
Being supplied to SDRAM, wherein a road is supplied to FPGA.
Present invention also offers a kind of many DSP based on above-mentioned multi-DSP parallel procession system to locate parallel
Reason method, including: step A: initialize multi-DSP parallel procession system；Step B: to described many
DSP parallel processing system (PPS) configures；Step C: the FPGA of every grade of signal-processing board receives upper one
The data of level signal-processing board transmission, and transfer data to a DSP of this grade of signal-processing board；
And step D: a DSP transfers data to other DSP of this grade of signal-processing board, all
DSP carries out parallel processing to data, and the data back after processing is to FPGA；Step E:FPGA
Data after processing are transmitted to next stage signal-processing board.
10, multi-DSP parallel procession method as claimed in claim 9, it is characterised in that described step
Rapid C specifically includes:
The FPGA of every grade of signal-processing board receives the data of upper level signal-processing board transmission by parallel port,
And data are given by link port transmission the DSP1 of this grade of signal-processing board；
Preferably, described step D specifically includes: data are given this level by link port transmission by DSP1
DSP2, DSP3, DSP4 of signal-processing board, DSP1, DSP2, DSP3, DSP4 are to data
Carry out parallel processing, and the data back after processing is to FPGA.
(3) beneficial effect
From technique scheme it can be seen that a kind of multi-DSP parallel procession system of the present invention and from
Reason method has the advantages that
(1) there is N level signal-processing board, greatly improve signal handling capacity, height can be realized
The data of fast and high complexity process；
(2) FPGA selects XC6VLX130T, XC6VLX130T cost performance height, internal resource
Abundant, macroelement quantity is many；
(3) DSP selects ADSP-TS201, ADSP-TS201 fast operation, provides high-performance
Static superscale DSP operation, special optimization is applicable to communication and needs the application of many dsp processors；
DSP algorithm and I/O excellent performance, instruction set is very flexible, supports the DSP architecture of high-level language,
It is easy to dsp program；It is extended to multicomputer system, during connection, only needs the lowest communication overhead, pole
The earth improves data processing speed and the ability of multi-DSP parallel procession system；
(4) data communication between DSP uses high-speed chain crossing to complete, and bidirectional data transfers rate can
Reach 1GB/s, it is achieved seamless link, it is to avoid bus arbitration problem, have process simultaneously a lot of different
The ability of task, highly-parallel, data transmission capabilities is strong, and motility is good；
(5) FLASH chip that DSP connects preserves the parameter that data process, and improves system number
According to processing speed；
(6) FLASH chip selects M29W640FT 60ZA6, and it is low in energy consumption, capacity is big, fast
Degree is fast, can retain information after power down, can write with online programming, can write by page successive byte,
Reading speed is high, and compared with EEPROM, it has more superior performance and lower price；
(7) SDRAM of the employing that DSP connects has high data throughout, and DSP has
SDRAM memory, simplifies the interface of SDRAM, without external circuits and consideration sequential；
(8) being transmitted by the data between parallel port realizes, message transmission rate is high, it is possible to achieve
The message transmission rate of 3.2Gbps；
(9) the PCIE interface of FPGA provides the >=high speed data transmission interface of 3Gbit/s speed,
Achieve high speed pipelined data between plate to process；
(10) by clock matches device distribute clock signal, it is to avoid clock signal because of reflection to it
He impacts by clock, it is ensured that each device clock synchronizes.
Accompanying drawing explanation
Fig. 1 is the multi-DSP parallel procession system structure schematic diagram of the embodiment of the present invention；
Fig. 2 is the timing relationship figure of the ADSP-TS201 of the embodiment of the present invention；
Fig. 3 is the control software interface figure of the embodiment of the present invention；
Fig. 4 is the PCIe function structure chart of the embodiment of the present invention；
Fig. 5 is the annexation figure of FPGA Yu DPS of the embodiment of the present invention；
Fig. 6 is the link port structure chart of the embodiment of the present invention.
Fig. 7 is the annexation figure of DSP Yu SDRAM of the embodiment of the present invention；
Fig. 8 is the multi-DSP parallel procession method flow diagram of the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with concrete real
Execute example, and referring to the drawings, the present invention is described in more detail.
Seeing Fig. 1, first embodiment of the invention provides a kind of multi-DSP parallel procession system, its bag
Including N level signal-processing board, adjacent two-stage signal is processed and is connected by data-interface between plate, every grade of letter
Number process plate include a FPGA and M sheet DSP, FPGA receive upper level signal-processing board transmission
Data, M sheet DSP carries out parallel processing to data, FPGA will process after data transmission under
One stage signal processes plate, wherein, 1≤N≤100,2≤M≤10.
Wherein, the FPGA of first order signal-processing board receives initial data, and M sheet DSP is to data
After carrying out parallel processing, the data after FPGA will process are transmitted to second level signal-processing board；N
Level signal-processing board receives the data of N-1 level signal-processing board transmission, and data are entered by M sheet DSP
Row parallel processing, obtains target data.
Preferably, described M takes 4, and FPGA is connected by data/address bus with the most a piece of DSP, should
Three DSP of sheet DSP and other are connected by data/address bus, the data transmission that FPGA will receive
Transfer data to other three DSP, four DSP to this sheet DSP, this sheet DSP data are entered
Row parallel processing, the data after other three DSP will process are transferred to this sheet DSP, this sheet DSP
Data after four DSP are processed be transferred to the data transmission after FPGA, FPGA will process under
One stage signal processes plate.
Further, described FPGA select XC6VLX130T, XC6VLX130T cost performance high,
Internal resource is abundant, macroelement quantity is many.DSP selects ADSP-TS201, ADSP-TS201 to transport
Calculation speed is fast, provide high-performance static state superscale DSP operation, special optimization to be applicable to communication and needs
The application of many dsp processors；DSP algorithm and I/O excellent performance, instruction set is very flexible, supports
The DSP architecture of high-level language, it is simple to dsp program；It is extended to multicomputer system, during connection
Only need the lowest communication overhead, be a high performance dsp chip, drastically increase many DSP
The data processing speed of parallel processing system (PPS) and ability.
The link port of FPGA and four DPS connects, every a piece of DSP all by link port and other
The link port of three DSP connects；FPGA by the data that receive by link port transmission to DSP1,
Data are passed through link port transmission to DSP2, DSP3 and DSP4, DSP1, DSP2, DSP3 by DSP1
With DSP4, data being carried out parallel processing, the data after DSP2, DSP3 and DSP4 will process pass
It is defeated by the data after DSP1, DSP2, DSP3 and DSP4 are processed by DSP1, DSP1 to be transferred to
Data after FPGA, FPGA will process are transmitted to next stage signal-processing board.FPGA in this enforcement
With the annexation of DPS as shown in Figure 5.
In the present embodiment, fpga chip completes electric control and DSP on DSP and carries out link port
Communication, PCI Express bus communication, Ethernet interface communication, parallel bus communication, 422 buses are led to
Letter, system reset, the function such as ASI bus communication.
ADSP-TS201 has 4 full-duplex link port communications mouths, uses LVDS (Low Voltage
Differential Signaling) circuit, it is provided that 4 extra complete two-way I/O abilities, each link
Mouth has one to receive passage and a sendaisle, all can be received and transmitted operation independently,
I.e. with Double Data Rate (being up to the rising and falling edges of CCLK clock) latch data, i.e. can lead to
Cross processor core to access, it is also possible to conduct interviews by the way of DMA.ADSP-TS201 uses
LVDS carries out data transmission, and relative to other DSP such as ADSP-TS101, can make link port work
Make in higher clock frequency, it is thus achieved that higher message transmission rate, to improve the performance of processor.
Link port structure chart is as shown in Figure 6.
Preferably, the link port data width of ADSP-TS201 is set to 1, or
The pull-up resistor of 500 Ω is added, by chain between TMROE and VDD_IO of ADSP-TS201
Intersection data width is set to 4.
Preferably, link port recipient is near the terminal build-out resistor of pin configuration 100 Ω so that chain
Crossing normally works and carries out link port data transmission at a high speed.
Preferably, on pcb board, link port clock cable should be placed between four groups of LVDS lines,
To adapt to the operation of high speed 4-bit；Distance between LVDS line is the biggest, and length is the shortest, and via is most
Amount is few；LVDS line is individually placed in one layer, and is put in bottom or the top layer of PCB；Bus plane or
Stratum is positioned at below LVDS line, it is also possible to LVDS line is placed in the interlayer of bus plane and ground plane.
First embodiment of the invention provides a kind of multi-DSP parallel procession system, has N level signal
Process plate, greatly improve signal handling capacity, can realize at a high speed and the data of high complexity process.
Have employed the structure exclusively enjoying bus, external data bus and the address bus of four DSP are separate,
Being independent of each other, data communication each other uses high-speed chain crossing to complete so that multicomputer system
Being suitable for processing the most different tasks, highly-parallel, motility is strong simultaneously.Present treatment system schema is more
Make use of well the feature of chip, make circuit function more abundant comprehensively, be conducive to digital signal
The function of processing module.
First embodiment of the invention provides a kind of multi-DSP parallel procession system, between four DSP
Data communication use high-speed chain crossing complete, when core clock is 500MHz, one-way data pass
The defeated 55MB/s that reaches as high as, bidirectional data transfers rate is up to 1GB/s.And if use high speed outer
Bus coupled modes, even if using the SCLK of 100MHz, 64 BITBUS network mouths, with the fastest flowing water
Operating protocol, is not added with any latent period, and bidirectional data transfers speed is only 800MB/s, thus may be used
Seeing, the point-to-point communication of link port has the highest transmission reliability.Data between four DSP are led to
Letter uses high-speed chain crossing to complete, it is only necessary to link port realizes communicating between DSP sheet, it is possible to realize nothing
Seam connects, and avoids bus arbitration problem.
Wherein, FPGA connects a piece of FLASH chip, FLASH chip storage FPGA program；
DSP4 connects a piece of FLASH chip, FLASH chip storage DSP program and systematic parameter, is somebody's turn to do
FLASH chip is the 64Mb FLASH memory of 8Mbit × 8, the chip selection signal of FLASH
With DSP4'sWithConnect after carrying out logical AND operation in FPGA.Many DSP locate parallel
The DSP of reason system needs to perform a series of Digital Signal Processing computings such as FFT, FIR, these algorithms
Needing some butterfly coefficient and window parameters, if again calculated with formula when using, can be substantially reduced
The arithmetic speed of system, the FLASH chip that DSP4 connects also is preserved the parameter that data process, is come
Raising system overall operation speed.
DSP4 is set to main boot pattern, and DSP4 is by guiding FLASH loading procedure, its pinPin connects low, and its pinWithThe sheet choosing of FLASH is connected respectively with defeated as output
Going out to enable, 8 position datawires of FLASH connect DATA0～DATA7 of DSP4, it is achieved DSP4
FLASH load.
DSP1, DSP2 and DSP3 are set to link port bootmode, by link port loading procedure,
Any one link port of DSP1, DSP2 and DSP3 could be used for guiding, and link port guides to use and is somebody's turn to do
The DMA channel of link port, DSP1, DSP2 and DSP3'sPin connects height,Pin
It is high level state when resetting, after reset, enters idle condition, wait for link port and start, from
The link port loading procedure of DSP4.
Preferably, FLASH chip selects the M29W640FT of STMicroelectronics company
60ZA6, this chip have low in energy consumption, capacity is big, speed is fast, can retain information after power down, can
With advantages such as online programming writes, and can write by page successive byte, reading speed is high, with
EEPROM compares, and it has more superior performance and lower price.
Wherein, DSP3 and DSP4 undertakes main data processing task, and its data processing amount is more than
DSP1 and DSP2, DSP3 and DSP4 external 8,64 SDRAM of every 512Mbit respectively,
Expand 4G off-chip memory space, be used for storing ephemeral data, expand disposal ability.SDRAM
Select IS42S16320B；ADSP-TS201'sManagement IS42S16320B, its SDA10
Pin connects the A10 of IS42S16320B, and when normal read-write operation, this pin is address signal,
When IS42S16320B refresh count is full, ADSP-TS201 by this pin to IS42S16320B
Send refresh command signal, A14, A13 and the IS42S16320B in ADSP-TS201 address wire
BA1, BA0 be connected, for the group selection of IS42S16320B.DSP's Yu SDRAM
Annexation is as shown in Figure 7.
Sync cap is used, according to system clock frequency relative to traditional DRAM, SDRAM
Each periodic transfer once, has high data throughout.ADSP-TS201 has SDRAM
Memorizer, is very easy to the Interface design of SDRAM, without external circuits and consideration sequential,
Wherein control line and data wire can be directly connected to, and address wire then to be come according to concrete handling characteristics
Judge to adjust, it is only necessary to carry out simple Initialize installation to controlling depositor SDRCON.
SDRAM also can be shared by multiple DSP, and the SDRAM of multiple DSP output controls letter
The interconnection of number line, the input signal of SDRAM is driven by main DSP, detects input signal from DSP,
Make ADSP-TS201 ensure to synchronize to the refresh count of SDRAM, prevent when bus power handing-over
Carry out unnecessary refresh operation.
Wherein, FPGA connects has a transmission parallel port and to receive parallel port, upper level signal-processing board
Sending parallel port and connect the reception parallel port of next stage signal-processing board, FPGA receives by receiving parallel port
One stage signal processes the data of plate transmission, and the data after processing pass through transmission port transmission to next stage
Signal-processing board.
Opening up two FIFO inside FPGA and carry out ping-pong operation, for data cached, data are led to
After crossing the incoming FPGA in parallel port, cache at the FIFO within FPGA, then send data to DSP1
Carry out data process, it is achieved that the uninterrupted water operation of data.Preferably, employing clock is
The parallel port of the 32bit of 100MHz, it is achieved the message transmission rate of 3.2Gbps.
Wherein, FPGA connects an Asynchronous Serial Interface (ASI, Asynchronous Serial Interface)
Interface, ASI interface is connected with external equipment (such as recorder), carries out the storage of video data.
ASI interface has at a high speed, reliable, accurate, hot swappable advantage.
Wherein, FPGA connects one 422 interfaces, and preferably MAX3491ESD chip is with FPGA even
Connect, it is achieved 422 serial communication data transmitting-receivings；PC is communicated with system by 422 interfaces, real
Existing master control order loading, observation system state and master control carry out mutual, the state inspection of instruction and data
Survey, DSP program loads, parameter is arranged.
Wherein, FPGA connects a PCIE interface, and the data after processing are sent to host computer,
Data after processing are further processed by host computer.There is inside M29W640FT PCIe module,
This PCIe function structure chart as shown in Figure 4, is the internal module of FPGA in high order end dotted line frame,
Be the PCIe module of FPGA in middle solid box, in the dotted line frame of the right for FPGA interconnect upper
Machine.PCIe module include PCI Express interface module, GTX transceiver, Block RAM, time
Clock module and reseting module, wherein PCI Express interface module is realized by the built-in stone of V6 FPGA,
It is responsible for protocol logic；GTX transceiver includes dma controller, sends logic and receive logic module；
Block RAM includes sending caching and receiving cache module；Clock module is responsible for providing clock accurately,
Reseting module is used for providing reset signal, PCIE interface to provide the >=high-speed data of 3Gbit/s speed
Coffret, it is achieved that between plate, high speed pipelined data processes.
Wherein, FPGA connects a network interface, and the data after processing are sent to host computer, upper
Data after processing are further processed by machine.Preferably Ethernet interface control chip
Ethernet MACs module within 88E1111-XX-RCJ1C000, FPGA and Ethernet interface control
Coremaking sheet connects, it is achieved the HVN port transmission of data.
Wherein, every one-level signal-processing board of multi-DSP parallel procession system also includes power supply chip, uses
In powering for signal-processing board.
ADSP-TS201 kernel VDD uses low-voltage, the working method of big electric current, core current
Up to more than 2A, electric power outputting current ability should be at more than 3A, and now ADSP-TS201 is total
Internal power is about 2W, and chip power-consumption is bigger.Through considering, power supply chip selects
PTH08T250WAD, the electric current of its monolithic the highest exportable 50A, output voltage range is
0.7-3.6V, meets four DSP and simultaneously works in maximum power dissipation state.
Analog PLL power vd D-A is the phaselocked loop within DSP and frequency multiplier circuit is powered, each
Dsp chip all with the addition of decoupling circuit, for being filtered VDD-A.VDD, VSS with
VDD-A is connected by a 10uH inductance the most between the two, VDD, VSS and VDD-A
Respectively by 1 μ F capacity earth, one or two 1nF high frequency is set near VSS and VDD-A
Surface Mount electric capacity, VDD-A lead-in wire on PCB is away from noise source, by above-mentioned decoupling circuit to electricity
Source filters, and improves stability and the quality of power supply.
All DSP share VDD-IO, and selecting PTH08T230WAD chip is outside port, chain
Circuit, the I/O port of FPGA that crossing is relevant to external terminal output driver and logic drive and supply
Electricity, the current value of exterior I/O is about 4A.
The inside DRAM processor of ADSP-TS201 is powered by external voltage source,
The voltage request of VDD-DRAM power supply depends on the operation frequency of DSP, for 500MHz speed
The equipment of grade, VDD-DRAM needs the power supply of 1.50V, selects PTH08T230WAD to open
Close the VDD-DRAM that power supply is four DSP to power.
The power supply of ADSP-TS201 is provided with shunt capacitance decoupling, and shunt capacitance is close proximity to electricity
Source pin, the VDD_DRAM power supply of DSP at least places the high frequency of 6 1nF near its pin
Shunt capacitance, 2 10nF electric capacity and 4 0.1uF electric capacity.
FPGA connects power supply chip, for the upper electric control of DSP.Use metal-oxide-semiconductor break-make and
The charging interval of electric capacity controls the sequencing powered on, and specifically includes: utilize the conducting of metal-oxide-semiconductor
Characteristic first powers on as control signal, 1.0V, and the enable that then 1.0V powers on as 2.5V controls,
2.5V is as the upper electric control of 1.5V, it is achieved power on step by step, it is ensured that core voltage VDD-A of DSP
1.0V power at first, power on after the 2.5V of IO voltage VDD-IO, the 1.5V of VDD-DRAM
Finally power on.
Wherein, every one-level signal-processing board of multi-DSP parallel procession system also includes reset chip, uses
In providing reset signal for signal-processing board.Reset request signal is by ADSP-TS201 chip:
Core voltage, PLL power, I/O voltage, system and core clock and to initialize pin the most steady
After Ding, keep the low level of 2ms.Selecting MAX708 reset chip, this chip structure is simple,
Feature richness, has hand-reset function, can carry out manual reset at any time, be that a cost performance is the highest
Reset chip.
Signal-processing board is also provided with external reset button and LED, for identifying system program
Running status.
Wherein, every one-level signal-processing board of multi-DSP parallel procession system also includes clock module, choosing
With CY2308-1H clock matches device, it is complete that input clock signal is divided into 8 phase frequencies by it
Identical clock signal, wherein four tunnel clock signals are supplied to DSP, and wherein two-way is supplied to SDRAM,
Wherein a road is supplied to FPGA, and arbitrary clock signal so can be avoided other clocks because of reflection
Impact, it is ensured that each device clock synchronizes.
As in figure 2 it is shown, the system clock of ADSP-TS201 has four kinds, they respectively: during system
Clock (SCLK), core clock (CCLK), peripheral bus clock (SOCCLK) and link port are defeated
Go out clock (LxCLKOUT).Wherein system clock provides clock, and conduct for external bus port
The AC specification reference of external bus signal.Core clock be kernel, internal bus, memorizer and
Link port provides clock, CCLK=SCLK × SCLKRATx, wherein the value model of SCLKRATx
Enclose is 4～12.Peripheral bus clock, i.e. SOC bus operating frequencies, equal to 1/2 × CCLK.Chain
Crossing output clock equal to CCLK/CR, wherein CR be LCTLx medium velocity position is set, take it
Value scope is 1～4.
Consider according to external bus port speed and the factor such as CCLK, instruction execution speed,
In the present embodiment, SCLK takes 100MHz, for arranging the N value of the clock multiplier of PLL by three
Individual external pin SCLKRAT2-0 determine, these three pin connect pull-up resistor (inside have weak under
Pull-up resistor) whether weld adjustable Clock Multiplier Factor size, this coefficient takes 5 by default, at this moment
Core clock can be produced by SCLK frequency multiplication, i.e. core clock CCLK=N × SCLK=500MHz.
As shown in Figure 8, second embodiment of the invention provides a kind of many DSP utilizing first embodiment
The multi-DSP parallel procession method of parallel processing system (PPS), comprising:
Step A: initialize multi-DSP parallel procession system.
Step A specifically includes: the signal-processing board of multi-DSP parallel procession system powers on, FPGA
Control the electric sequence of DSP, arrangement reset signal and clock signal.
Step B: multi-DSP parallel procession system is configured.
Step B specifically includes: PC is ordered to multi-DSP parallel procession system loads by 422 interfaces
Order, arranges multi-DSP parallel procession systematic parameter.System is carried out by PC end by corresponding software
And control, software interface figure is as shown in Figure 3.
Step C: the FPGA of every grade of signal-processing board receives the data of upper level signal-processing board transmission,
And transfer data to a DSP of this grade of signal-processing board.
Step C specifically includes: the FPGA of every grade of signal-processing board receives upper level signal by parallel port
Process the data of plate transmission, and data are given by link port transmission the DSP1 of this grade of signal-processing board.
Wherein, the FPGA of first order signal-processing board receives initial data.
Step D a: DSP transfers data to other DSP of this grade of signal-processing board, all
DSP carries out parallel processing to data, and the data back after processing is to FPGA.
Step D specifically includes: data are given this grade of signal-processing board by link port transmission by DSP1
DSP2, DSP3, DSP4, DSP1, DSP2, DSP3, DSP4 carry out parallel processing to data,
And the data back after processing is to FPGA.
Data after step E:FPGA will process are transmitted to next stage signal-processing board.
Step E specifically includes: FPGA will process after data by and port transmission to next stage signal
Process plate.
Wherein, what N level signal-processing board obtained is target data, and target data is exported by FPGA
To host computer.
Wherein, during multi-DSP parallel procession method performs, PC is by passing through 422 interfaces
Communicate with system, carry out system mode observation and master control carries out that instruction and data is mutual, state
Detection etc..
So far, already in connection with accompanying drawing, the present embodiment has been described in detail.According to above description, this
The multi-DSP parallel procession system of the present invention and processing method thereof should have been had clearly by skilled person
The understanding of Chu.
It should be noted that in accompanying drawing or description text, the implementation not illustrating or describing,
It is form known to a person of ordinary skill in the art in art, is not described in detail.Additionally,
The above-mentioned definition to each element is not limited in various concrete structures, shape or the side mentioned in embodiment
Formula, it can be changed or replace, such as by those of ordinary skill in the art simply:
(1) FPGA and DSP can also select the chip of other models；
(2) the direction term mentioned in embodiment, such as " on ", D score, "front", "rear", " left ",
" right " etc., are only the directions with reference to accompanying drawing, are not used for limiting the scope of the invention；
(3) above-described embodiment can based on design and the consideration of reliability, being mixed with each other collocation use or
Using with other embodiment mix and match, the technical characteristic in i.e. different embodiments can be with independent assortment shape
Become more embodiment.
In sum, a kind of multi-DSP parallel procession system of the present invention and processing method thereof, there is N
Level signal-processing board, greatly improves signal handling capacity, can realize at a high speed and the number of high complexity
According to process；FPGA selects XC6VLX130T, XC6VLX130T cost performance height, internal resource
Abundant, macroelement quantity is many；DSP select ADSP-TS201, ADSP-TS201 fast operation,
High-performance static state superscale DSP operation, special optimization is provided to be applicable to communication and need at many DSP
The application of reason device；DSP algorithm and I/O excellent performance, instruction set is very flexible, supports high-level language
DSP architecture, it is simple to dsp program；It is extended to multicomputer system, only needs the lowest during connection
Communication overhead, drastically increase data processing speed and the ability of multi-DSP parallel procession system；
Data communication between DSP uses high-speed chain crossing to complete, bidirectional data transfers rate up to 1GB/s,
Realize seamless link, it is to avoid bus arbitration problem, there is the energy simultaneously processing the most different tasks
Power, highly-parallel, data transmission capabilities is strong, and motility is good；The FLASH chip that DSP connects is protected
There is the parameter that data process, improves system data processing speed；FLASH chip is selected
M29W640FT 60ZA6, it is low in energy consumption, capacity is big, speed is fast, can retain information after power down,
Can write with online programming, can write by page successive byte, reading speed is high, with EEPROM
Comparing, it has more superior performance and lower price；The SDRAM tool of the employing that DSP connects
Having high data throughout, DSP has SDRAM memory, simplifies the interface of SDRAM,
Without external circuits and consideration sequential；Data transmission between being realized by parallel port, message transmission rate
High, it is possible to achieve the message transmission rate of 3.2Gbps；The PCIE interface of FPGA provides >=3Gbit/s
The high speed data transmission interface of speed, it is achieved that between plate, high speed pipelined data processes；Pass through clock matches
Device distribution clock signal, it is to avoid other clocks are impacted by clock signal because of reflection, it is ensured that
Each device clock synchronizes.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect
Further describe, be it should be understood that the foregoing is only the present invention specific embodiment and
, be not limited to the present invention, all within the spirit and principles in the present invention, that is done any repaiies
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (10)
1. a multi-DSP parallel procession system, it is characterised in that including: N level signal-processing board,
Adjacent two-stage signal is processed and is connected by data-interface between plate；Wherein,
Every grade of signal-processing board includes that a FPGA and M sheet DSP, described FPGA receive upper one
The data of level signal-processing board transmission, described M sheet DSP carries out parallel processing to data, described
FPGA will process after data transmission to next stage signal-processing board, wherein, 1≤N≤100,2≤
M≤10。
2. multi-DSP parallel procession system as claimed in claim 1, it is characterised in that described M
Taking 4, the link port of described FPGA and four DPS connects, and every a piece of DSP all passes through link port
It is connected with the link port of other three DSP；
Described FPGA by the data that receive by link port transmission to DSP1, described DSP1 will
Data by link port transmission to DSP2, DSP3 and DSP4, described DSP1, DSP2, DSP3
With DSP4, data are carried out parallel processing, described DSP2, DSP3 and DSP4 will process after number
According to being transferred to described DSP1, after DSP1, DSP2, DSP3 and DSP4 are processed by described DSP1
Data be transferred to described FPGA, described FPGA will process after data transmit to next stage signal
Process plate.
3. multi-DSP parallel procession system as claimed in claim 2, it is characterised in that described FPGA
Select XC6VLX130T；And/or described DSP selects ADSP-TS201.
4. multi-DSP parallel procession system as claimed in claim 2, it is characterised in that described FPGA
Connect a piece of FLASH chip, be used for storing FPGA program；And/or described DSP4 connects a piece of
FLASH chip, is used for storing DSP program and systematic parameter；Described FLASH chip is selected
M29W640FT60ZA6；And/or described DSP3 and DSP4 external one group of SDRAM respectively, respectively
Expand 4G off-chip memory space, be used for storing ephemeral data.
5. multi-DSP parallel procession system as claimed in claim 1, it is characterised in that described FPGA
Connecting and have a transmission parallel port and to receive parallel port, the transmission parallel port of upper level signal-processing board connects next
The reception parallel port of level signal-processing board, FPGA receives upper level signal-processing board biography by receiving parallel port
Defeated data, the data after processing pass through transmission port transmission to next stage signal-processing board.
6. multi-DSP parallel procession system as claimed in claim 1, it is characterised in that described FPGA
Connecting an Asynchronous Serial Interface, described Asynchronous Serial Interface is connected with external equipment, carries out video data
Storage；And/or described FPGA connects one 422 interfaces, it is achieved and the serial communication between PC；
And/or described FPGA connects a PCIE interface and/or a network interface, the data after processing send
To host computer.
7. multi-DSP parallel procession system as claimed in claim 1, it is characterised in that described FPGA
Connect power supply chip, it is achieved the following electric sequence of DSP: core voltage VDD-A of DSP is at first
Powering on, power on after IO voltage, VDD-DRAM finally powers on.
8. multi-DSP parallel procession system as claimed in claim 4, it is characterised in that also include
CY2308-1H clock module, its input clock signal is divided into 8 phase frequencies identical time
Clock signal, wherein four tunnel clock signals are supplied to DSP, and wherein two-way is supplied to SDRAM, wherein
One tunnel is supplied to FPGA.
9. locate parallel based on the many DSP described in claim any one of claim 1 to 8 for one kind
The multi-DSP parallel procession method of reason system, it is characterised in that including:
Step A: initialize multi-DSP parallel procession system；
Step B: described multi-DSP parallel procession system is configured；
Step C: the FPGA of every grade of signal-processing board receives the data of upper level signal-processing board transmission,
And transfer data to a DSP of this grade of signal-processing board；And
Step D a: DSP transfers data to other DSP of this grade of signal-processing board, all
DSP carries out parallel processing to data, and the data back after processing is to FPGA；
Data after step E:FPGA will process are transmitted to next stage signal-processing board.
10. multi-DSP parallel procession method as claimed in claim 9, it is characterised in that described step
Rapid C specifically includes:
The FPGA of every grade of signal-processing board receives the data of upper level signal-processing board transmission by parallel port,
And data are given by link port transmission the DSP1 of this grade of signal-processing board；
Described step D specifically includes: data are given this grade of signal processing by link port transmission by DSP1
DSP2, DSP3, DSP4 of plate, data are carried out parallel by DSP1, DSP2, DSP3, DSP4
Process, and will process after data back to FPGA.
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