CN105183680B - Realize that PCIe interface turns the fpga chip and method of CF card interfaces - Google Patents
Realize that PCIe interface turns the fpga chip and method of CF card interfaces Download PDFInfo
- Publication number
- CN105183680B CN105183680B CN201510599657.9A CN201510599657A CN105183680B CN 105183680 B CN105183680 B CN 105183680B CN 201510599657 A CN201510599657 A CN 201510599657A CN 105183680 B CN105183680 B CN 105183680B
- Authority
- CN
- China
- Prior art keywords
- module
- data
- card
- interface
- pcie
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3804—Memory card connected to a computer port directly or by means of a reader/writer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
Realize that PCIe interface turns the fpga chip and method of CF card interfaces, be related to PCIe interface and turn CF card interfaces field, including：PCIe IP kernels module, adaptation module, direct memory access module, CF card interfaces protocol module and control register, instructed for PIO classes, control register control CF card interface protocol modules, command content is formed into corresponding CF card interfaces instruction sequencing；Instructed for Ultra direct memory access class, direct memory access module is controlled by control register, maximum bus burst transfer length, CPU side storage address and this transmission data length are set, direct memory access module waits the ready request in data/space that CF card interface protocol modules provide, and control register control CF card interfaces protocol module sends the transmission instruction of Ultra direct memory access；The present invention can be applicable the different demands of different usage scenarios, and flexibility is high.
Description
Technical field
The present invention relates to PCIe interface to turn CF card interfaces field, in particular to realizes that PCIe interface turns CF card interfaces
Fpga chip and method.
Background technology
With PCIe, (Peripheral Component Interconnect express, Peripheral Component Interconnect standard connect
Mouthful) technology reach its maturity and high performance characteristics, CPU Peripheral Interfaces are limited, use the application of PCIe interface carry external equipment
It is more and more extensive.CF (Compact Flash, the data storage device of portable electric appts) cards are as a kind of general reliable
Removable portable memory, has extensive demand, CF card interfaces meet PATA in communication equipment and industrial equipment
The definition of (Parallel Advanced Technology Attachment, parallel hard-disk interface technology) interface protocol.
The bridging functionality chip species that PCIe interface turns CF card interfaces is less, and existing PCIe interface turns the core of CF card interfaces
Piece, it is uniformly to produce, and for some specific demands in different usage scenarios, such as start by set date data transfer, DMA moulds
Block actively initiates data transfer, the functions such as CF card interfaces sequential is configurable, can not meet to require one by one, flexibility is low, it is impossible to
Adapt to a variety of usage scenarios.
The content of the invention
For defect present in prior art, realize that PCIe interface turns CF clampings it is an object of the invention to provide one kind
The fpga chip and method of mouth, can be applicable the different demands of different usage scenarios, and flexibility is high.
To achieve the above objectives, the present invention takes a kind of fpga chip realized PCIe interface and turn CF card interfaces, connects respectively
CPU and CF cards are connect, including：PCIe IP kernel modules, for providing standard PCIe interface to CPU；Adaptation module, for PCIe IP
Adaptation of the interface bus of core module to local bus；Direct memory access module, it is connected with PCIe IP kernel modules, for sending out
Play the data transfer between CF cards and CPU；CF card interface protocol modules, are connected with direct memory access module, for CF cards
The interface for meeting parallel hard-disk interface technology is provided；Control register, it is articulated in by adaptation module under the space of PCIe base address,
For controlling direct memory access module and CF card interface protocol modules.
On the basis of above-mentioned technical proposal, the interface bus of the PCIe IP kernels module is total for Avalon buses or AXI
Line.
On the basis of above-mentioned technical proposal, the control register includes the direct interior of control direct memory access module
Deposit access controller, and the CF card controllers of control CF card interface protocol modules.
On the basis of above-mentioned technical proposal, the direct memory access module includes sending direction controller, recipient
To controller and First Input First Output module, sending direction controller is used to control direct memory access module by PCIe IP kernels
Module reads the data for needing to write CF cards, receives direction controller and is used to control direct memory access module, reads CF clampings
The data that mouth protocol module is read from CF cards, First Input First Output module include two First Input First Outputs, are respectively used to deposit
Store up the data for needing to write CF cards and the data read in the card from CF.
On the basis of above-mentioned technical proposal, in the First Input First Output for storing the data for needing to write CF cards,
When data volume reaches bus burst transfer length, data transfer is initiated to CF card interfaces protocol module.
On the basis of above-mentioned technical proposal, in the First Input First Output for storing the data read from CF cards,
When data volume reaches interface bus length corresponding with PCIe IP kernel modules, PCIe IP are passed through by direct memory access module
Core module writes data to CPU.
On the basis of above-mentioned technical proposal, CF card controllers in the control register also include module register,
Instruction FIFO register, read First Input First Output register and write First Input First Output register, module control is posted
Storage is used to configure interface sequence, each First Input First Output depth, First Input First Output threshold values.
The present invention also provides a kind of method realized PCIe interface and turn CF card interfaces, including：
Instructed for PIO classes, control register control CF card interface protocol modules, command content is formed into corresponding CF cards
Interface instruction sequential, if PIO reading instructions, the data that CF cards return are stored in control register, posted by reading control
Storage obtains data；If PIO write commands, the data are reflected in interface sequence；
Instructed for Ultra direct memory access class, direct memory access module is controlled by control register, set most
Big bus burst transfer length, CPU side storage address and this transmission data length, direct memory access module wait CF clampings
The ready request in data/space that mouth protocol module provides, control register control CF card interfaces protocol module send Ultra
Direct memory access transmission instruction；If writing the instruction of data to CF cards, when control register storage data quantity is less than threshold values,
Direct memory access module reads data from CPU side, and is stored in control register, by CF card interface protocol modules according to CF
Interface sequence writes CF cards；If CF cards read the instruction of data, then CF card interfaces protocol module reads destination address in CF cards
Data, and be stored in control register, when storage data volume is higher than threshold values, internal storage access module directly reads purpose by several times
The data of address, and write CPU side.
On the basis of above-mentioned technical proposal, the control register includes the CF controls of control CF card interface protocol modules
Device processed, CF card controllers include module register, instruction FIFO register, read First Input First Output register and write
First Input First Output register；If PIO reading instructions, the data that CF cards return are stored in and read First Input First Output register
In；If PIO write commands, by software elder generation configuration-direct First Input First Output register, it is reconfigured at writing First Input First Output deposit
Device, finally the data be reflected in interface sequence.
On the basis of above-mentioned technical proposal, the control register includes the CF controls of control CF card interface protocol modules
Device processed, CF card controllers include module register, are instructed for Ultra direct memory access class, by controlling CF card controllers
Configure direct memory access module maximum bus burst transfer length, CPU side storage address and this transmission data length.
The beneficial effects of the present invention are：
1st, CF Master (CF card interfaces agreement) module realizes PATA interface function, the CF cards in control register
Under controller control, PIO (parallel input output, parallel input and output), DMA (Direct are combined into
MemoryAccess, direct memory access) etc. interface sequence corresponding to instruction, realize the PATA patterns of standard, it is achieved thereby that
Control to CF card apparatus, available for other ATA/ATAPI equipment.
2nd, the CF card controllers in control register include module register, instruction FIFO (First Input First
Output, First Input First Output) register, to read fifo register and write fifo register, module register is used to configure interface
Sequential, each FIFO depth, FIFO threshold values, and be transmitted, abnormal ending transmission etc. state reporting function；It is each
Fifo register is the interface for accessing each FIFO, for being continuously written into instruction, caching transmission data, improves efficiency of transmission.
3rd, dma module can be realized and actively initiate interacting for data and CPU side data in EMS memory in CF cards, it would be preferable to support
After the free time of a period of time, data renewal is initiated in timing.
Brief description of the drawings
Fig. 1 realizes that PCIe interface turns the fpga chip use state diagram of CF card interfaces for the present invention；
Fig. 2 realizes that PCIe interface turns the structural representation of the fpga chip of CF card interfaces for the present invention；
Fig. 3 is the detailed construction schematic diagram of dma module in Fig. 2.
Reference：
Fpga chip 1, CPU 2, CF cards 3,
PCIe IP kernels module 11, adaptation module 12, dma module 13, CF Master modules 14, control register 15；
First interface 131, second interface 132, sending direction controller 133, fifo module 134, receive direction controller
135, dma controller 151, CF controllers 152.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
As shown in figure 1, the present invention realizes that PCIe interface turns the fpga chip 1 of CF card interfaces, CPU 2 and CF cards are connected respectively
3, for realizing on pcb board carry CF card memory appts under CPU 2 PCIe interface, or individually the small boards of PCB realize PCIe
Interface turns CF interface functions.Wherein, CPU2 is connected by PCIe interface with fpga chip 1, and CF cards 3 pass through CF card interfaces and FPGA
Chip 1 is connected, and CF card interfaces meet the PATA (definition of interface protocol.In order to facilitate the connection of CF cards 3, CF card interfaces are generally adopted
With the form of CF card slots, interpolation CF cards 3 can be with connection PCB signal and the pin signal of CF cards 3.
As shown in Fig. 2 the present invention realizes that PCIe interface turns the fpga chip 1 of CF card interfaces, it can use and carry PCIe IP
Based on the FPGA models of stone, as the FPGA of more money difference class of Altera, Xilinx company is satisfied by requiring.It is described
Fpga chip 1 includes PCIe IP kernels module 11, adaptation module 12, DMA, and (Direct Memory Access, direct internal memory are visited
Ask) module 13, CF Master modules 14 and control register 15, PCIe IP kernels module 11 is connected with CPU 2, for CPU
Offer standard PCIe interface.Wherein, the interface bus of PCIe IP kernels module 11 is different according to selected basic FPGA, right
In the FPGA of altera corp, interface is Avalon buses；For the FPGA of Xilinx companies, interface is AXI buses, this implementation
In example by taking the FPGA of altera corp as an example.The adaptation module 12 is articulated in PCIe Bar0 (PCIe base address) space, is used for
Adaptation of the interface bus of PCIe IP kernels module 11 to local bus.Dma module 13 connects the module of PCIe IP kernels module 11, uses
Data transfer between initiation CF cards and CPU.CF Master modules 14 are connected with dma module 13 respectively, for being carried to CF cards
Interface for meeting PATA.Control register 15 is articulated under PCIe Bar0 by adaptation module 12, for receiving adaptation module
12 register commands sent, it is additionally operable to connect and controls dma module 13 and CF Master modules 14.In more detail, control is posted
Storage 15 includes the dma controller 151 of control dma module 13, includes the CF card controllers of control CF Master modules 14
152。
As shown in figure 3, the dma module 13 includes first interface 131 (Master corresponding with PCIe IP kernels module 11
For AXI/Avalon), with the corresponding second interface 132 (Master AHB) of CF Master modules 14, in addition to sending direction
Controller 133 (TX Ctrl), receive direction controller 135 and FIFO (First Input First Output, FIFO
Queue) module 134, fifo module 134 includes two FIFO, is sending direction FIFO respectively, receives direction FIFO, sending direction
FIFO is used to store the data for needing to write CF cards；Direction FIFO is received to be used to store the number read from CF cards
According to.Sending direction controller 133 is used to control dma module 13, and by PCIe IP kernels mould, 11 pieces are read the number for needing to write CF cards
According to, i.e. the data for needing to write CF cards are read in the active of dma module 13 from the memory of CPU side.The data for needing to write CF cards are deposited
Storage is to the sending direction FIFO in fifo module 134, when the data volume stored in sending direction FIFO reaches AHB Burst
During (Advanced High-performance Bus buses burst transfer) length, initiate data to CF Master modules 14 and pass
It is defeated, interrupt notification CPU after transmission is completed, discharges CPU in transmitting procedure.Direction controller 135 is received to be used to control dma module
13, the data that CF Master modules 14 are read from CF cards are read, and store into fifo module 134 and receive direction FIFO, tool
Body is：When the data that CF Master modules 14 are read from CF cards reach AHB Burst length, CF Master modules 14 pass through
Signal notifies dma module 13, and dma module actively initiates AHB interface read data transmission by second interface 132, from CF Master
Data are obtained in module 14 and are stored in fifo module 134.When the data volume received in the FIFO of direction reaches PCIe IP kernel moulds
During interface bus corresponding to block (such as AvalonBurst) length, CPU side is write data to by PCIe IP kernels module 11
Memory, interrupt notification CPU after transmission is completed, discharges CPU in transmitting procedure.
The CF Master modules 14 realize the function of PATA interfaces, including PIO read-writes, DMA read-writes, equipment identification etc.
Command operating, PATA patterns are realized, it is achieved thereby that the control to CF cards (can also be other ATA/ATAPI) equipment.Institute
State CF card controllers 152 in control register 15 and also include module register, instruction FIFO register, read fifo register and
Fifo register is write, module control register is used to configure matching somebody with somebody for the parameters such as interface sequence, each FIFO depth, FIFO threshold values
Put, and be transmitted, the function of the state reporting such as abnormal ending transmission, (instruction FIFO is deposited for each fifo register
Device, read fifo register and write fifo register) it is the interface for accessing each FIFO (being located in CF Master modules 14), use
To be continuously written into instruction, caching transmission data, improve efficiency of transmission.
Such as Fig. 1 to Fig. 3, the present invention realizes that PCIe interface turns the method for CF card interfaces, specifically includes following two parts：
(it is a kind of data-transmission mode defined in CF interfaces, is mainly used in protocol-dependent instruction for the instruction of PIO classes
Transmission, it can also be used to data transfer, belong to the data transfer of the transmission means of low speed), the CF controllers in control register 15
Instruction FIFO register in 152 control CF Master modules 14, CF Master modules 14 can be according to the command contents of configuration
Corresponding CF card interfaces instruction sequencing is formed, if PIO reading instructions, the data that CF cards return are stored in CF Master modules
In reading fifo register in 14；If PIO write commands, after software elder generation configuration-direct fifo register, configurable write FIFO is posted
The data are reflected on the interface sequence of CF cards 3 by storage, last CF Master modules 14.
Instructed for Ultra DMA classes, the efficient biography of chunk data is realized by the control dma module 13 of control register 15
It is defeated, by the dma controller 151 in software merit rating control register 15, set maximum burst (bus burst transfer) length,
CPU side storage address and this transmission data length, software, which is opened in dma controller 151, controls the work of dma module 13 to open
Close, dma module 13 waits the ready request in data/space that CF Master modules 14 provide.In configuration control register 15
CF controllers 152, control CF Master modules 14 send the instruction of Ultra DMA transfers, if writing the instruction of data to CF cards,
In CF card controllers 152 when writing data volume in fifo register and being less than threshold values, CF Master modules 14 pass through tx_req signals
Dma module 13 is notified, dma module 13 starts actively from CPU side storage purpose address, and (Avalon is total according to Avalon Burst
Line burst transfer) length reads data by several times, and actively writes data into and write in fifo register, and then CF Master modules
These data are write CF cards by 14 according to CF interface sequences.If CF cards read the instruction of data, then CF Master modules 14 are initiated
CF interface sequences read the data of destination address in CF cards, and are stored in the reading fifo register of CF card controllers 152, work as storage
When data volume is higher than threshold values, dma module 13 reads and reads fifo register to obtain data by several times according to AHB Busrt length, and
These data are actively write into CPU side storage purpose address.One Ultra DMA command usually requires multiple burst could be complete
Into data transfer, actively initiated by DMA in this transmitting procedure, release CPU improves system effectiveness.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (10)
1. a kind of fpga chip realized PCIe interface and turn CF card interfaces, CPU and CF cards are connected respectively, it is characterised in that including：
PCIe IP kernel modules, for providing standard PCIe interface to CPU；
Adaptation module, for PCIe IP kernel modules interface bus to local bus adaptation；
Direct memory access module, it is connected with PCIe IP kernel modules, for initiating the data transfer between CF cards and CPU；
CF card interface protocol modules, are connected with direct memory access module, for meeting parallel hard-disk interface skill to CF card offers
The interface of art；
Control register, be articulated in by adaptation module under the space of PCIe base address, for control direct memory access module and
CF card interface protocol modules.
2. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 1, it is characterised in that：The PCIe IP
The interface bus of core module is Avalon buses or AXI buses.
3. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 1, it is characterised in that：The control deposit
Device includes the direct memory access controller of control direct memory access module, and the CF cards of control CF card interface protocol modules
Controller.
4. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 3, it is characterised in that：The direct internal memory
Access modules include sending direction controller, receive direction controller and First Input First Output module, and sending direction controller is used
The data for needing to write CF cards are read by PCIe IP kernels module in control direct memory access module, direction controller is received and uses
In control direct memory access module, the data that CF card interfaces protocol module is read from CF cards, First Input First Output mould are read
Block includes two First Input First Outputs, is respectively used to what is stored the data for needing to write CF cards and read in the card from CF
Data.
5. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 4, it is characterised in that：Needed for storing
Write in the First Input First Output of the data of CF cards, when data volume reaches bus burst transfer length, assisted to CF card interfaces
Discuss module and initiate data transfer.
6. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 4, it is characterised in that：For store from
In the First Input First Output of the data read in CF cards, when data volume reaches interface bus length corresponding with PCIe IP kernel modules
When spending, CPU is write data to by PCIe IP kernel modules by direct memory access module.
7. realize that PCIe interface turns the fpga chip of CF card interfaces as claimed in claim 4, it is characterised in that：The control deposit
CF card controllers in device also include module register, instruction FIFO register, read First Input First Output register
With write First Input First Output register, module control register is used to configure interface sequence, each First Input First Output depth, elder generation
Enter first dequeue threshold values.
8. PCIe interface turns the method for CF card interfaces to a kind of realizing based on fpga chip described in claim 1, it is characterised in that
Including：
Instructed for PIO classes, control register control CF card interface protocol modules, command content is formed into corresponding CF card interfaces
Instruction sequencing, if PIO reading instructions, the data that CF cards return are stored in control register, by reading control register
Obtain data；If PIO write commands, the data are reflected in interface sequence；
Instructed for Ultra direct memory access class, direct memory access module is controlled by control register, set maximum total
Line burst transfer length, CPU side storage address and this transmission data length, direct memory access module wait CF card interfaces association
The ready request in data/space that view module provides, it is direct that control register control CF card interfaces protocol module sends Ultra
Internal storage access transmission instruction；If writing the instruction of data to CF cards, when control register storage data quantity is less than threshold values, directly
Internal storage access module reads data from CPU side, and is stored in control register, by CF card interfaces protocol module according to CF interfaces
Sequential writes CF cards；If CF cards read the instruction of data, then CF card interfaces protocol module reads the data of destination address in CF cards,
And be stored in control register, when storage data volume is higher than threshold values, internal storage access module directly reads destination address by several times
Data, and write CPU side.
9. realize that PCIe interface turns the method for CF card interfaces as claimed in claim 8, it is characterised in that：The control register bag
The CF card controllers of control CF card interface protocol modules are included, CF card controllers include module register, instruction FIFO
Register, read First Input First Output register and write First Input First Output register；If PIO reading instructions, CF cards are returned
Data, which are stored in, to be read in First Input First Output register；If PIO write commands, posted by software elder generation configuration-direct First Input First Output
Storage, it is reconfigured at writing First Input First Output register, finally the data are reflected in interface sequence.
10. realize that PCIe interface turns the method for CF card interfaces as claimed in claim 8, it is characterised in that：The control register
CF card controllers including controlling CF card interface protocol modules, CF card controllers include module register, directly interior for Ultra
Deposit and access class instruction, by controlling CF card controllers to configure direct memory access module maximum bus burst transfer length, CPU side
Storage address and this transmission data length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510599657.9A CN105183680B (en) | 2015-09-18 | 2015-09-18 | Realize that PCIe interface turns the fpga chip and method of CF card interfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510599657.9A CN105183680B (en) | 2015-09-18 | 2015-09-18 | Realize that PCIe interface turns the fpga chip and method of CF card interfaces |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105183680A CN105183680A (en) | 2015-12-23 |
| CN105183680B true CN105183680B (en) | 2018-03-20 |
Family
ID=54905770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510599657.9A Active CN105183680B (en) | 2015-09-18 | 2015-09-18 | Realize that PCIe interface turns the fpga chip and method of CF card interfaces |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105183680B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109478166A (en) * | 2016-07-08 | 2019-03-15 | 深圳市大疆创新科技有限公司 | For storing the method and system of image |
| CN107180005A (en) * | 2017-06-15 | 2017-09-19 | 烽火通信科技股份有限公司 | CF cards realize the method and system of warm connection function |
| CN107590092A (en) * | 2017-10-23 | 2018-01-16 | 济南浪潮高新科技投资发展有限公司 | A kind of PCIE based on FPGA turns EMC bridges |
| CN108227614A (en) * | 2018-01-25 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of data flow control module based on FPGA, control method and circuit |
| CN110196824B (en) * | 2018-05-31 | 2022-12-09 | 腾讯科技（深圳）有限公司 | Method and device for realizing data transmission and electronic equipment |
| CN108920391A (en) * | 2018-06-26 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of Nand Flash translation interface and data transfer device |
| CN111736792B (en) * | 2019-03-25 | 2024-02-06 | 西安诺瓦星云科技股份有限公司 | Programmable logic device, control method and control system thereof and video processor |
| CN110109857A (en) * | 2019-04-29 | 2019-08-09 | 杭州迪普科技股份有限公司 | A kind of data transmission method and device |
| CN110990310B (en) * | 2019-12-19 | 2020-11-24 | 山东方寸微电子科技有限公司 | Device side SD controller, control method and electronic device |
| CN111414325B (en) * | 2020-02-29 | 2021-09-17 | 苏州浪潮智能科技有限公司 | Method for converting Avalon bus into Axi4 bus |
| CN111666237B (en) * | 2020-06-08 | 2022-06-28 | 王斌 | DMA controller with cache management function |
| CN112256603B (en) * | 2020-10-29 | 2023-02-28 | 浪潮电子信息产业股份有限公司 | Server and expansion equipment based on OCP |
| CN114168520B (en) * | 2021-12-13 | 2023-08-25 | 航天新长征大道科技有限公司 | Optical fiber communication bus device, equipment and system |
| CN114595171A (en) * | 2022-02-21 | 2022-06-07 | 杭州加速科技有限公司 | PCIE-to-GPIB interface conversion device and use method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1458559A (en) * | 2002-05-15 | 2003-11-26 | 希旺科技股份有限公司 | Electronic peripheral card with multiple I/O interfaces |
| CN101980258A (en) * | 2010-11-11 | 2011-02-23 | 四川省绵阳西南自动化研究所 | Cache-containing high-speed compact flash (CF) card |
| CN103530265A (en) * | 2013-10-24 | 2014-01-22 | 烽火通信科技股份有限公司 | Device and method for realizing safe hot plugging of CF card of electronic equipment |
| CN103559152A (en) * | 2013-10-31 | 2014-02-05 | 烽火通信科技股份有限公司 | Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol |
| CN104270341A (en) * | 2014-09-03 | 2015-01-07 | 烽火通信科技股份有限公司 | A data protocol forwarding system and method in an IPRAN |
-
2015
- 2015-09-18 CN CN201510599657.9A patent/CN105183680B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1458559A (en) * | 2002-05-15 | 2003-11-26 | 希旺科技股份有限公司 | Electronic peripheral card with multiple I/O interfaces |
| CN101980258A (en) * | 2010-11-11 | 2011-02-23 | 四川省绵阳西南自动化研究所 | Cache-containing high-speed compact flash (CF) card |
| CN103530265A (en) * | 2013-10-24 | 2014-01-22 | 烽火通信科技股份有限公司 | Device and method for realizing safe hot plugging of CF card of electronic equipment |
| CN103559152A (en) * | 2013-10-31 | 2014-02-05 | 烽火通信科技股份有限公司 | Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol |
| CN104270341A (en) * | 2014-09-03 | 2015-01-07 | 烽火通信科技股份有限公司 | A data protocol forwarding system and method in an IPRAN |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105183680A (en) | 2015-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105183680B (en) | Realize that PCIe interface turns the fpga chip and method of CF card interfaces | |
| CN106874224B (en) | Multi-line SPI-Flash controller capable of automatically carrying and adapting to device | |
| CN107203484B (en) | PCIe and SRIO bus bridging system based on FPGA | |
| CN106951388B (en) | PCIe-based DMA data transmission method and system | |
| CN107077304B (en) | Data conversion equipment, chip, method, apparatus and image system | |
| US20160342547A1 (en) | Host bus access by add-on devices via a network interface controller | |
| CN110196824A (en) | Realize method and device, the electronic equipment of data transmission | |
| CN111931442B (en) | FPGA embedded FLASH controller and electronic device | |
| CN105824777A (en) | Method for implementing SPI (Serial Peripheral Interface) bus in IPRAN (Internet Protocol Radio Access Network) equipment | |
| CN108959136B (en) | SPI-based data transmission accelerating device and system and data transmission method | |
| JP2018502406A (en) | Multi-channel I2S transmission control system and method | |
| CN105892359A (en) | Multi-DSP parallel processing system and method | |
| CN102521190A (en) | Hierarchical bus system applied to real-time data processing | |
| CN109634901A (en) | A kind of data transmission system and its control method based on UART | |
| CN105356988A (en) | PCIe based full duplex DMA transmission method | |
| CN105718396B (en) | A kind of I of big data master transmissions2C bus units and its means of communication | |
| WO2004102411A1 (en) | Controller interface | |
| CN116776781B (en) | Register parameter management method, system, equipment and storage medium | |
| CN109522251A (en) | A kind of high-speed synchronous serial port board and its working method based on PXIe bus | |
| Kavianipour et al. | High performance FPGA-based scatter/gather DMA interface for PCIe | |
| KR20120134918A (en) | Electronic apparatus including a plurality of processors | |
| US20090138673A1 (en) | Internal memory mapped external memory interface | |
| CN105550133A (en) | AXIS-FIFO bridge circuit based on ZYNQ and data transmission method using same | |
| CN104156336A (en) | Control method of USB2.0 interface chip | |
| CN109800194A (en) | SDIO interface data transmission method and device based on linux system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |