CN103559152A - Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol - Google Patents
Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol Download PDFInfo
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Abstract
The invention discloses a device and a method for a CPU (central processing unit) to access a local bus on the basis of a PCIE (peripheral component interface express) protocol, which relate to the field of IPRAN (internet protocol radio access network). The device comprises a PCIE interface module, a data conversion module and a local bus interface module, wherein the PCIE interface module is used for realizing the PCIE underlying protocol, so that the device is used as one PCIE slave-end device to work under a PCIE system; the local bus interface module is used for simulating the time sequence of a traditional local bus and realizing the reading-writing access to an FPGA (field programmable gate array) local register or an external chip which is bridged through the FPGA. By Adopting the device and method, the highest possibility and performance can be obtained on the premise of consuming the least logic resource, the complexity in designing a PCIE interface transmission layer can be effectively simplified, the reading-writing efficiency of the system can be remarkably improved, and different local bus time sequences can be provided in real time.
Description
Technical field
The present invention relates to IPRAN field, particularly relate to a kind of device and method of the CPU access local bus based on PCIE agreement.
Background technology
Along with based on IP(Internet Protocol, Internet protocol) transmission network development, at IPRAN(IP Radio Access Network Carrier, IPization wireless backhaul bearer network) main card CPU(Central Processing Unit in equipment, central processing unit) need to carry out exchanges data with numerous acp chips and subcard, from the viewpoint of the maintenance of device tree, interface, simplify and data transmission efficiency etc. traditional localbus(local bus) be difficult to be competent at this work.PCIE(Pedpherd Component Interconnect Express, quick component interconnection) as a kind of maturation and widely used local bus technology, because its device tree is easy to safeguard, interface is simple, message transmission rate advantages of higher, be specially adapted to the exchanges data of CPU and peripheral hardware.
In the various device of optical-fiber network, CPU is indispensable function for the read and write access of local bus.CPU need to be to configuration register value of writing of local parts (FPGA design cell or local chip), thereby local parts are worked under predetermined mode of operation, and CPU also needs to read status register, the data buffer storage of local parts to be realized monitoring function and extracts the required data of protocol algorithm.
FPGA(Field Programmable Gate Array in the past, field programmable gate array) read-write interface that is designed to CPU and provides is generally local bus interface, local bus interface is comprised of chip selection signal (cs), read-write (rw), 32 bit address signals (addr), 8/16/32 bi-directional data signal (data), the advantage of this interface is that sequential is simple, easy to use, but the shortcoming of local bus is also fairly obvious:
(1) read-write efficiency is low: each read-write operation of CPU can only transmit a register data.
(2) device tree is difficult in maintenance and extendability is poor: for different peripheral hardwares, CPU distinguishes by different chip selection signals, and CPU need to access how many peripheral hardwares, and how many chip selection signals just should be provided.
(3) transfer rate is low, and it is large that hardware is realized cost: local bus is parallel bus, and it is only tens megahertzes that the cross-interference issue of parallel bus makes its reliably working frequency, and the PCB cabling of parallel bus is also very complicated simultaneously.
PCIE is a kind of HSSI High-Speed Serial Interface agreement being proposed by intel, is characterized in high speed serialization point-to-point transmission, has very high bandwidth.The terminal device that PCIE bus connects exclusively enjoys channel bandwidth, is the main flow trend of current local bus.Than traditional local bus, the advantage that the read-write interface of CPU is upgraded to PCIE interface is fairly obvious:
(1) read-write efficiency is high: the data upper limit of each PCIE read-write message transmissions is minimum is 128 bytes, can pass through DMA(Direct Memory Access, direct memory access simultaneously) mode promotes the work efficiency of CPU.
(2) plant maintenance is simple: the base address of PCIE device is by system software dynamic assignment, and different PCIE devices is distinguished by PCIE base address in PCIE bus territory, and supports the hot plug of PCIE device.
(3) transfer rate is high, and hardware line is simple: hardware line only need bi-directional data and reference clock several to differential lines, PCIE interface is HSSI High-Speed Serial Interface, the minimum speed limit of single path is 2.5Gbps.
But the cpu i/f that will realize FPGA design in IPRAN equipment upgrades to PCIE interface by local bus interface, realize the memory read/write message of PCIE interface and the conversion of local bus operation, also exist at present following technical matters urgently to be resolved hurrily:
(1) externally need to provide the PCIE interface of standard, requirement can be processed PCIE message, and as an EP(Endpoint, PCIE is from end equipment) communicate by letter with CPU.
(2) internally need to provide the local bus interface that can join flexibly, as supported from end reply pattern, the characteristic such as the operating cycle is adjustable, realize with in the past for the compatibility of the FPGA design of local bus interface exploitation.
(3) need to define the data structure corresponding relation of PCIE interface and local bus interface.
Summary of the invention
The object of the invention is in order to overcome the deficiency of above-mentioned background technology, a kind of device and method of the CPU access local bus based on PCIE agreement is provided, can under the prerequisite of consumes least logical resource, obtain the highest reliability and performance, effectively simplify the complexity of PCIE interface transport layer design, significantly improve the read-write efficiency of system, different local bus sequential is provided in real time.
The device that the invention provides a kind of CPU access local bus based on PCIE agreement, comprises PCIE interface module, data conversion module and local bus interface module, wherein:
Described PCIE interface module, for: realize PCIE underlying protocol, make this device under PCIE system as a PCIE from the work of end equipment;
Described data conversion module, for: realize the entrained data layout of PCIE read-write message and the conversion of local bus data layout;
Described local bus interface module, for: simulate traditional local bus sequential, realize to the local register of FPGA or via the read and write access of the external chip of FPGA bridge joint.
On the basis of technique scheme, described PCIE interface module designs according to the three-decker of PCIE protocol definition, the PCIE stone that the Physical layer of PCIE interface and data link layer functions are carried by FPGA device completes, PCIE stone is realized the processing of configuration space, PCIE data link layer and Physical layer message of PCIE interface, the link training function of PCIE link, realize the bottom passage of PCIE link, the transport layer logic of PCIE interface module is communicated by letter with the user side interface of PCIE stone, realizes the processing of PCIE read-write message.
On the basis of technique scheme, described PCIE Design of Interface Module flow control mechanism: utilize PCIE read-write message that the user side interface place of PCIE stone provides to receive enable signal and be designed with control submodule, it is not busy controlling submodule original state, when client layer receives a PCIE read-write message, control submodule and transfer busy condition to, when control submodule is busy condition, will close the user side interface of PCIE stone, the PCIE read-write packet buffer of this stylish reception is in PCIE stone; Complete after the processing of a PCIE read-write message, control submodule and return to not busy state, reopen the user side interface of PCIE stone; In the situation that CPU sends PCIE read-write message continuously, above flow process loops, until all PCIE read-write messages are disposed in PCIE stone buffer memory.
On the basis of technique scheme, described data conversion module is write with CPU and is read the data buffer storage that two data transfer directions arrange suitable capacity at CPU, the buffer memory capacity of data conversion module is all designed to the twice of PCIE read-write message maximum data capacity 32 double words, i.e. 256 bytes, data-switching corresponding relation is 32 bit data of the corresponding local bus operation of a double word of PCIE read-write message data; In PCIE read-write message, four bytes of a double word are that large end is arranged.
On the basis of technique scheme, described local bus interface module has been combined the timing of local bus sequential by counter, counter works clock is 125Mhz, counter combination comprises double word counter and period counter, wherein double word counter is the high-positioned counter of period counter, double word counter shows which double-word data at transmission PCIE message, be which local bus operating cycle, period counter shows how many 125Mhz clock period of transmission needs of each double-word data; The length field of PCIE message has determined the maximum count value of double word counter, double word counter reads and writes at the moment or the PCIE that reset, PCIE interface mould receives PCIE read-write message the moment zero clearing that message is finished dealing with, period counter is except above condition, also zero clearing when meeting carry condition; Period counter each 125Mhz rising edge clock between each double-word data transmission period adds one, and after reaching carry condition, period counter zero clearing simultaneously double word counter adds one.
On the basis of technique scheme, described local bus interface module realizes by operator scheme and two parameters of operation width the local bus sequential that can join flexibly, operator scheme has general mode and from end reply pattern, when this block configuration is general mode, the carry condition of period counter is to equal to operate width parameter, be the length in local bus operating cycle corresponding to the assignment of operation width parameter, this module supports under general mode the local bus operating cycle adjustable by 6-240 125Mhz clock period; This block configuration is during from end reply pattern, now operates width parameter invalid, and the carry condition of this module period counter is to receive from reply or the stand-by period of end to surpass 240 125Mhz clock period.
On the basis of said apparatus, the present invention also provides a kind of method of the CPU access local bus based on PCIE agreement, comprises the following steps:
CPU comprises two separate processes of write and read to the access method of local bus, is described below respectively:
(1) write the realization of process:
First, PCIE interface module is processed PCIE and is write message in writing process, be that the storer that CPU sends is write message, the storer sending for CPU is write message, the data that PCIE interface module extraction CPU writes, the start address that CPU writes, three fields of length that CPU writes, the data that PCIE interface module is write CPU, start address, data length are submitted to data conversion module, and the start address of simultaneously CPU being write, length are submitted to local bus interface module;
Then, data conversion module buffer memory in writing process is write data, start address, data length from the CPU of PCIE interface module, data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus write operations, when each local bus write cycles starts, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides data and the address of this local bus write operation;
Finally, local bus interface module is responsible for the generation that local bus is write sequential in writing process, when each local bus operating cycle starts, this module sends commencing signal to data conversion module, behind the write operation address and data that have obtained from data conversion module, local bus interface module completes this local bus write operation, enter the next local bus operating cycle, until that current storage is write all data processings of message is complete;
(2) realization of read procedure:
First, PCIE interface module is processed the PCIE literary composition of reading the newspaper in read procedure, it is storer that CPU the sends literary composition of reading the newspaper, the storer sending for the CPU literary composition of reading the newspaper, the start address that PCIE interface module extraction CPU reads, the data length that CPU reads, requestor ID, request label, the data length that the start address that PCIE interface module is read CPU, CPU read is submitted to data conversion module and local bus interface module;
Then, data conversion module buffer memory in read procedure is read start address, data length from the CPU of PCIE interface module, data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus read operations, each local bus read operation cycle is when start, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides the address of this local bus read operation;
Next, local bus interface module is responsible for the generation that local bus is read sequential in read procedure, and local bus is read the realization of sequential and combined by counter, realizes principle with writing process; Each local bus read operation cycle, while starting, local bus interface module sent commencing signal to data conversion module, and behind the local bus read operation address having obtained from data conversion module, local bus interface module is initiated this local bus read operation; In each local bus read operation, local bus interface module is obtained local bus Data Concurrent and is given data conversion module, local bus data acquisition is complete enters the next local bus operating cycle, until that current PC IE reads all data acquisitions of message request is complete;
Finally, after each local bus read operation completes, data conversion module extracts local bus data buffer memory; After all local bus read operations complete, data conversion module offers PCIE interface module by data according to PCIE stone user side interface data layout; The storer sending for the CPU literary composition of reading the newspaper, PCIE interface module is replied message according to PCIE agreement echo back data, the requestor ID that PCIE interface module is extracted, request label generate for the frame head of data recovery message, and the read request data of obtaining from local bus generate for the payload of data recovery message.
Compared with prior art, advantage of the present invention is as follows:
(1) the PCIE stone that the present invention calls FPGA device manufacturer and provides is realized Physical layer and the data link layer of PCIE interface, only need be absorbed in the design of PCIE interface transport layer, the Physical layer of PCIE interface and data link layer realize with PCIE stone, can under the prerequisite of consumes least logical resource, obtain the highest reliability and performance.
(2) local bus interface data width of the present invention is defined as 32, compatible 8,16,32 read-writes flexibly, simultaneously consistent with the minimum data transmission unit of PCIE agreement and need not consider byte mask field, can effectively simplify the complexity that PCIE interface transport layer designs.
(3) local bus interface support of the present invention is converted to repeatedly continuous local bus operation to carrying the PCIE read-write message of a plurality of double-word datas, PCIE read-write message of maximum support is converted to 32 continuous local bus operations, can reduce the free time of local bus between the operating cycle, significantly improve the read-write efficiency of system.
(4) the present invention can configuration operation pattern, two parameters of operation width, realize the local bus sequential that can join flexibly.Operator scheme, operation width offer FPGA top layer logic as module pin of the present invention, FPGA top layer logic can be adjusted this two module pins in real time according to different local bus operation address, can realize different local bus sequential is provided when CPU accesses different local bus addresses in real time, because this function is that FPGA realizes automatically, its flexibility ratio is that traditional local bus does not possess.
(5) the invention provides the switching of PCIE interface and local bus interface, when enjoying PCIE interface advantage, the FPGA design that can compatiblely in the past develop for local bus interface.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of writing process in the embodiment of the present invention.
Fig. 2 is the process flow diagram of read procedure in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Shown in Figure 1, the embodiment of the present invention provides a kind of device of the CPU access local bus based on PCIE agreement, comprises PCIE interface module, data conversion module and local bus interface module, wherein:
PCIE interface module, for: realize PCIE underlying protocol, this device is worked from end equipment (EP) as a PCIE under PCIE system;
Data conversion module, for: realize the entrained data layout of PCIE read-write message and the conversion of local bus data layout;
Local bus interface module, for: simulate traditional local bus sequential, realize to the local register of FPGA or via the read and write access of the external chip of FPGA bridge joint.
PCIE interface module designs according to the three-decker of PCIE protocol definition, the PCIE stone that the Physical layer of PCIE interface and data link layer functions are carried by FPGA device completes, PCIE stone is realized the processing of configuration space, PCIE data link layer and Physical layer message of PCIE interface, the functions such as link training of PCIE link, realize the bottom passage of PCIE link, the transport layer logic of PCIE interface module need to be communicated by letter with the user side interface of PCIE stone, realizes the processing of PCIE read-write message.
PCIE interface module needs design discharge controlling mechanism.Data (being 32 double words in the embodiment of the present invention to the maximum) due to a plurality of double words of PCIE read-write message portability, need repeatedly local bus operation to complete, if receive again a new PCIE read-write message in the processing procedure of the PCIE read-write message that a CPU sends, the embodiment of the present invention cannot be processed it, in order to address this problem, the embodiment of the present invention utilizes the PCIE read-write message reception enable signal that the user side interface place of PCIE stone provides to design control submodule, it is not busy controlling submodule original state, when client layer receives a PCIE read-write message, control submodule and transfer busy condition to, when control submodule is busy condition, the user side interface of PCIE stone will be closed, the PCIE read-write packet buffer of this stylish reception is in PCIE stone, complete after the processing of a PCIE read-write message, control submodule and return to not busy state, reopen the user side interface of PCIE stone, in the situation that CPU sends PCIE read-write message continuously, above flow process loops, until all PCIE read-write messages are disposed in PCIE stone buffer memory.Because PCIE agreement has guaranteed when not having enough time to respond the request of main side from end by credit mechanism, flow control can be carried out according to the water level from end buffer memory in main side, and (from end buffer memory, arriving certain water level main side stops sending, until water level drops to safe numerical value), so there is not the possibility of overflowing in PCIE stone buffer memory.
Data conversion module is write with CPU and is read the data buffer storage that two data transfer directions need to arrange suitable capacity at CPU, reason is the data (embodiment of the present invention is 32 double words to the maximum) of a plurality of double words of PCIE read-write message portability, and PCIE interface rate is far above local bus speed.That the capacity of data buffer storage need to meet is simultaneously functional, the requirement of reliability and resource utilization.Owing to being designed with control submodule in PCIE interface module, the buffer memory capacity of data conversion module is all designed to the twice of PCIE read-write message maximum data capacity (32 double word), i.e. 256 bytes.The data-switching corresponding relation of the embodiment of the present invention is 32 bit data of the corresponding local bus operation of a double word of PCIE read-write message data.In PCIE read-write message, four bytes of a double word are that large end is arranged (big-endian), and four bytes of a double word of local bus are small end arrangement (little-endian), for aspects such as logical design in the past of compatibility and application layer software personnel operating habits, consider, these mapping relations realize in the drive software of this invention.The benefit designing is like this in downstream logic of the present invention or the data rule of seeing in CPU application layer is all that large end is arranged (big-endian).
Local bus interface module has been combined the timing of local bus sequential by counter, counter works clock is 125Mhz.Counter combination comprises double word counter and period counter, and wherein double word counter is the high-positioned counter of period counter.Double word counter shows that at which double-word data (which local bus operating cycle) of transmission PCIE message, period counter shows how many 125Mhz clock period of transmission needs of each double-word data.The length field of PCIE message has determined the maximum count value of double word counter.Double word counter reads and writes at the moment or the PCIE that reset, PCIE interface mould receives PCIE read-write message the moment zero clearing that message is finished dealing with, and period counter, also can zero clearing when meeting carry condition except above condition.Period counter each 125Mhz rising edge clock between each double-word data transmission period adds one, and after reaching carry condition, period counter zero clearing simultaneously double word counter adds one.
Local bus interface module realizes by operator scheme and two parameters of operation width the local bus sequential that can join flexibly.Operator scheme has general mode and from end reply pattern.When this block configuration is general mode, the carry condition of period counter is to equal to operate width parameter, be the length in local bus operating cycle corresponding to the assignment of operation width parameter, this module supports under general mode the local bus operating cycle adjustable by 6-240 125Mhz clock period.This block configuration is during from end reply pattern, now operates width parameter invalid, and the carry condition of this module period counter is to receive from reply or the stand-by period of end to surpass 240 125Mhz clock period.Operator scheme and operation width two parameter designing are module pin rather than preset parameter, and this just allows each local bus operating cycle can be in real time to these two parameter pin assignment.The meaning of doing is like this to make CPU without being concerned about the concrete sequential of access from device, and the mapping of address and specific time sequence relation is completed automatically by FPGA.By above flexible design, local bus interface of the present invention not only can normally be accessed all FPGA designs for traditional local bus exploitation in the past, local bus signal of the present invention is all the synchronizing signal in FPGA sheet simultaneously, more convenient than traditional local bus interface use, reliability is higher.
On the basis of said apparatus, the embodiment of the present invention also provides a kind of method of the CPU access local bus based on PCIE agreement, comprises the following steps:
CPU comprises two separate processes of write and read to the access method of local bus, is described below respectively:
(1) write the realization of process:
Shown in Figure 1, first, PCIE interface module is processed PCIE and is write message in writing process, and the storer that CPU sends is write message.The storer sending for CPU is write message, PCIE interface module need be extracted the data that CPU writes, the start address that CPU writes, three fields of length that CPU writes, the data that PCIE interface module is write CPU, start address, data length are submitted to data conversion module, and the start address of simultaneously CPU being write, length are submitted to local bus interface module.
Then, data conversion module buffer memory in writing process is write data, start address, data length from the CPU of PCIE interface module.Data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus write operations, when each local bus write cycles starts, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides data and the address of this local bus write operation.
Finally, local bus interface module is responsible for the generation that local bus is write sequential in writing process, when each local bus operating cycle starts, this module sends commencing signal to data conversion module, behind the write operation address and data that have obtained from data conversion module, local bus interface module completes this local bus write operation and enters the next local bus operating cycle, until that current storage is write all data processings of message is complete.
(2) realization of read procedure:
Shown in Figure 2, first, PCIE interface module is processed the PCIE literary composition of reading the newspaper in read procedure, the storer that CPU the sends literary composition of reading the newspaper.The storer sending for the CPU literary composition of reading the newspaper, PCIE interface module is extracted the start address that CPU reads, data length, requestor ID, the request label that CPU reads.The data length that the start address that PCIE interface module is read CPU, CPU read is submitted to data conversion module and local bus interface module.
Then, data conversion module buffer memory in read procedure is read start address, data length from the CPU of PCIE interface module, data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus read operations, each local bus read operation cycle is when start, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides the address of this local bus read operation.
Next, local bus interface module is responsible for the generation that local bus is read sequential in read procedure, and local bus is read the realization of sequential and combined by counter, realizes principle with writing process; Each local bus read operation cycle, while starting, local bus interface module sent commencing signal to data conversion module, and behind the local bus read operation address having obtained from data conversion module, local bus interface module is initiated this local bus read operation; In each local bus read operation, local bus interface module is obtained local bus Data Concurrent and is given data conversion module, local bus data acquisition is complete enters the next local bus operating cycle, until that current PC IE reads all data acquisitions of message request is complete.
Finally, after each local bus read operation completes, data conversion module extracts local bus data buffer memory; After all local bus read operations complete, data conversion module offers PCIE interface module by data according to PCIE stone user side interface data layout; The storer sending for the CPU literary composition of reading the newspaper, PCIE interface module need to be replied message according to PCIE agreement echo back data.The requestor ID that PCIE interface module is extracted, request label generate for the frame head of data recovery message, and the read request data of obtaining from local bus generate for the payload of data recovery message.
The embodiment of the present invention is applied on the IPRAN of Fiberhome telecommunication equipment, and under the prerequisite without the modification local bus interface that ripe FPGA designed in the past, the mode that has successfully realized CPU access FPGA upgrades to PCIE interface by traditional local bus interface.
Those skilled in the art can carry out various modifications and variations to the embodiment of the present invention, if these revise and modification within the scope of the claims in the present invention and equivalent technologies thereof, these modifications and modification are also within protection scope of the present invention.
The prior art that the content of not describing in detail in instructions is known to the skilled person.
Claims (7)
1. the CPU based on PCIE agreement accesses a device for local bus, it is characterized in that: comprise PCIE interface module, data conversion module and local bus interface module, wherein:
Described PCIE interface module, for: realize PCIE underlying protocol, make this device under PCIE system as a PCIE from the work of end equipment;
Described data conversion module, for: realize the entrained data layout of PCIE read-write message and the conversion of local bus data layout;
Described local bus interface module, for: simulate traditional local bus sequential, realize to the local register of FPGA or via the read and write access of the external chip of FPGA bridge joint.
2. the CPU based on PCIE agreement as claimed in claim 1 accesses the device of local bus, it is characterized in that: described PCIE interface module designs according to the three-decker of PCIE protocol definition, the PCIE stone that the Physical layer of PCIE interface and data link layer functions are carried by FPGA device completes, PCIE stone is realized the configuration space of PCIE interface, the processing of PCIE data link layer and Physical layer message, the link training function of PCIE link, realize the bottom passage of PCIE link, the transport layer logic of PCIE interface module is communicated by letter with the user side interface of PCIE stone, realize the processing of PCIE read-write message.
3. the CPU based on PCIE agreement as claimed in claim 2 accesses the device of local bus, it is characterized in that: described PCIE Design of Interface Module flow control mechanism: utilize PCIE read-write message that the user side interface place of PCIE stone provides to receive enable signal and be designed with control submodule, it is not busy controlling submodule original state, when client layer receives a PCIE read-write message, control submodule and transfer busy condition to, when control submodule is busy condition, to close the user side interface of PCIE stone, the PCIE read-write packet buffer of this stylish reception is in PCIE stone; Complete after the processing of a PCIE read-write message, control submodule and return to not busy state, reopen the user side interface of PCIE stone; In the situation that CPU sends PCIE read-write message continuously, above flow process loops, until all PCIE read-write messages are disposed in PCIE stone buffer memory.
4. the CPU based on PCIE agreement as claimed in claim 3 accesses the device of local bus, it is characterized in that: described data conversion module is write with CPU and read the data buffer storage that two data transfer directions arrange suitable capacity at CPU, the buffer memory capacity of data conversion module is all designed to the twice of PCIE read-write message maximum data capacity 32 double words, i.e. 256 bytes, data-switching corresponding relation is 32 bit data of the corresponding local bus operation of a double word of PCIE read-write message data; In PCIE read-write message, four bytes of a double word are that large end is arranged.
5. the CPU based on PCIE agreement as claimed in claim 4 accesses the device of local bus, it is characterized in that: described local bus interface module has been combined the timing of local bus sequential by counter, counter works clock is 125Mhz, counter combination comprises double word counter and period counter, wherein double word counter is the high-positioned counter of period counter, double word counter shows which double-word data at transmission PCIE message, it is which local bus operating cycle, period counter shows how many 125Mhz clock period of transmission needs of each double-word data, the length field of PCIE message has determined the maximum count value of double word counter, double word counter reads and writes at the moment or the PCIE that reset, PCIE interface mould receives PCIE read-write message the moment zero clearing that message is finished dealing with, period counter is except above condition, also zero clearing when meeting carry condition, period counter each 125Mhz rising edge clock between each double-word data transmission period adds one, and after reaching carry condition, period counter zero clearing simultaneously double word counter adds one.
6. the CPU based on PCIE agreement as claimed in claim 5 accesses the device of local bus, it is characterized in that: described local bus interface module realizes by operator scheme and two parameters of operation width the local bus sequential that can join flexibly, operator scheme has general mode and from end reply pattern, when this block configuration is general mode, the carry condition of period counter is to equal to operate width parameter, be that the length in local bus operating cycle is corresponding to the assignment of operation width parameter, under this module support general mode, the local bus operating cycle is adjustable by 6-240 125Mhz clock period, this block configuration is during from end reply pattern, now operates width parameter invalid, and the carry condition of this module period counter is to receive from reply or the stand-by period of end to surpass 240 125Mhz clock period.
7. the method for the CPU access local bus based on PCIE agreement based on installing described in any one in claim 1 to 6, is characterized in that, comprises the following steps:
CPU comprises two separate processes of write and read to the access method of local bus, is described below respectively:
(1) write the realization of process:
First, PCIE interface module is processed PCIE and is write message in writing process, be that the storer that CPU sends is write message, the storer sending for CPU is write message, the data that PCIE interface module extraction CPU writes, the start address that CPU writes, three fields of length that CPU writes, the data that PCIE interface module is write CPU, start address, data length are submitted to data conversion module, and the start address of simultaneously CPU being write, length are submitted to local bus interface module;
Then, data conversion module buffer memory in writing process is write data, start address, data length from the CPU of PCIE interface module, data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus write operations, when each local bus write cycles starts, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides data and the address of this local bus write operation;
Finally, local bus interface module is responsible for the generation that local bus is write sequential in writing process, when each local bus operating cycle starts, this module sends commencing signal to data conversion module, behind the write operation address and data that have obtained from data conversion module, local bus interface module completes this local bus write operation, enter the next local bus operating cycle, until that current storage is write all data processings of message is complete;
(2) realization of read procedure:
First, PCIE interface module is processed the PCIE literary composition of reading the newspaper in read procedure, it is storer that CPU the sends literary composition of reading the newspaper, the storer sending for the CPU literary composition of reading the newspaper, the start address that PCIE interface module extraction CPU reads, the data length that CPU reads, requestor ID, request label, the data length that the start address that PCIE interface module is read CPU, CPU read is submitted to data conversion module and local bus interface module;
Then, data conversion module buffer memory in read procedure is read start address, data length from the CPU of PCIE interface module, data conversion module knows that according to data length local bus interface module needs to produce continuously how many local bus read operations, each local bus read operation cycle is when start, local bus interface module sends commencing signal to data conversion module, then by data conversion module, to it, provides the address of this local bus read operation;
Next, local bus interface module is responsible for the generation that local bus is read sequential in read procedure, and local bus is read the realization of sequential and combined by counter, realizes principle with writing process; Each local bus read operation cycle, while starting, local bus interface module sent commencing signal to data conversion module, and behind the local bus read operation address having obtained from data conversion module, local bus interface module is initiated this local bus read operation; In each local bus read operation, local bus interface module is obtained local bus Data Concurrent and is given data conversion module, local bus data acquisition is complete enters the next local bus operating cycle, until that current PC IE reads all data acquisitions of message request is complete;
Finally, after each local bus read operation completes, data conversion module extracts local bus data buffer memory; After all local bus read operations complete, data conversion module offers PCIE interface module by data according to PCIE stone user side interface data layout; The storer sending for the CPU literary composition of reading the newspaper, PCIE interface module is replied message according to PCIE agreement echo back data, the requestor ID that PCIE interface module is extracted, request label generate for the frame head of data recovery message, and the read request data of obtaining from local bus generate for the payload of data recovery message.
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