CN111078619A - Conversion device, network equipment and data transmission method - Google Patents
Conversion device, network equipment and data transmission method Download PDFInfo
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- CN111078619A CN111078619A CN201910251487.3A CN201910251487A CN111078619A CN 111078619 A CN111078619 A CN 111078619A CN 201910251487 A CN201910251487 A CN 201910251487A CN 111078619 A CN111078619 A CN 111078619A
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Abstract
The application provides a conversion device, network equipment and a data transmission method, wherein the conversion device comprises an interrupt processing unit, a read processing unit, a buffer area and a DMA controller; the interrupt processing unit is used for forbidding sending the interrupt to the main control board and outputting a control command to the read processing unit when receiving the interrupt sent by the interface board each time; the read processing unit is used for sending a read operation command to the interface board when receiving the control command every time so that the interface board returns data according to the read operation command; the buffer area is used for storing data returned by the interface board; and the DMA controller is used for acquiring the operation parameters, and transmitting the data in the buffer area to the main control board when the operation parameters meet the data uploading condition. Through the technical scheme of the application, the resources of the main control board can be saved, the bandwidth utilization rate is improved, and the occupancy rate of the main control board is reduced.
Description
Technical Field
The present application relates to the field of communications, and in particular, to a conversion apparatus, a network device, and a data transmission method.
Background
The network device (such as a router, a switch, a firewall, etc.) includes a main control board and an interface board, the main control board may include a PCI-E (Peripheral Component Interconnect Express) interface, and the interface board may also include a PCI-E interface, based on which the main control board may be connected with the interface board through a PCI-E bus, that is, both sides of the PCI-E bus are PCI-E interfaces.
In some application scenarios, the interface board does not have a PCI-E interface but has a low-speed interface (e.g., a local bus interface), and in order to enable the main control board to interact with the interface board, a conversion device is required to be disposed between the main control board and the interface board, the conversion device has a PCI-E interface and a low-speed interface, the main control board is connected with the conversion device through the PCI-E bus, and the interface board is connected with the conversion device through the low-speed bus (e.g., a local bus).
In the application scenario, in order to read data 1 to data 10 from the interface board, the main control board sends a read command to the conversion device, the conversion device reads data 1 from the interface board, and returns data 1 to the main control board. After the main control board acquires the data 1, a reading command is sent to the conversion device, the conversion device reads the data 2 from the interface board, the data 2 is returned to the main control board, and the like until the data 1-data 10 are successfully read.
The data reading operation needs to consume a long time, and in the time, the main control board is always occupied, and the main control board cannot process other tasks, namely other tasks can only wait, so that the resources of the main control board are wasted.
Disclosure of Invention
The application provides a conversion device, the conversion device is applied to network equipment, network equipment still includes main control board and interface board, conversion device through first type of interface with the main control board is connected, conversion device through second type of interface with the interface board is connected, wherein: the conversion device comprises an interrupt processing unit, a read processing unit, a buffer area and a Direct Memory Access (DMA) controller;
the interrupt processing unit is used for receiving the interrupt sent by the interface board; when receiving the interrupt sent by the interface board, forbidding sending the interrupt to the main control board and outputting a control command to the read processing unit;
the read processing unit is configured to send a read operation command to the interface board every time the control command is received, so that the interface board returns data according to the read operation command;
the buffer area is used for storing the data returned by the interface board;
and the DMA controller is used for acquiring operation parameters, and sending the data in the buffer area to the main control board when the operation parameters meet data uploading conditions.
The application provides a network device, which comprises a main control board, an interface board and a conversion device, and is characterized in that the conversion device is connected with the main control board through a first type of interface, and the conversion device is connected with the interface board through a second type of interface; wherein:
the interface board is used for sending an interrupt to the conversion device;
the conversion device is used for receiving the interrupt sent by the interface board; when receiving the interrupt sent by the interface board every time, forbidding sending the interrupt to the main control board, and sending a read operation command to the interface board so that the interface board returns data according to the read operation command; after receiving the data returned by the interface board, storing the data into a buffer area of the conversion device;
the conversion device is further configured to obtain an operation parameter, and when the operation parameter meets a data uploading condition, send the data in the buffer area to the main control board.
The application provides a data transmission method, apply to the network equipment, the said network equipment includes main control board, interface board and switching device, characterized by that, the said switching device is connected with main control board through the first interface, the said switching device is connected with interface board through the second interface, the said method includes:
the interface board sends an interrupt to the conversion device;
the conversion device receives the interrupt sent by the interface board; when receiving an interrupt sent by an interface board each time, forbidding sending the interrupt to the main control board, and sending a read operation command to the interface board;
the interface board sends data to the conversion device after receiving the read operation command;
after receiving the data returned by the interface board, the conversion device stores the data into a buffer area of the conversion device;
and the conversion device acquires the operation parameters, and when the operation parameters meet the data uploading condition, the data in the buffer area is sent to the main control board.
Based on the above technical solution, in the embodiment of the present application, after receiving an interrupt sent by an interface board, a conversion device does not send the interrupt to a main control board, but directly reads data from the interface board, so that a process of reading data from the interface board does not need to be initiated by the main control board, the conversion device stores the read data in a buffer, and after data reading is completed, the data in the buffer is sent to the main control board. Obviously, the above method can avoid the main control board from initiating a data reading process, reduce the time consumed by the data reading operation, avoid the main control board from being occupied by the data reading operation for a long time, save the resources of the main control board, improve the bandwidth utilization rate, improve the efficiency of the main control board for acquiring data, improve the overall performance of network equipment, and reduce the occupancy rate of the main control board.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present application or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings of the embodiments of the present application.
FIG. 1 is a diagram of a hardware configuration of a network device in one embodiment of the present application;
FIG. 2 is a hardware block diagram of a conversion device in an embodiment of the present application;
FIG. 3 is a diagram of a hardware configuration of a network device in one embodiment of the present application;
fig. 4 is a flowchart of a data transmission method according to an embodiment of the present application.
Detailed Description
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein is meant to encompass any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Depending on the context, moreover, the word "if" is used may be interpreted as "at … …," or "when … …," or "in response to a determination.
The embodiment of the present application provides a network device (such as a router, a switch, a firewall, a server, etc.), which may include a main control board, an interface board, and a conversion apparatus. Referring to fig. 1, a schematic diagram of the network device is shown, and the network device may include, but is not limited to: a main control board 10, a conversion device 20, an interface board 30 and an interface board 40. The main control board 10 can be connected to the interface board 40, the main control board 10 can also be connected to the conversion device 20, and the conversion device 20 can be connected to the interface board 30.
In an example, the conversion apparatus 20 and the main control board 10 may be disposed on the same single board, that is, one single board includes both the conversion apparatus 20 and the main control board 10. Alternatively, the conversion apparatus 20 may be disposed on a single board, that is, the conversion apparatus 20 and the main control board 10 are disposed on different boards. Of course, the above are just two examples, and the position of the switching device 20 is not limited. For example, the conversion apparatus 20 may also be disposed on the same board as the interface board 30, or for a network device including a main control board, a network board and an interface board, the conversion apparatus 20 may also be disposed on the same board as the network board, which is not limited to this.
Referring to fig. 1, the conversion apparatus 20 is disposed on a single board for illustration.
The main control board 10 includes a CPU (central processing Unit) implemented based on an SOC (System on Chip), and the CPU communicates with the interface board 30/interface board 40, that is, writes data into the interface board 30/interface board 40 and reads data from the interface board 30/interface board 40.
In one example, some interface boards (e.g., the interface board 40) have high-speed interfaces (e.g., a PCI-E interface, an SGMII (Serial Gigabit Media Independent) interface, etc., and the PCI-E interface is illustrated in fig. 1), and since the main control board 10 has the PCI-E interface, the main control board 10 and the interface board 40 are directly connected, that is, the main control board 10 and the interface board 40 may be connected by a high-speed bus (e.g., a PCI-E bus, an SGMII bus, etc., and the PCI-E bus is illustrated in fig. 1).
In another example, some interface boards (e.g., the interface board 30) may have a low-speed interface (e.g., a local bus interface, a TDM (Time Division Multiplexing) interface, etc., which is illustrated as the local bus interface in fig. 1), but do not have a PCI-E interface, and since the main control board 10 has the PCI-E interface but does not have the local bus interface, the main control board 10 may be connected to the interface board 30 through the conversion device 20, that is, the main control board 10 is not directly connected to the interface board 30.
Further, the conversion device 20 may have a PCI-E interface and a local bus interface, and therefore, the conversion device 20 may be connected to the main control board 10 through the PCI-E interface, that is, the conversion device 20 and the main control board 10 may be connected through a PCI-E bus. Further, the conversion device 20 may be connected to the interface board 30 through a local bus interface, that is, the conversion device 20 and the interface board 30 may be connected through a low-speed bus (such as a local bus, a TDM bus, etc., which is exemplified by the local bus in fig. 1).
In the application scenario, regarding the communication process between the main control board 10 and the interface board 40, the method may include: the main control board 10 writes data into the interface board 40 through the PCI-E bus, and the main control board 10 reads data from the interface board 40 through the PCI-E bus, and the data writing process and the data reading process are not repeated.
For the communication process between the main control board 10 and the interface board 30, the following steps may be included: the main control board 10 sends data to the conversion device 20 through the PCI-E bus, and the conversion device 20 writes data into the interface board 30 through the local bus, which is not described again. The main control board 10 sends a read command to the conversion device 20 through the PCI-E bus, and the conversion device 20 reads data from the interface board 30 through the local bus and returns the data to the main control board 10 through the PCI-E bus.
In a conventional method, in order to read data from the interface board 30, the main control board 10 sends a read command to the conversion device 20, the conversion device 20 reads data from the interface board 30 through the local bus, and since the data bit width of the local bus is 8 bits, the conversion device 20 only reads 8 bits of data from the interface board 30 and sends the data to the main control board 10. After receiving the 8-bit data, if all the data are not read, the main control board 10 continues to send a read command to the conversion device 20, and so on.
Assuming that the interface board 30 includes 80 bits of data, the main control board 10 needs to send 10 times of read commands, the conversion device 20 reads 10 times of data from the interface board 30, and the conversion device 20 sends 10 times of data to the main control board 10. Obviously, the data reading operation needs to take a long time, and in this time, the main control board 10 is always occupied, and cannot process other tasks, and other tasks can only wait, which wastes resources of the main control board 10.
In view of the above discovery, in the embodiment of the present application, after receiving the interrupt sent by the interface board 30, the conversion device 20 does not forward the interrupt to the main control board, but directly reads data from the interface board 30 through the local bus, and stores the read data in the buffer. The conversion apparatus 20 can read data from the interface board 30 for a plurality of times, and transmit the data in the buffer to the main control board until the data uploading condition is satisfied. For example, the interface board 30 includes 80 bits of data, the conversion apparatus 20 reads the data from the interface board 30 10 times, 8 bits at a time, so that a total of 80 bits of data are read and all the read data are stored in the buffer. After the data reading is completed, the conversion device 20 sends the data in the buffer area to the main control board.
In summary, it can be seen that in the process of reading data from the interface board 30, storing the data in the buffer area, and sending the data in the buffer area to the main control board 10 by the conversion device 20, the main control board 10 does not participate, that is, the time consumed by the data reading operation and the main control board 10 are not occupied, other tasks can be continuously processed, so that the resources of the main control board 10 are saved, the occupancy rate of the main control board 10 is reduced, and the overall performance of the network device is improved.
In order to implement the above functions, an embodiment of the present application provides a conversion apparatus, where the conversion apparatus may be applied to a network device, the network device may further include a main control board (e.g., a main control board having a first type interface) and an interface board (e.g., an interface board having a second type interface), the conversion apparatus may include the first type interface and the second type interface, the conversion apparatus is connected to the main control board through the first type interface, and the conversion apparatus is connected to the interface board through the second type interface. The first type of interface may be a high-speed interface (such as a PCI-E interface, an SGMII interface, etc., and the PCI-E interface is illustrated in fig. 1), and the second type of interface may be a low-speed interface (such as a local bus interface, a TDM interface, etc., and the local bus interface is illustrated in fig. 1).
Referring to fig. 2, a schematic diagram of a conversion device 20 is shown, the conversion device 20 may include, but is not limited to: an interrupt processing unit 21, a read processing unit 22, a buffer 23, and a DMA (Direct Memory Access) controller 24. The buffer 23 is a storage area inside the conversion apparatus 20, and may include, but is not limited to, a RAM (Random access memory) or the like.
In one example, the interrupt processing unit 21 is configured to receive an interrupt sent by the interface board 30; each time an interrupt sent by the interface board 30 is received, the interrupt is prohibited from being sent to the main control board 10, and a control command is output to the read processing unit 22. The read processing unit 22 is configured to send a read operation command to the interface board 30 each time the control command is received, so that the interface board 30 returns data according to the read operation command; a buffer area 23 for storing data returned by the interface board 30; and the DMA controller 24 is configured to obtain the operation parameter, and send the data in the buffer 23 to the main control board 10 when the operation parameter meets the data uploading condition.
Optionally, the DMA controller 24 obtains an operation parameter in each period, and determines whether a data uploading condition is satisfied according to the operation parameter. If so, all data in the buffer 23 is sent to the master control board 10. If not, the data in the buffer area 23 is not sent to the main control board 10, but the next period is waited, the operation parameters are continuously obtained, whether the data uploading conditions are met is judged according to the operation parameters, and the like.
Optionally, when determining that the operation parameter satisfies the data uploading condition, the DMA controller 24 is specifically configured to:
in case one, if the operation parameter is the data amount in the buffer 23, when the data amount in the buffer 23 reaches a preset threshold, it may be determined that the operation parameter satisfies the data uploading condition.
In case two, if the operation parameter is the interrupt interval time, when the interrupt processing unit 21 does not receive the interrupt sent by the interface board within the preset time, it may be determined that the operation parameter satisfies the data uploading condition.
If the operation parameter includes the data amount and the interrupt interval time in the buffer area 23, when the data amount in the buffer area 23 reaches a preset threshold value, determining that the operation parameter meets a data uploading condition; or, when the interrupt processing unit 21 does not receive the interrupt sent by the interface board within the preset time, it is determined that the operation parameter meets the data uploading condition.
Optionally, when the DMA controller 24 sends the data in the buffer 23 to the main control board 10, the following steps are specifically performed: all data in the buffer area 23 are stored in a memory corresponding to the main control board 10; after the data storage is completed, that is, after all the data in the buffer 23 is stored in the memory, a DMA completion interrupt is sent to the main control board 10, so that the main control board 10 obtains the data from the memory after receiving the DMA completion interrupt.
Further, the DMA controller 24 sends a DMA completion interrupt to the main control board 10, so that the main control board 10 is specifically configured to, after receiving the DMA completion interrupt, obtain data from the memory:
the DMA controller 24 sends a DMA completion interrupt to the main control board 10, and sends BD information and a data length corresponding to the data in the buffer 23 to the main control board 10, so that the main control board 10 obtains the data from the memory according to the BD information and the data length after receiving the DMA completion interrupt.
Based on the above technical solution, in the embodiment of the present application, after receiving an interrupt sent by an interface board, a conversion device does not send the interrupt to a main control board, but directly reads data from the interface board, so that a process of reading data from the interface board does not need to be initiated by the main control board, the conversion device stores the read data in a buffer, and after data reading is completed, the data in the buffer is sent to the main control board. Obviously, the above method can avoid the main control board from initiating a data reading process, reduce the time consumed by the data reading operation, avoid the main control board from being occupied by the data reading operation for a long time, save the resources of the main control board, improve the bandwidth utilization rate, improve the efficiency of the main control board for acquiring data, improve the overall performance of network equipment, and reduce the occupancy rate of the main control board.
The above scheme is described in detail below with reference to the application scenario shown in fig. 2. Referring to fig. 2, the conversion apparatus 20 may include: an interrupt processing unit 21, a read processing unit 22, a buffer 23, a DMA controller 24. The converting Device 20 may include, but is not limited to, a Logic chip, such as an FPGA (Field Programmable Gate Array), a CPLD (Complex Programmable Logic Device), an ASIC (Application Specific Integrated Circuit), and the like, and the type of the converting Device 20 is not limited in particular.
In one example, when the interface board 30 has data to be read (i.e., data that needs to be sent to the main control board 10), the interface board 30 sends an interrupt to the interrupt processing unit 21 of the conversion apparatus 20 through the interrupt channel.
The interrupt processing unit 21 does not forward the interrupt to the main control board 10 after receiving the interrupt, but the interrupt processing unit 21 itself responds to the interrupt, that is, the interrupt processing unit 21 prohibits sending the interrupt to the main control board 10 after receiving the interrupt, but determines that data needs to be read from the interface board 30 based on the interrupt. In order to read data from the interface board 30, the interrupt processing unit 21 may output a control command for instructing the read processing unit 22 to read data from the interface board 30 to the read processing unit 22.
The read processing unit 22, upon receiving the control command, may send a read operation command to the interface board 30 to cause the interface board 30 to return data, such as 8-bit data, to the buffer 23 of the conversion device 20 according to the read operation command. Specifically, the read processing unit 22 may send only one read operation command to the interface board 30, after receiving the read operation command, the interface board 30 may return data to the buffer 23 of the conversion device 20 through the local bus interface, and after receiving the data, the buffer 23 may store the data.
After the interface board 30 sends the data to the buffer area 23, if the interface board 30 still has the data to be read, the interface board 30 continues to send the interrupt to the interrupt processing unit 21. The interrupt processing unit 21 outputs a control command to the read processing unit 22 after receiving the interrupt, the read processing unit 22 sends a read operation command to the interface board 30 when receiving the control command, so that the interface board 30 returns data to the buffer area 23 according to the read operation command, and so on, until the interface board 30 does not have data to be read, the sending of the interrupt is stopped, the interrupt processing unit 21 does not output the control command to the read processing unit 22 after receiving no interrupt, and the read processing unit 22 does not send the read operation command to the interface board 30, so that the data is not read from the interface board.
In one example, the DMA controller 24 may obtain an operation parameter every statistical period (the interval of the statistical period may be configured empirically), and determine whether the data uploading condition is satisfied according to the operation parameter. If so, the DMA controller 24 may send all of the data in the buffer 23 to the master control board 10. If not, the DMA controller 24 does not send the data in the buffer 23 to the main control board 10 at present, but waits for the next cycle, continues to obtain the operation parameter, and determines whether the data uploading condition is satisfied according to the operation parameter, and so on.
The operation parameter may be the data amount in the buffer 23, or the interrupt interval time, and the operation parameter is not limited to the following manner.
Mode one, the operational parameter is the amount of data in the buffer 23. The DMA controller 24 acquires the amount of data in the buffer 23 every statistical period. If the data amount reaches a preset threshold (the preset threshold may be configured according to experience, for example, 95% of the maximum storage amount of the buffer 23, and the preset threshold is not limited), it indicates that a large amount of data has been stored in the buffer 23, and the data occupies the storage space of the buffer 23, so that the DMA controller 24 determines that the data uploading condition is satisfied, and sends all the data in the buffer 23 to the main control board 10. If the data amount does not reach the preset threshold, it indicates that the storage space in the buffer 23 is still unoccupied, so the DMA controller 24 determines that the data uploading condition is not satisfied, does not send the data in the buffer 23 to the main control board 10 at present, and waits for the next cycle to obtain the data amount in the buffer 23.
In the second mode, the operation parameter is an interrupt interval time, i.e. a difference between the current time and the time when the interrupt processing unit 21 has received the interrupt last time. The DMA controller 24 obtains the interrupt interval time of the interrupt processing unit 21 in each statistical period, and if it is determined that the interrupt processing unit 21 does not receive the interrupt within the preset time (the preset time may be configured according to experience without limitation), the DMA controller 24 determines that the data uploading condition is satisfied, and sends all the data in the buffer 23 to the main control board 10. If it is determined that the interrupt processing unit 21 has received the interrupt within the preset time according to the interrupt interval time, the DMA controller 24 determines that the data uploading condition is not satisfied, currently, the data in the buffer 23 is not sent to the main control board 10, and waits for the next cycle to obtain the interrupt interval time of the interrupt processing unit 21.
For example, when there is data to be read on the interface board 30, the interface board 30 sends an interrupt to the conversion device 20 every time length a (the time length a is an empirical value and there is an error), the preset time may be greater than or equal to the time length a, and then, taking the time length B as an example, the time length B is greater than the time length a.
Each time the interrupt processing unit 21 receives an interrupt, the DMA controller 24 may record the reception timing of the interrupt. For example, when the interrupt processing unit 21 receives an interrupt at time 1, the DMA controller 24 records the interrupt reception time as time 1; when the interrupt processing unit 21 receives an interrupt at time 2, the DMA controller 24 records the reception time of the interrupt as time 2, deletes the previously recorded time 1, and so on.
The DMA controller 24 determines the difference between the current time and the time of receipt of the most recent interrupt (e.g., time 2) at each statistical cycle. If the difference is greater than the time length B, it indicates that the interface board 30 has not sent an interrupt to the interrupt processing unit 21 within the time length B, and the interrupt processing unit 21 has not received an interrupt within the time length B, which may be because the interface board 30 does not have data to be read, that is, the read processing unit 22 of the logic device 20 has read all data from the interface board 30, and therefore, the DMA controller 24 determines that the data uploading condition is satisfied, and sends all data in the buffer 23 to the main control board 10.
If the difference is smaller than the time length B, it indicates that the interface board 30 sends an interrupt to the interrupt processing unit 21 within the time length B, and the interrupt processing unit 21 receives the interrupt within the time length B, that is, the interface board 30 still has data to be read. Therefore, the DMA controller 24 determines that the data upload condition is not satisfied.
Mode three, the operation parameters are the amount of data in the buffer 23 and the interrupt interval time.
The DMA controller 24 acquires the amount of data in the buffer 23 and the interrupt interval time every statistical period. If the data amount reaches the preset threshold, the DMA controller 24 determines that the data uploading condition is satisfied, and sends all the data in the buffer 23 to the main control board 10. Or, if it is determined that the interrupt processing unit 21 does not receive the interrupt within the preset time according to the interrupt interval time, the DMA controller 24 determines that the data uploading condition is satisfied, and sends all the data in the buffer 23 to the main control board 10.
In one example, when the data upload condition is satisfied, then the DMA controller 24 may send all the data in the buffer 23 to the master control board 10. Specifically, the DMA controller 24 stores all data in the buffer 23 in the memory corresponding to the main control board 10. For example, the DMA controller 24 directly transfers all data in the buffer 23 to the memory corresponding to the main control board 10 through a DMA write operation, the DMA write operation is implemented based on a DMA technology, and the DMA controller 24 does not need to participate in the main control board 10 when writing data into the memory, so that the operation of the main control board 10 is omitted, the interaction between the DMA controller 24 and the main control board 10 is not involved, and the DMA controller 24 only needs to transfer the data to the memory corresponding to the main control board 10.
In summary, the DMA controller 24 moves all the data in the buffer 23 to the memory corresponding to the main control board 10, and this operation does not require the main control board 10 to participate, which is not limited to this process.
After the data is stored, that is, after all the data in the Buffer 23 is stored in the memory, the DMA controller 24 may further send a DMA completion interrupt (such as a PCI-E in-band interrupt), BD (Buffer Descriptor) information, a data length, and other contents to the main control board 10, where the BD information may include, but is not limited to, a start address of the data in the Buffer 23 in the memory, and of course, the BD information may also include other contents, which is not limited thereto. The data length is the data length of the data in the buffer 23.
After receiving the DMA completion interrupt, the BD information, and the data length, the main control board 10 determines that data needs to be acquired from the memory based on the DMA completion interrupt. In order to obtain data from the memory, the main control board 10 determines a start address of the data in the memory by using the BD information, and then reads data matching the data length from the start address, so that the main control board 10 successfully obtains the data of the interface board 30.
Based on the above technical solution, in the embodiment of the present application, after receiving the interrupt sent by the interface board, the conversion device does not send the interrupt to the main control board, but directly reads data from the interface board, so that the process of reading data from the interface board does not need to be initiated by the main control board, the conversion device stores the read data into the buffer, and after the data reading is completed, the data in the buffer is sent to the main control board. Obviously, the above manner can avoid the main control board from initiating a data reading process, that is, the main control board does not need to participate in data acquisition, and the main control board only reads data from the memory after receiving the interrupt of the DMA completion, thereby releasing a large amount of resources of the main control board, avoiding the main control board from being occupied by data reading operation for a long time, saving resources of the main control board, improving the bandwidth utilization rate, improving the efficiency of the main control board for acquiring data, improving the overall performance of the network device, and reducing the occupancy rate of the main control board.
Referring to fig. 3, in an embodiment of the present application, a network device is further provided, where the network device may include a main control board, an interface board, and a conversion device, the conversion device may be connected to the main control board through a first type interface, and the conversion device may be connected to the interface board through a second type interface; wherein:
the interface board is used for sending an interrupt to the conversion device;
the conversion device is used for receiving the interrupt sent by the interface board; when receiving the interrupt sent by the interface board every time, forbidding sending the interrupt to the main control board, and sending a read operation command to the interface board so that the interface board returns data according to the read operation command; after receiving the data returned by the interface board, storing the data into a buffer area of the conversion device;
the conversion device is further configured to obtain an operation parameter, and when the operation parameter meets a data uploading condition, send the data in the buffer area to the main control board.
Optionally, in an example, if the operation parameter is a data amount, the conversion device is specifically configured to, when determining that the operation parameter satisfies a data uploading condition: and when the data volume in the buffer zone reaches a preset threshold value, determining that the operation parameters meet data uploading conditions.
Optionally, in an example, if the operation parameter is an interrupt interval time, the conversion device is specifically configured to: and when the conversion device does not receive the interrupt sent by the interface board within the preset time, determining that the operation parameters meet the data uploading condition.
Optionally, in an example, when the conversion device sends the data in the buffer to the main control board, the conversion device is specifically configured to: storing all data in the buffer area into a memory corresponding to the main control board; the conversion device is also used for sending DMA completion interrupt to the main control board after the data storage is completed;
and the main control board is used for receiving the DMA completion interrupt sent by the conversion device and acquiring data from the memory after receiving the DMA completion interrupt.
Optionally, in an example, the converting apparatus is further configured to send, after sending a DMA completion interrupt to a main control board, buffer descriptor BD information and a data length corresponding to data in the buffer to the main control board; the main control board is specifically configured to, when acquiring data from the memory: and receiving the BD information and the data length, and acquiring data from the memory according to the BD information and the data length.
Optionally, in an example, the conversion device and the main control board may be disposed on the same board; alternatively, the conversion apparatus may be disposed on a separate board.
For the functions of each component in the network device, reference may be made to the above embodiments, which are not described herein again.
Based on the same application concept as the network device and the conversion device, an embodiment of the present application further provides a data transmission method, which can be applied to a network device, where the network device includes a main control board, an interface board, and a conversion device, the conversion device is connected to the main control board through a first type of interface, and the conversion device is connected to the interface board through a second type of interface, as shown in fig. 4, the method may include:
in step 401, the interface board sends an interrupt to the conversion device.
In step 403, the interface board sends data to the conversion device after receiving the read operation command.
In step 404, after receiving the data returned by the interface board, the conversion device stores the data in a buffer of the conversion device.
Optionally, in an example, if the operation parameter is a data amount, the determining, by the conversion device, that the operation parameter satisfies a data uploading condition may include: and when the data volume in the buffer zone reaches a preset threshold value, determining that the operation parameters meet data uploading conditions.
Optionally, in an example, if the operation parameter is the interrupt interval time, the determining, by the conversion device, that the operation parameter satisfies the data uploading condition may include: and when the conversion device does not receive the interrupt sent by the interface board within the preset time, determining that the operation parameters meet the data uploading condition.
Optionally, in an example, the sending, by the conversion device, the data in the buffer to the main control board may include: storing all data in the buffer area into a memory corresponding to the main control board; and after the data storage is finished, sending a DMA finishing interrupt to the main control board, so that the main control board acquires data from the memory after receiving the DMA finishing interrupt.
Optionally, in an example, the sending, by the conversion device, a DMA completion interrupt to the main control board, so that the main control board obtains data from the memory after receiving the DMA completion interrupt, may include: and sending a DMA completion interrupt to the main control board, and sending Buffer Descriptor (BD) information and data length corresponding to the data in the buffer area to the main control board, so that the main control board obtains the data from the memory according to the BD information and the data length after receiving the DMA completion interrupt.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Furthermore, these computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A conversion apparatus, characterized in that, the conversion apparatus is applied to a network device, the network device further includes a main control board and an interface board, the conversion apparatus is connected with the main control board through a first type of interface, the conversion apparatus is connected with the interface board through a second type of interface, wherein: the conversion device comprises an interrupt processing unit, a read processing unit, a buffer area and a Direct Memory Access (DMA) controller;
the interrupt processing unit is used for receiving the interrupt sent by the interface board; when receiving the interrupt sent by the interface board, forbidding sending the interrupt to the main control board and outputting a control command to the read processing unit;
the read processing unit is configured to send a read operation command to the interface board every time the control command is received, so that the interface board returns data according to the read operation command;
the buffer area is used for storing the data returned by the interface board;
and the DMA controller is used for acquiring operation parameters, and sending the data in the buffer area to the main control board when the operation parameters meet data uploading conditions.
2. The conversion apparatus according to claim 1, wherein the operation parameter is a data amount; and when the DMA controller determines that the operating parameters meet the data uploading condition, the DMA controller is specifically configured to:
and when the data volume in the buffer zone reaches a preset threshold value, determining that the operation parameters meet data uploading conditions.
3. The conversion apparatus of claim 1, wherein the operational parameter is an interrupt interval time; and when the DMA controller determines that the operating parameters meet the data uploading condition, the DMA controller is specifically configured to:
and when the interrupt processing unit does not receive the interrupt sent by the interface board within the preset time, determining that the operation parameter meets the data uploading condition.
4. The conversion apparatus according to claim 1,
when the DMA controller sends the data in the buffer to the main control board, the DMA controller is specifically configured to:
storing all data in the buffer area into a memory corresponding to the main control board;
and after the data storage is finished, sending a DMA finishing interrupt to the main control board, so that the main control board acquires data from the memory after receiving the DMA finishing interrupt.
5. The conversion apparatus according to claim 4,
the DMA controller sends a DMA completion interrupt to the main control board, so that the main control board is specifically configured to, after receiving the DMA completion interrupt, obtain data from the memory:
and sending a DMA completion interrupt to the main control board, and sending Buffer Descriptor (BD) information and data length corresponding to the data in the buffer area to the main control board, so that the main control board obtains the data from the memory according to the BD information and the data length after receiving the DMA completion interrupt.
6. A network device is characterized in that the network device comprises a main control board, an interface board and a conversion device, wherein the conversion device is connected with the main control board through a first type of interface, and the conversion device is connected with the interface board through a second type of interface; wherein:
the interface board is used for sending an interrupt to the conversion device;
the conversion device is used for receiving the interrupt sent by the interface board; when receiving the interrupt sent by the interface board every time, forbidding sending the interrupt to the main control board, and sending a read operation command to the interface board so that the interface board returns data according to the read operation command; after receiving the data returned by the interface board, storing the data into a buffer area of the conversion device;
the conversion device is further configured to obtain an operation parameter, and when the operation parameter meets a data uploading condition, send the data in the buffer area to the main control board.
7. The network device of claim 6,
when the conversion device sends the data in the buffer area to the main control board, the conversion device is specifically configured to: storing all data in the buffer area into a memory corresponding to the main control board;
the conversion device is also used for sending DMA completion interrupt to the main control board after the data storage is completed;
and the main control board is used for receiving the DMA completion interrupt sent by the conversion device and acquiring data from the memory after receiving the DMA completion interrupt.
8. The network device of claim 7,
the conversion device is further configured to send, to the main control board, buffer descriptor BD information and data length corresponding to the data in the buffer after the DMA transmission to the main control board is completed;
the main control board is specifically configured to, when acquiring data from the memory: and receiving the BD information and the data length, and acquiring data from the memory according to the BD information and the data length.
9. The network device according to any of claims 6-8, wherein the conversion apparatus and the main control board are deployed on a same board; or, the conversion device is disposed on a separate single board.
10. A data transmission method is characterized in that the method is applied to network equipment, the network equipment comprises a main control board, an interface board and a conversion device, the conversion device is connected with the main control board through a first type of interface, the conversion device is connected with the interface board through a second type of interface, and the method comprises the following steps:
the interface board sends an interrupt to the conversion device;
the conversion device receives the interrupt sent by the interface board; when receiving an interrupt sent by an interface board each time, forbidding sending the interrupt to the main control board, and sending a read operation command to the interface board;
the interface board sends data to the conversion device after receiving the read operation command;
after receiving the data returned by the interface board, the conversion device stores the data into a buffer area of the conversion device;
and the conversion device acquires the operation parameters, and when the operation parameters meet the data uploading condition, the data in the buffer area is sent to the main control board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910251487.3A CN111078619A (en) | 2019-03-29 | 2019-03-29 | Conversion device, network equipment and data transmission method |
| PCT/CN2020/081745 WO2020200111A1 (en) | 2019-03-29 | 2020-03-27 | Network device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910251487.3A CN111078619A (en) | 2019-03-29 | 2019-03-29 | Conversion device, network equipment and data transmission method |
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| CN111078619A true CN111078619A (en) | 2020-04-28 |
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| WO2020200111A1 (en) | 2020-10-08 |
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