CN111143250A

CN111143250A - Method, device and medium for accessing FPGA storage unit based on AXI-ST interface

Info

Publication number: CN111143250A
Application number: CN201911327059.0A
Authority: CN
Inventors: 郭巍; 郝锐; 梅国强
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2020-05-12
Anticipated expiration: 2039-12-20
Also published as: CN111143250B

Abstract

The invention discloses a method, equipment and a storage medium for accessing an FPGA storage unit based on an AXI-ST interface, wherein the method comprises the following steps: opening a slave mode of an AXI-ST interface to receive a read-write operation frame sent by a CPU, analyzing the read-write operation frame and generating a control signal based on an analysis result; judging whether the control signal is a read request signal; reading data of the FPGA storage unit based on the AXI-MM interface in response to the control signal being a read request signal; and composing a read response frame of the AXI-ST interface based on the data, and opening a master mode of the AXI-ST interface to transmit the read response frame to the CPU. The method, the equipment and the medium for accessing the FPGA storage unit based on the AXI-ST interface, which are provided by the invention, can realize control without interface conversion by packaging the read-write instruction of the AXI-MM interface in the frame of the AXI-ST interface for transmission.

Description

Method, device and medium for accessing FPGA storage unit based on AXI-ST interface

Technical Field

The present invention relates to the field of interfaces, and in particular, to a method, an apparatus, and a readable medium for accessing an FPGA storage unit based on an AXI-ST interface.

Background

In the SOC (system on chip) design scenario of FPGA (Field Programmable Gate Array), embedded CPU and its peripheral devices commonly use the axi bus as the bus interface of the device or IP. We refer to the memory-mapped AXI bus as the AXI-MM bus and the streaming data-oriented AXI bus as the AXI-ST bus. The memory used in FPGA or the memory interface controlled by the memory generally adopts the AXI-MM interface form, but when the system is designed, only AXI-ST is selected as the main bus of the system due to the special requirement of the main peripheral or the purpose of simplifying the system bus design, and the problem of interface conversion is faced when the memory unit is accessed to the CPU system.

The commonly used solutions at present are: (1) AXI DMA (Direct Memory Access) mechanism: the CPU directly controls the DMA IP by using one DMA IP, mounts the memory of the interface in the memory mapping mode under the DMA, and converts the AXI-MM interface into the AXI-ST interface through DMA equipment for data transmission; (2) AXI DataMover mechanism: and using a DataMover IP to control the memory of the MM interface to use the AXI-ST interface to transmit data through the self-defined logic code in the logic chip. The first method requires CPU software programming, and the second method requires logic chip programming to implement the corresponding functions, which is not simple and effective in some cases. In an actual application scenario, a CPU is connected to an FPGA through a PCIe (peripheral component interconnect express) interface, an AXI-ST oriented interface is provided by PCIe IP for bus connection of devices in the FPGA, and then access to a storage unit in the FPGA requires using AXI-MM and AXI-ST conversion modules. However, in some cases, it is inconvenient to use the two conversion modules.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a method, a device, and a medium for accessing an FPGA storage unit based on an AXI-ST interface, which can greatly simplify an interface conversion operation process by encapsulating a read/write command and related data of an AXI-MM into an AXI-ST transmission data frame.

In view of the foregoing, an aspect of the embodiments of the present invention provides a method for accessing an FPGA memory cell based on an AXI-ST interface, including the following steps: opening a slave mode of an AXI-ST interface to receive a read-write operation frame sent by a CPU, analyzing the read-write operation frame and generating a control signal based on an analysis result; judging whether the control signal is a read request signal; reading data of an FPGA storage unit based on an AXI-MM interface in response to the control signal being a read request signal; and composing a read response frame for the AXI-ST interface based on the data and opening a master mode for the AXI-ST interface to send the read response frame to the CPU.

In some embodiments, further comprising: writing data in the read-write operation frame into the FPGA memory cells based on the AXI-MM interface in response to the control signal not being a read request signal.

In some embodiments, the parsing the read-write operation frame and generating a control signal based on the parsing result includes: analyzing the type of the read-write operation frame, and generating a corresponding request signal based on the type and the initial address of the read-write operation frame.

In some embodiments, said composing a read response frame for the AXI-ST interface based on the data comprises: converting the data into a format that the AXI-ST interface is capable of accommodating.

In some embodiments, further comprising: generating a read-write timing of the AXI-MM interface based on the read request signal and the write request signal.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: opening a slave mode of an AXI-ST interface to receive a read-write operation frame sent by a CPU, analyzing the read-write operation frame and generating a control signal based on an analysis result; judging whether the control signal is a read request signal; reading data of an FPGA storage unit based on an AXI-MM interface in response to the control signal being a read request signal; and composing a read response frame for the AXI-ST interface based on the data and opening a master mode for the AXI-ST interface to send the read response frame to the CPU.

In some embodiments, the steps further comprise: writing data in the read-write operation frame into the FPGA memory cells based on the AXI-MM interface in response to the control signal not being a read request signal.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: (1) by encapsulating the read-write command and related data of the AXI-MM into the transmission data frame of the AXI-ST, the interface conversion control process can be greatly simplified; (2) the definition of the read-write operation frame is simple, the protocol overhead is low, and the problem of read-write access of the storage unit based on Block operation is effectively solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for accessing FPGA memory cells based on an AXI-ST interface according to the present invention;

FIG. 2 is a schematic diagram of a read/write operation frame of the method for accessing an FPGA memory cell based on an AXI-ST interface according to the present invention;

fig. 3 is a schematic diagram of a hardware structure of an embodiment of the method for accessing an FPGA memory cell based on an AXI-ST interface according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above, a first aspect of the embodiments of the present invention proposes an embodiment of a method for accessing an FPGA memory cell based on an AXI-ST interface. Fig. 1 is a schematic diagram illustrating an embodiment of a method for accessing an FPGA memory cell based on an AXI-ST interface according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, starting the slave mode of the AXI-ST interface to receive the read-write operation frame sent by the CPU, analyzing the read-write operation frame and generating a control signal based on the analysis result;

s2, judging whether the control signal is a read request signal;

s3, responding to the control signal as a read request signal, and reading the data of the FPGA storage unit based on the AXI-MM interface; and

s4, composing a read response frame for the AXI-ST interface based on the data, and opening a master mode of the AXI-ST interface to transmit the read response frame to the CPU.

The embodiment of the invention mainly solves the conversion problem of the data interface and realizes the effective control of the conversion process. The operation of the CPU on the FPGA storage unit is divided into read operation and write operation, and the read-write based on Block is a mode for effectively using PCIe bandwidth, and the read-write operation can be realized on the storage unit based on Block. Of course, random reading and writing based on any address can be realized based on the implementation framework of the embodiment of the invention. And (3) writing: the CPU forms a write operation frame by the initial address and the data content of the data block needing to be written, receives the write operation frame through the AXI-ST interface, extracts the address and the data content, and uses the AXI-MM interface to continuously write in the memory unit. And (3) reading: the CPU forms the initial address and length information to be read into a read operation frame, receives the read operation frame through an AXI-ST interface, extracts the initial address, continuously reads the data of the memory unit by using the AXI-MM interface, forms a read response frame by the obtained data and sends the read response frame to the CPU. All control processes are contained in the read-write operation frame, and no additional control interface is needed.

And opening the slave mode of the AXI-ST interface to receive the read-write operation frame sent by the CPU, analyzing the read-write operation frame and generating a control signal based on the analysis result. In some embodiments, the parsing the read-write operation frame and generating a control signal based on the parsing result includes: judging whether length information is analyzed; generating a read request signal based on a start address in the operation frame in response to parsing out the length information; and in response to not parsing out the length information, generating a write request signal based on a start address in the operation frame. The interface function of the Slave mode of AXI-ST is realized, and the read-write operation frame sent by the CPU is received. And analyzing the read-write operation frame to generate a control signal and controlling the read-write operation caching module to complete corresponding functions. And the writing operation is used for controlling the data of the writing operation frame to be written into the cache module and generating a writing request signal. And reading operation, extracting read address information and generating a read request signal.

Judging whether the control signal is a read request signal; and reading the data of the FPGA memory unit based on the AXI-MM interface in response to the control signal being a read request signal. When receiving the read request signal, the data of the FPGA memory unit can be read based on the AXI-MM interface, and the data read out from the memory unit is buffered to form an AXI-ST read response frame. In some embodiments, said composing a read response frame for the AXI-ST interface based on the data comprises: converting the data into a format that the AXI-ST interface is capable of accommodating. In this way, by encapsulating the commands of the AXI-MM into the data frames of the AXI-ST, specific control can be achieved without replacing the interface.

In some embodiments, further comprising: writing data in the read-write operation frame into the FPGA memory cells based on the AXI-MM interface in response to the control signal not being a read request signal. When a write request signal is received, data in the read-write operation frame can be written into the FPGA memory unit based on the AXI-MM interface.

Fig. 2 is a schematic diagram of a read-write operation frame of the method for accessing an FPGA memory cell based on an AXI-ST interface according to the present invention. Length in the figure indicates Length, typically 16 bits. Type indicates the Type of frame, which is generally 4 bits, and 0x1 indicates that it is a write operation frame; 0x2 indicates a read frame; 0x3 indicates a read response frame. StartAddress denotes a start address, which is a start address of a read/write operation and is typically 32 bits. Data-0 to Data-n represent the Data contents of the write operation frame and the read response frame, and in the read operation frame, there is no Data field. Reserved represents a Reserved space, typically 12 bits.

It should be particularly noted that, the steps in the embodiments of the method for accessing an FPGA memory cell based on an AXI-ST interface may be mutually intersected, replaced, added, or deleted, and therefore, these reasonable permutation and combination transformations should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.

In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, starting the slave mode of the AXI-ST interface to receive the read-write operation frame sent by the CPU, analyzing the read-write operation frame and generating a control signal based on the analysis result; s2, judging whether the control signal is a read request signal; s3, responding to the control signal as a read request signal, and reading the data of the FPGA storage unit based on the AXI-MM interface; and S4, composing a read response frame of the AXI-ST interface based on the data, and opening a master mode of the AXI-ST interface to transmit the read response frame to the CPU.

In some embodiments, the parsing the read-write operation frame and generating a control signal based on the parsing result includes: judging whether length information is analyzed; generating a read request signal based on a start address in the operation frame in response to parsing out the length information; and in response to not parsing out the length information, generating a write request signal based on a start address in the operation frame.

Fig. 3 is a schematic diagram of a hardware structure of an embodiment of the method for accessing an FPGA memory unit based on an AXI-ST interface according to the present invention.

Taking the apparatus shown in fig. 3 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.

The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 3 illustrates the connection by a bus as an example.

The memory 302, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for accessing FPGA memory cells based on the AXI-ST interface in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., a method of implementing the above-described method embodiments for accessing FPGA memory cells based on the AXI-ST interface, by running the nonvolatile software program, instructions, and modules stored in the memory 302.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of a method of accessing the FPGA memory cell based on the AXI-ST interface, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.

Program instructions/modules corresponding to one or more methods of accessing FPGA memory cells based on an AXI-ST interface are stored in memory 302 and, when executed by processor 301, perform the methods of accessing FPGA memory cells based on an AXI-ST interface in any of the above-described method embodiments.

Any of the embodiments of the computer apparatus for performing the method for accessing an FPGA memory cell based on an AXI-ST interface described above may achieve the same or similar effects as any of the preceding method embodiments corresponding thereto.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, a program of the method for accessing an FPGA storage unit based on an AXI-ST interface can be stored in a computer-readable storage medium, and the program can include the processes of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for accessing an FPGA memory unit based on an AXI-ST interface is characterized by comprising the following steps:

opening a slave mode of an AXI-ST interface to receive a read-write operation frame sent by a CPU, analyzing the read-write operation frame and generating a control signal based on an analysis result;

judging whether the control signal is a read request signal;

reading data of an FPGA storage unit based on an AXI-MM interface in response to the control signal being a read request signal; and

composing a read response frame for the AXI-ST interface based on the data, and opening a master mode for the AXI-ST interface to send the read response frame to the CPU.

2. The method of claim 1, further comprising:

writing data in the read-write operation frame into the FPGA memory cells based on the AXI-MM interface in response to the control signal not being a read request signal.

3. The method of claim 1, wherein parsing the read/write operation frame and generating a control signal based on the parsing result comprises:

analyzing the type of the read-write operation frame, and generating a corresponding request signal based on the type and the initial address of the read-write operation frame.

4. The method of claim 3, wherein composing the read response frame for the AXI-ST interface based on the data comprises:

converting the data into a format that the AXI-ST interface is capable of accommodating.

5. The method of claim 1, further comprising:

generating a read-write timing of the AXI-MM interface based on the read request signal and the write request signal.

6. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:

judging whether the control signal is a read request signal;

7. The computer device of claim 6, wherein the steps further comprise:

8. The computer device of claim 6, wherein parsing the read-write operation frame and generating a control signal based on the parsing result comprises:

9. The computer device of claim 8, wherein composing the read response frame for the AXI-ST interface based on the data comprises:

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.