CN101140556A - Method and device for realizing accessing multiple I2C slave device by programmable device - Google Patents
Method and device for realizing accessing multiple I2C slave device by programmable device Download PDFInfo
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- CN101140556A CN101140556A CNA2007101453780A CN200710145378A CN101140556A CN 101140556 A CN101140556 A CN 101140556A CN A2007101453780 A CNA2007101453780 A CN A2007101453780A CN 200710145378 A CN200710145378 A CN 200710145378A CN 101140556 A CN101140556 A CN 101140556A
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Abstract
The invention discloses a method and a relevant facility to fulfill access on a plurality of I2C slave components with programmable components; wherein, the method comprises the following steps: (1) Select an I2C slave component to be accessed in a plurality of I2C slave components, and write circuit selection information for accessing the I2C slave component into a register group inside the programmable component; meanwhile, connect an I2C controller inside the programmable component with the I2C slave component in a corresponding circuit according to the information; (2) Write the data information, which is needed in accessing the I2C slave component, into the register group in the programmable component, and send a command to start access operation on the I2C slave component; (3) Follow the time sequence in I2C bus specifications to execute access operation on the I2C slave component according to the data information inside the register group. When a CPU accesses a plurality of I2C slave components, the method provided in the invention has advantages of simple and flexible operation, stable and reliable running, high efficiency, high speed and low single-board development cost.
Description
Technical field
The present invention relates to and a kind ofly utilize programming device to realize the method for a plurality of I2C from the device read-write operation also related to a kind of existing programming device that utilizes, realize the device of a plurality of I2C of visit from device at communication field.
Background technology
The I2C bus interface has signal wire characteristics few, easy and simple to handle, and in domain of communication equipment, the I2C bus interface obtains application more and more widely.In the application of standard, each I2C device has unique address of devices, and the I2C controller is realized carrying out read-write operation to what be connected to the I2C bus from device by distinguishing address of devices.But in the application of reality, can run into the situation that need conduct interviews to a plurality of I2C devices with identity unit address, all be " A0H " or " A2H " that is solidificated among the E2PROM such as the address of devices of little encapsulation optical module.
Solve this class problem, essence is will solve the realization of I2C controller and multipath I 2 C from the problem of the selection of device, in the prior art, has formed some and has realized the method for a plurality of I2C from the device read-write operation.Aspect the realization of I2C controller, a kind of is the I/O pin simulation I2C bus timing that utilizes CPU, realizes the I2C interface with the mode of complete software, and this mode takies many cpu resources, and is subjected to the stability influence of running software, inefficiency easily; Another kind method is to utilize the I2C controller on the IC chip to realize the read-write operation of a plurality of I2C from device, and this mode is stable, but can only use single board design cost height on the veneer that the special-purpose I2C of support interface ASIC stone is arranged.
From aspect the selection of device, a kind of method is from the serial data line of device switches set to be set at main I2C device and a plurality of I2C, need to select the I2C of operation from device by I2C from the serial data line of device at multipath I 2 C; Another kind method is from the serial time clock line of device switches set to be set at main I2C device and a plurality of I2C, need to select the I2C of operation from device by gating I2C from the serial time clock line of device.This dual mode all is to realize routing by a circuit of control I2C bus, another circuit then is connected from device with all I2C, if certain I2C that is connected on the I2C bus is damaged from device, the situation that this circuit is dragged down always can appear, cause other device can not use the I2C bus, so there is risk in these two kinds of I2C from the system of selection of device.
Summary of the invention
The technical problem to be solved in the present invention has provided a kind of with method and the device of a plurality of I2C of programming device realization visit from device, utilize the I2C controller and the multichannel of existing programming device realization hardware on the veneer to select network, realization is to the read-write operation of a plurality of I2C from device, improve access efficiency and the reliability of I2C, reduce cost of development from device.
In order to address the above problem, the invention provides and a kind ofly realize the method for a plurality of I2C of visit from device with programming device, may further comprise the steps:
(1) from device, chooses some I2C that will visit from device at a plurality of I2C, this I2C of registers group write-access in described programming device is from the route selection information of device, and, I2C controller in the programming device is communicated with from the corresponding line of device with this I2C according to this information;
(2) registers group in described programming device is written in data message required when visiting this I2C from device, and the concurrent order of losing one's life starts the accessing operation of I2C from device;
(3) according to the sequential of I2C bus specification,, carry out the accessing operation of this I2C from device according to the data message in the described registers group;
Further, method of the present invention, wherein, described registers group comprises: from the address of devices register, from device register address register, read data register, write data register, read operation control register, write operation control register, from device mask register, read operation status register and write operation status register;
Further, method of the present invention, wherein, in the described step (1), comprise: CPU choose prepare visit I2C from device, in programming device, write route selection information, and according to described route selection information from the device mask register from the device mask register, with serial data line, the serial time clock line of I2C controller in the programming device, be communicated with from serial data line, the serial time clock line of device with this I2C respectively; With serial data line, the serial time clock line of I2C controller in the programming device, disconnect from device serial data line, serial time clock line with the I2C that does not operate;
Further, method of the present invention, wherein, in the step (2), described data message comprises: I2C is from address of devices information, service data and control information;
Further, method of the present invention, wherein described in the step (2) to the accessing operation of I2C from device, comprise following two kinds of situations: I2C is carried out write operation and I2C is carried out read operation from device from device;
Further, method of the present invention wherein, is carried out write operation to I2C from device, may further comprise the steps:
(21a) write to operate from address of devices;
(22a) write to operate from the device register address;
(23a) writing will be to the data that write from the device register;
(24a) initiation starts the order of write operation;
Further, method of the present invention wherein, is carried out read operation to I2C from device, may further comprise the steps:
(21b) write to operate from address of devices;
(22b) write to operate from the device register address;
(23b) initiation starts the order of read operation;
Method of the present invention, wherein, in the described step (3), further comprise: after carrying out accessing operation, read read operation status register and write operation status register in the programming device, judge that this I2C is read states or writes state from the residing mode of operation of device, and, select this I2C is handled accordingly from device according to this mode of operation;
Further, method of the present invention wherein, if programming device is in the state of writing, is handled from device described I2C, and is further comprising the steps of:
(41a) through one section time-delay, wait for that I2C controller function I2C finishes from device in the programming device;
(42a) read the write operation status register;
(43a) judge whether write operation is finished, write operation is finished and is then entered step 44a); Otherwise, turn back to step 41a);
(44a) judge whether success of write operation, if operate successfully, end operation then; Otherwise, enter step 45a);
(45a) report the write operation alarm that makes mistakes;
Further, method of the present invention wherein, if programming device is in read states, is handled from device described I2C, and is further comprising the steps of:
(41b) through one section time-delay, wait for that I2C controller function I2C finishes from device in the programming device;
(42b) read the write operation status register;
(43b) judge whether read operation is finished,, then enter step 44b) if read operation is finished; Otherwise, turn back to step 41b);
(44b) judge that whether read operation is successful, if operate successfully, then enters step 45b); Otherwise, enter step 46b);
(45b) read I2C from the device register data;
(46b) report the read operation alarm that makes mistakes;
In order to address the above problem, the present invention also provides a kind of device of a plurality of I2C from device of realizing visiting, comprise: a CPU, a programming device and a plurality of I2C are from device, wherein, described CPU links to each other with bus mode with described programming device, the serial time clock line and the serial data line of described a plurality of I2C each I2C interface from device are connected with corresponding clock line and the data line that described programming device I/O pin is drawn respectively;
Described CPU, the I2C that is used to select to visit provides this I2C the data message from device from device to programming device, this I2C is initiated to carry out the order of reading and writing operation from device, and in described programming device, read the mode of operation of this I2C from device, handle accordingly;
Described programming device by described CPU control, is finished the visit from device to a plurality of I2C, comprising:
A registers group, be used to store CPU by this programming device visit I2C during from device employed this I2C from the relevant information of device;
An I2C controller is the Hardware I 2C controller of realizing in programming device, is used for the sequential according to the I2C bus specification, according to the indication of CPU, carries out the operation of I2C from device;
A route selection network, what the one side connected is I2C serial data line and the serial time clock line that described I2C controller is drawn, opposite side is connected to the I/O pin of described programming device, thereby some from device of described I2C controller and described a plurality of I2C is communicated with from device;
Further, device of the present invention, wherein, described I2C comprises from the data message of device: I2C is from address of devices information, service data and control information;
Further, device of the present invention, wherein, described I2C comprises from the relevant information of device: I2C is from address of devices information, data message, control information and status information;
Further, device of the present invention, wherein, described registers group comprises: from the address of devices register, from device register address register, read data register, write data register, read operation control register, write operation control register, from device mask register, read operation status register and write operation status register;
Further, device of the present invention, wherein, when described I2C when device is not in user mode, described route selection network, I2C serial data line and serial time clock line with the I2C controller extracts with certain two I/O pins disconnection of programming device, thereby make described I2C controller and described this I2C disconnect from device;
At one time, route selection network only is communicated with an I2C I2C controller from device, and I2C controller and other I2C are in off-state from device.
Compared with prior art, the method of the invention and device, existing programming device has been realized the I2C controller of hardware on the employing veneer, the I2C interface of I2C controller by route selection network and the I2C that will operate from device together with, CPU is as long as to programming device transmit operation data and initiation operational order, just can realize the operation from device to a plurality of I2C.Convenient, flexible, efficient is high, stable operation is reliable, reduced the veneer cost of development.
Description of drawings
The hardware connection layout of Fig. 1 for installing in the embodiment of the invention;
Fig. 2 is registers group and the electrical block diagram in the programming device in the embodiment of the invention;
Fig. 3 be in the embodiment of the invention any I2C of CPU write operation from the process flow diagram of device register;
Fig. 4 be in the embodiment of the invention any I2C of CPU read operation from the process flow diagram of device register.
Embodiment
The present invention is in order to solve the drawback that conventional solution exists, further set forth of the present invention a kind of with the method and the device of a plurality of I2C of programming device realization visit from device by following specific embodiment, below embodiment is described in detail, but not as a limitation of the invention.
As shown in Figure 1, the hardware connection layout for installing in the embodiment of the invention.This device is made up of from device CPU, programming device and a plurality of I2C, wherein CPU is connected with programming device by local bus, the serial time clock line and the serial data line of a plurality of I2C each I2C interface from device, be connected with corresponding clock line and the data line that described programming device I/O pin is drawn respectively, wherein a plurality of I2C that are connected with programming device from device only relate to comprise address of devices and device register address I2C from device, such as the SFP optical module.
As shown in Figure 2, be registers group in the programming device in the embodiment of the invention and electrical block diagram.
Described registers group comprises: from address of devices register Reg_Dev_Addr, from device register address register Reg_RW_Addr, read data register Reg_Rd_Data, write data register Reg_Wr_Data, read operation control register Reg_Rd_Contrl, write operation control register Reg_Wr_Contrl, read operation status register Reg_Rd_Status, write operation status register Reg_Wr_Status with from device mask register Reg_Slave_Select;
Wherein from the address of devices register, be used to store from device register address register the I2C that will visit from address of devices and I2C from the device register address; The write data register storage will be written to the data of I2C from the device register; The data that the read data register storage is read from the device register from I2C; Read operation control register storage CPU writes " 1 " expression and initiates read operation to the order of programming device transmission read operation, writes " 0 " expression and does not carry out read operation; Write operation control register storage CPU writes " 1 " expression and initiates write operation to the order of programming device transmission write operation, writes " 0 " expression and does not carry out write operation;
Read operation status register and write operation status register respectively comprise two state indicating bits, write by programming device and to represent progress and the result of I2C controller function I2C from device, the write operation status register comprises a Wr_Busy and two write operation states of position Wr_Error indicating bit, Wr_Busy is carrying out for " 1 " expression write operation, Wr_Busy finishes for " 0 " expression write operation, Wr_Error makes mistakes for " 1 " expression write operation, and Wr_Error is the success of " 0 " expression write operation; The read operation status register comprises a Rd_Busy and two read operation states of position Rd_Error indicating bit, Rd_Busy is carrying out for " 1 " expression read operation, Rd_Busy finishes for " 0 " expression read operation, Rd_Error makes mistakes for " 1 " expression read operation, and Rd_Error is " 0 " expression read operation success.
Equate from the device number of device with the I2C that will operate from the data width of device mask register, for the product that has N I2C from device, N bit data from the device mask register is corresponding one by one from device from each I2C of device with N I2C respectively, the 1st bit data Reg_Slave_Select[0 from the device mask register] corresponding with the 1st 12C from device, the 2nd bit data Reg_Slave_Select[1 from the device mask register] corresponding with the I2C from device, the rest may be inferred, the N-1 bit data Reg_Slave_Select[N-1 from the device mask register] corresponding with N I2C from device.A certain position from the device mask register writes " 0 ", represents that then CPU will be to the operating from device of correspondence, and a certain position from the device mask register writes " 1 ", then represent CPU inoperation correspondence from device.
I2C controller among the figure is realized by the hardware circuit in the programming device, carries out the desired read-write of CPU I2C from device operation according to the sequential of I2C bus specification.It is after programming device receives the write operation order that CPU sends out, read ready address of registers group and data message, ordered pair I2C carries out write operation from device during according to the write operation of I2C bus specification, after write operation is finished according to operational circumstances rewriting operation mode register data information more; It is after programming device receives the read operation order that CPU sends out, read the ready address information of registers group, ordered pair I2C carries out read operation from device during according to the read operation of I2C bus specification, after read operation is finished according to operational circumstances change read operation mode register data information;
Route selection network among the figure is according to from the Information Selection of each data bit of device mask register the I2C interface of I2C controller and each I2C being communicated with or disconnecting from the I2C interface of device.Each data from the device mask register are corresponding one by one from device from each I2C of device with a plurality of I2C respectively, each I2C is connected on two different I/O pins of programming device from device, if (0≤m≤N) bit data is " 0 " to the m from the device mask register, on the SDAm and two I/O pins of SCLm that route selection network then is connected to programming device with the SDA data line and the SCL clock line of I2C controller, be about to the I2C controller and be communicated with from device with m I2C; If the m bit data from the device mask register is " 1 ", route selection network then disconnects the SDA data line of I2C controller and SDAm and two I/O pins of SCLm of SCL clock line and programming device, is about to I2C controller and m I2C and disconnects from device.At one time, route selection network can only be communicated with an I2C I2C controller from device, and I2C controller and other I2C are in off-state from device.
Be example with certain disposable plates that contains 8 SFP optical modules below, illustrate that CPU will carry out the method for read-write operation to 8 SFP optical modules.The SFP optical module is to contain the I2C of I2C interface from device, the address of devices of each optical module is A0H or A2H, programming device is as main I2C device, and CPU can read the digital diagnostic information of SFP optical module by programming device, also can write data to some register of SFP optical module.CPU is connected with programming device with data bus by the address, and each the SFP optical module I2C interface in 8 SFP optical modules is connected with two different I/O pin of programming device.
As shown in Figure 3, may further comprise the steps from the process flow diagram of device register for any I2C of CPU write operation in the embodiment of the invention:
The SFP optical module that step 301, selection will be operated is promptly to writing data, to determine to visit the some SFP optical modules in 8 SFP optical modules from the device mask register;
If CPU will be to the operation of the 2nd SFP optical module, promptly from device mask register Reg_Slave_Select[7:0] write " 1111_1101 ";
Step 302 writes the address of devices of the SFP optical module that will operate, promptly writes A0H or A2H in Reg_Dev_Addr;
Step 303 writes the SFP optical module register address that will operate, promptly in Reg_RW_Addr, write to operate from the device register address;
Step 304 writes the data that will write in SFP optical module register, promptly write the data that will be written to SFP optical module register in Reg_Wr_Data;
Step 305 is initiated the order of startup write operation to programming device, promptly writes in the Reg_Wr_Contrl register " 1 ";
Step 306 is delayed time 30 SCL clock period, waits for that the I2C controller in the programming device is finished write operation according to the sequential of I2C bus specification;
Step 307 reads the write operation status register;
Step 308 judges whether write operation is finished, and judges promptly whether Wr_Busy is " 0 ", if be 0, then the expression operation is finished, and enters into step 309; Otherwise, turn back to step 306;
Step 309 judges whether write operation is successful, judges promptly whether Wr_Error is " 0 ", if be 0, then expression is operated successfully, does not make mistakes, and enters step 311; Otherwise, enter step 310.
Step 310 reports the write operation alarm that makes mistakes;
As shown in Figure 4, may further comprise the steps from the process flow diagram of device register for any I2C of CPU read operation in the embodiment of the invention:
The SFP optical module that step 401, selection will be operated is promptly to writing data, to determine to visit the some SFP optical modules in 8 SFP optical modules from the device mask register;
If CPU will be to the operation of the 2nd SFP optical module, promptly from device mask register Reg_Slave_Select[7:0] write " 1111_1101 ";
Step 402 writes the address of devices of the SFP optical module that will operate, promptly writes A0H or A2H in Reg_Dev_Addr;
Step 403 writes the SFP optical module register address that will operate, promptly writes the SFP optical module register address that will operate in Reg_RW_Addr;
Step 404 is initiated the order of startup write operation to programming device, promptly writes in the Reg_Rd_Contrl register " 1 ";
Step 405 is delayed time 50 SCL clock period, waits for that the I2C controller in the programming device is finished write operation according to the sequential of I2C bus specification;
Step 406 reads the read operation status register;
Step 407 judges whether write operation is finished, and judges promptly whether Rd_Busy is " 0 ", if be 0, represents that then write operation finishes, and enters into step 408; Otherwise, turn back to step 405;
Step 408 judges whether read operation is successful, judges promptly whether Rd_Error is " 0 ", if be 0, then represents the write operation success, enters step 409; Otherwise, enter step 410;
Step 409 reads the I2C that will the operate data from the device register, promptly reads the data among the read data register Reg_Rd_Data;
Step 410 reports the write operation alarm that makes mistakes;
Method provided by the invention when CPU visits a plurality of I2C from device, operate simple and easy flexibly, stable and reliable operation, the efficient height, speed is fast, the veneer cost of development is low.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (15)
1. realize the method for a plurality of I2C of visit with programming device for one kind, it is characterized in that, may further comprise the steps from device:
(1) from device, chooses some I2C that will visit from device at a plurality of I2C, this I2C of registers group write-access in described programming device is from the route selection information of device, and, I2C controller in the programming device is communicated with from the corresponding line of device with this I2C according to this information;
(2) registers group in described programming device is written in data message required when visiting this I2C from device, and the concurrent order of losing one's life starts the accessing operation of I2C from device;
(3) according to the sequential of I2C bus specification,, carry out the accessing operation of this I2C from device according to the data message in the described registers group.
2. the method for claim 1, it is characterized in that, described registers group comprises: from the address of devices register, from device register address register, read data register, write data register, read operation control register, write operation control register, from device mask register, read operation status register and write operation status register.
3. method as claimed in claim 2 is characterized in that, in the described step (1), comprising:
CPU chooses the I2C of preparation visit from device, in programming device, write route selection information from the device mask register, and according to described route selection information from the device mask register, with serial data line, the serial time clock line of I2C controller in the programming device, be communicated with from serial data line, the serial time clock line of device with this I2C respectively; With serial data line, the serial time clock line of I2C controller in the programming device, disconnect from device serial data line, serial time clock line with the I2C that does not operate.
4. the method for claim 1 is characterized in that, in the step (2), described data message comprises: I2C is from address of devices information, service data and control information.
5. the method for claim 1 is characterized in that, and is described to the accessing operation of I2C from device in the step (2), comprises following two kinds of situations:
I2C is carried out write operation and I2C is carried out read operation from device from device.
6. method as claimed in claim 5 is characterized in that, I2C is carried out write operation from device, may further comprise the steps:
(21a) write to operate from address of devices;
(22a) write to operate from the device register address;
(23a) writing will be to the data that write from the device register;
(24a) initiation starts the order of write operation.
7. method as claimed in claim 5 is characterized in that, I2C is carried out read operation from device, may further comprise the steps:
(21b) write to operate from address of devices;
(22b) write to operate from the device register address;
(23b) initiation starts the order of read operation.
8. method as claimed in claim 2, it is characterized in that, in the described step (3), further comprise: after carrying out accessing operation, read read operation status register and write operation status register in the programming device, judge that this I2C is read states or writes state from the residing mode of operation of device, and, select this I2C is handled accordingly from device according to this mode of operation.
9. method as claimed in claim 8 is characterized in that, if programming device is in the state of writing, described I2C is handled from device, and is further comprising the steps of:
(41a) through one section time-delay, wait for that I2C controller function I2C finishes from device in the programming device;
(42a) read the write operation status register;
(43a) judge whether write operation is finished, write operation is finished and is then entered step 44a); Otherwise, turn back to step 41a);
(44a) judge whether success of write operation, if operate successfully, end operation then; Otherwise, enter step 45a);
(45a) report the write operation alarm that makes mistakes.
10. method as claimed in claim 8 is characterized in that, if programming device is in read states, described I2C is handled from device, and is further comprising the steps of:
(41b) through one section time-delay, wait for that I2C controller function I2C finishes from device in the programming device;
(42b) read the write operation status register;
(43b) judge whether read operation is finished,, then enter step 44b) if read operation is finished; Otherwise, turn back to step 41b);
(44b) judge that whether read operation is successful, if operate successfully, then enters step 45b); Otherwise, enter step 46b);
(45b) read I2C from the device register data;
(46b) report the read operation alarm that makes mistakes.
11. realize visiting the device of a plurality of I2C for one kind from device, comprise: a CPU, a programming device and a plurality of I2C are from device, wherein, described CPU links to each other with bus mode with described programming device, it is characterized in that, the serial time clock line and the serial data line of described a plurality of I2C each I2C interface from device are connected with corresponding clock line and the data line that described programming device I/O pin is drawn respectively;
Described CPU, the I2C that is used to select to visit provides this I2C the data message from device from device to programming device, this I2C is initiated to carry out the order of reading and writing operation from device, and in described programming device, read the mode of operation of this I2C from device, handle accordingly;
Described programming device by described CPU control, is finished the visit from device to a plurality of I2C, comprising:
A registers group, be used to store CPU by this programming device visit I2C during from device employed this I2C from the relevant information of device;
An I2C controller is the Hardware I 2C controller of realizing in programming device, is used for the sequential according to the I2C bus specification, according to the indication of CPU, carries out the operation of I2C from device;
A route selection network, what the one side connected is I2C serial data line and the serial time clock line that described I2C controller is drawn, opposite side is connected to the I/O pin of described programming device, thereby some from device of described I2C controller and described a plurality of I2C is communicated with from device.
12. device as claimed in claim 11 is characterized in that, described I2C comprises from the data message of device: I2C is from address of devices information, service data and control information.
13. device as claimed in claim 11 is characterized in that, described I2C comprises from the relevant information of device: I2C is from address of devices information, data message, control information and status information.
14. device as claimed in claim 11, it is characterized in that, described registers group comprises: from the address of devices register, from device register address register, read data register, write data register, read operation control register, write operation control register, from device mask register, read operation status register and write operation status register.
15. device as claimed in claim 11, it is characterized in that, when described I2C when device is not in user mode, described route selection network, I2C serial data line and serial time clock line that the I2C controller is extracted, disconnect with certain two I/O pin of programming device, thereby described I2C controller and described this I2C are disconnected from device;
At one time, route selection network only is communicated with an I2C I2C controller from device, and I2C controller and other I2C are in off-state from device.
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| CNB2007101453780A CN100568211C (en) | 2007-09-11 | 2007-09-11 | Realize method and the device of a plurality of I2C of visit with programming device from device |
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| CNB2007101453780A CN100568211C (en) | 2007-09-11 | 2007-09-11 | Realize method and the device of a plurality of I2C of visit with programming device from device |
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| CN101763331A (en) * | 2010-01-18 | 2010-06-30 | 中兴通讯股份有限公司 | System and method for realizing I2C bus control |
| CN101604277B (en) * | 2008-06-11 | 2012-03-28 | 比亚迪股份有限公司 | I<2>C bus verification system and method |
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| CN102567133A (en) * | 2011-12-31 | 2012-07-11 | 广州视声电子科技有限公司 | Method for implementing communication by means of interruption I2C (inter to integrated circuit) devices and I2C system |
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Effective date of registration: 20151111 Address after: 430223 East Lake Wuhan New Technology Development Zone Hua Hua Road, Optics Valley Industrial Park, ZTE building, building No. 3, building Patentee after: WUHAN ZHONGXING SOFTWARE CO., LTD. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |