CN112817885A - Data access control method, programmable logic device and electronic equipment - Google Patents
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Abstract
The application discloses a data access control method, a programmable logic device and electronic equipment. The method is applied to a programmable logic device, wherein a plurality of storage devices are externally connected to the programmable logic device, and the method comprises the following steps: the time division multiplexing multi-channel control module sequentially transmits the device identification of the current storage device to be accessed to the I2C arbitration module according to the identification sequence, wherein the current storage device to be accessed is one of the plurality of storage devices; the I2C arbitration module is controlled to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification; and the time division multiplexing multi-channel control module controls the current storage equipment to be accessed and a random access storage unit in the programmable logic device to access data by using the I2C data channel.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a data access control method, a programmable logic device, and an electronic device.
Background
In the existing design system, when a Programmable logic device (FPGA) on a motherboard is connected to each storage device on a backplane, it needs to communicate with the FPGA through an I2C controller. When the system supports a plurality of storage devices, a plurality of I2C controllers are needed, the consumed FPGA logic resources are increased, and therefore FPGA models with richer resources and higher price have to be selected, and the design cost is increased.
Disclosure of Invention
The application discloses a data access control method, a programmable logic device and electronic equipment.
According to a first aspect of the present application, there is provided a data access control method, which is applied to a programmable logic device, the programmable logic device being externally connected with a plurality of storage devices, the method including: the time division multiplexing multi-channel control module sequentially transmits the device identification of the current storage device to be accessed to the I2C arbitration module according to the identification sequence, wherein the current storage device to be accessed is one of the plurality of storage devices; the I2C arbitration module is controlled to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification; and the time division multiplexing multi-channel control module controls the current storage equipment to be accessed and a random access storage unit in the programmable logic device to access data by using the I2C data channel.
According to an embodiment of the present application, the method further comprises: the time division multiplexing multichannel control module receives an interrupt request aiming at a first storage device, wherein the first storage device is one of the plurality of storage devices; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to an I2C arbitration module after controlling the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
According to an embodiment of the present application, the I2C arbitration module controlling to switch on an I2C data channel between an I2C control module and the current storage device to be accessed according to the device identifier comprises: the I2C arbitration module distributes the two-wire I2C signal generated by the I2C control module to the data link of the memory device currently to be accessed based on the device identification.
According to an embodiment of the present application, the data access between the current memory device to be accessed and the random access memory cell in the programmable logic device by using the turned-on I2C data channel includes: and utilizing the I2C data channel, and storing the control information or the state information of the current storage device to be accessed into a random access storage unit in the programmable logic device.
According to an embodiment of the present application, the data access between the current memory device to be accessed and the random access memory cell in the programmable logic device by using the turned-on I2C data channel includes: and acquiring control information from a random access memory unit in the programmable logic device by using the I2C data channel.
According to a second aspect of the present application, there is also provided a programmable logic device externally connected with a plurality of storage devices, the programmable logic device including: the time division multiplexing multi-channel control module is used for sequentially transmitting the device identification of the current storage device to be accessed to the I2C arbitration module according to the identification sequence, wherein the current storage device to be accessed is one of the plurality of storage devices; the I2C arbitration module is used for controlling to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification; the time division multiplexing multi-channel control module is further configured to control the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
According to an embodiment of the present application, the time division multiplexing multichannel control module is further configured to receive an interrupt request for a first storage device, where the first storage device is one of the plurality of storage devices; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to an I2C arbitration module after controlling the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
According to an embodiment of the present application, the I2C arbitration module is specifically configured to distribute the two-wire I2C signal generated by the I2C control module to the data link of the current storage device to be accessed based on the device identifier.
According to an embodiment of the present application, the time division multiplexing multi-channel control module is specifically configured to utilize the I2C data channel to control the current storage device to be accessed to store its own control information or state information in the random access storage unit in the programmable logic device.
According to an embodiment of the present application, the time division multiplexing multi-channel control module is specifically configured to utilize the I2C data channel to control the current storage device to be accessed to obtain control information from a random access memory unit in the programmable logic device.
According to a third aspect of the present application, there is provided an electronic device, including a motherboard and a backplane, where a programmable logic device on the motherboard is connected to a plurality of storage devices on the backplane; wherein, the programmable logic device is any one of the programmable logic devices.
In the data access control method, the programmable logic device and the electronic equipment of the embodiment of the application, in the time division multiplexing scheme, the time division multiplexing multichannel control module and the I2C control module are both single modules, and the logic of the modules is applied to all external storage equipment; furthermore, unified I2C bus data is distributed to the I2C bus of the corresponding storage device by the newly added I2C arbitration module based on the device identification of the storage device to turn on the I2C data channel between the I2C control module and the storage device of the corresponding device identification. Therefore, the time division multiplexing scheme realizes the unified integration of the multi-channel control module and the I2C control module, so that when the number of channels is greatly increased, the consumed logic resources are only slightly increased, and the resource consumption is reduced to a greater extent; when the programmable logic device is selected, an FPGA chip with less logic data and lower price can be selected, so that the related cost is effectively reduced.
It is to be understood that the teachings of this application need not achieve all of the above-described benefits, but rather that specific embodiments may achieve specific technical results, and that other embodiments of this application may achieve benefits not mentioned above.
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The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 shows a block control diagram of a related art time division multiplex design A;
FIG. 2 shows a block control diagram of a related art time division multiplexing design B;
FIG. 3 shows a block diagram of the time division multiplex design of the present application;
FIG. 4 is a schematic diagram illustrating a flow chart of an implementation of a data access control method according to an embodiment of the present application;
FIG. 5 is a flow chart illustrating an implementation of a data access control method according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a component structure of a programmable logic device according to an embodiment of the present application;
fig. 7 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The principles and spirit of the present application will be described with reference to a number of exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and to implement the present application, and do not limit the scope of the present application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The technical solution of the present application is further elaborated below with reference to the drawings and the specific embodiments.
FIG. 1 shows a block control diagram of a related art time division multiplex design A; FIG. 2 shows a block control diagram of a related art time division multiplexing design B; fig. 3 shows a block diagram of the time division multiplexing design of the present application.
In the existing time division multiplexing design system, when the FPGA on the motherboard is connected to each external storage device (such as NVME sub-device) on the backplane, it needs to communicate with it through an I2C controller. When the system supports a plurality of NVME sub-devices, a plurality of I2C controllers are needed, the consumed FPGA logic resources are increased, and therefore FPGA models with richer resources and higher prices have to be selected, and the design cost is increased.
Referring to fig. 1, a conventional time division multiplexing design a is provided with a separate control module and I2C controller for each NVME subset. The design concept is simple and direct, and all the sub-devices are independent from each other and have no coupling. But as the number of channels increases, the consumed FPGA resources increase linearly.
Further, referring to fig. 2, the improvement scheme B integrates the control modules of the channels to reduce resource consumption. But each sub-device still needs an independent I2C controller, and as the number of channels increases, the consumed FPGA resources also increase substantially linearly.
The present application is directed to solving the above-mentioned problems of the related art time division multiplexing design, and a new time division multiplexing design is creatively adopted. Referring to fig. 3, in the time-division multiplexing design of the present application, the time-division multiplexing multi-channel control module and the I2C control module (i.e. I2C controller) are both a single number of modules, and the logic thereof is applied to all external storage devices, such as NVME sub-device (1), NVME sub-device (2), …, and NVME sub-device (n), where n is a positive integer greater than or equal to 2; furthermore, unified I2C bus data is distributed to the I2C bus of the corresponding storage device by the newly added I2C arbitration module (i.e., I2C arbiter) based on the device Identification (ID) of the NVME subset to turn on the I2C data channel between the I2C control module and the NVME subset of the corresponding device identification; furthermore, the time division multiplexing multi-channel control module can control the NVME sub-equipment and the random access storage unit in the FPGA to perform data access by using the established I2C data channel.
Fig. 4 is a schematic flow chart illustrating an implementation of a data access control method according to an embodiment of the present application.
According to the time division multiplexing design scheme shown in fig. 3, an embodiment of the present application provides a data access control method, as shown in fig. 4, the method is applied to an FPGA externally connected with a plurality of storage devices, and the method includes: in operation 401, the time division multiplexing multi-channel control module sequentially transmits the device identifier of the current storage device to be accessed to the I2C arbitration module according to the identifier sequence, where the current storage device to be accessed is one of the plurality of storage devices; at operation 402, the I2C arbitration module controls to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification; operation 403, so.
In operation 401, the time division multiplexing multi-channel control module sorts the external storage devices in advance according to device Identifiers (IDs); then, the device ID of the current storage device to be accessed may be transmitted to the I2C arbitration module according to the identification sequence, so as to trigger the I2C arbitration module to establish the I2C data channel between the current storage device to be accessed and the I2C control module.
In operation 402, the I2C arbitration module accurately distributes the two-wire I2C signal generated by the I2C control module to the data link of the memory device currently being accessed based on the device ID transmitted by the time-division multiplexed multi-channel control module. In actual distribution, the I2C arbitration module requires reasonable tri-state control of the bidirectional data line SDA and control line SCL generated by the I2C control module.
In operation 403, after the I2C data channel between the current storage device to be accessed and the I2C control module is established, the time division multiplexing multi-channel control module may control the current storage device to be accessed and the random access memory unit in the FPGA to access data by using the I2C data channel.
In this embodiment of the present application, the time division multiplexing multi-channel control module may control the current storage device to be accessed and the random access memory unit in the FPGA to perform data access by using the I2C data channel, including: storing the self control information of the current storage equipment to be accessed or the state information acquired from the storage equipment into a random access storage unit;
in this embodiment of the present application, the time division multiplexing multi-channel control module may control the current storage device to be accessed and the random access memory unit in the FPGA to perform data access by using the I2C data channel, and further includes: the current storage device to be accessed acquires control information related to the current storage device from the random access storage unit.
In an application example, referring to the time division multiplexing design scheme shown in fig. 3, the time division multiplexing multichannel control module is a control core of the whole time division multiplexing system, and is required to support logic control of all NVME sub-devices. In practical design, the time division multiplexing multichannel control module can support 32 NVME sub-devices at most.
For each NVME kid device, a certain number of registers (typically 1-8 registers) need to be accessed. As the number of NVME sub-devices increases, the number of consumed logic cells also increases linearly. In order to save logic resources, the module further adopts a processing structure of replacing logic units with RAM.
FPGA chips provide a certain amount of RAM (random access memory cell) resources, taking the MAX10 series of 10M25 chips as an example, which provide 75M 9K (9bit x 1024) RAM resources. Thus, if each NVME kid device needs to access 8 bytes of registers, then 256 bytes of storage would be required for 32 kid devices, which can be achieved using 1M 9K. The control information of the NVME sub-equipment, the state information acquired from the NVME sub-equipment and the like are stored in RAM resources, and access to all registers can be realized only by matching with a small number of logic processing units.
Through operations 401 to 403 shown in fig. 4, the time division multiplexing multichannel control module sequentially obtains or stores relevant information from the RAM according to the IDs of the NVME sub-devices, and performs processing on the next NVME sub-device after processing one NVME sub-device and generating a corresponding command word. After all the 32 sub-devices complete processing, the process proceeds to the next cycle. The cycle duration depends on the number of NVME subdevices that need to be processed and the number of registers that each NVME subdevice needs to access. In a practical design, when 28 NVME sub-devices are processed, each NVME sub-device has an average access to 8 registers, and the I2C line rate is set to 100KHz, the duration of one cycle is about 34 ms. The time length can meet the real-time requirement of the system.
Therefore, the time division multiplexing scheme realizes the unified integration of the multi-channel control module and the I2C control module, so that when the number of channels is greatly increased, the consumed logic resources are only slightly increased, and the resource consumption is reduced to a greater extent; when the programmable logic device is selected, an FPGA chip with less logic data and lower price can be selected, so that the related cost is effectively reduced.
Fig. 5 is a schematic flow chart illustrating an implementation of a data access control method according to another embodiment of the present application.
According to the time division multiplexing design scheme shown in fig. 3, another embodiment of the present application further provides a data access control method, as shown in fig. 5, the method is applied to an FPGA externally connected with a plurality of storage devices, and the method includes: in operation 501, the time division multiplexing multi-channel control module sequentially transmits the device identifier of the current storage device to be accessed to the I2C arbitration module according to the identifier sequence, where the current storage device to be accessed is one of the plurality of storage devices; at operation 502, the I2C arbitration module controls to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification; in operation 503, the time division multiplexing multi-channel control module controls the current storage device to be accessed and a random access storage unit in the FPGA to access data by using the I2C data channel; at operation 504, the time division multiplexing multi-channel control module receives an interrupt request for the first storage device; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to the I2C arbitration module after controlling the current storage device to be accessed and the random access storage unit in the FPGA to perform data access by using the I2C data channel.
In operation 501, the time division multiplexing multi-channel control module sorts the external storage devices in advance according to device Identifiers (IDs); then, the device ID of the current storage device to be accessed may be transmitted to the I2C arbitration module according to the identification sequence, so as to trigger the I2C arbitration module to establish the I2C data channel between the current storage device to be accessed and the I2C control module.
In operation 502, the I2C arbitration module accurately distributes the two-wire I2C signal generated by the I2C control module to the data link of the memory device currently being accessed based on the device ID transmitted by the time-division multiplexed multi-channel control module. In actual distribution, the I2C arbitration module requires reasonable tri-state control of the bidirectional data line SDA and control line SCL generated by the I2C control module.
In operation 503, after the I2C data channel between the current storage device to be accessed and the I2C control module is established, the time division multiplexing multi-channel control module may control the current storage device to be accessed and the random access memory unit in the FPGA to perform data access by using the I2C data channel, for example, store the control information of the current storage device to be accessed or the state information obtained from the current storage device into the random access memory unit; or the current storage device to be accessed acquires the control information related to the current storage device from the random access storage unit.
It should be particularly noted that, for the requirement of high real-time performance in a specific environment, the time division multiplexing multi-channel control module according to the embodiment of the present application also introduces an interrupt request mechanism. That is, if a certain storage device applies for the interrupt request, the time division multiplexing multi-channel control module will immediately respond to the storage device corresponding to the interrupt request after completing the processing of the current storage device.
At operation 504, an interrupt request mechanism needs to be enabled when the first storage device needs to immediately perform data access, but it is not the storage device currently being accessed. Specifically, the time division multiplexing multichannel control module receives an interrupt request aiming at a first storage device, wherein the first storage device is one of the plurality of storage devices; in response to the interrupt request, after controlling and completing the data access between the current storage device to be accessed and the random access storage unit in the FPGA by using the I2C data channel, directly transmitting the device identifier of the first storage device to the I2C arbitration module, so as to establish the I2C data channel between the first storage device and the I2C control module, and implementing the data access between the first storage device and the random access storage unit in the FPGA by using the established I2C data channel. In practical application, the maximum response delay of the interrupt request mechanism is only 1.72ms, and the high real-time requirement under a specific environment is completely met.
Further, based on the data access control method described above, an embodiment of the present application further provides a programmable logic device, as shown in fig. 6, where the programmable logic device 60 is externally connected with a plurality of storage devices 61, and the programmable logic device 60 includes: the time division multiplexing multi-channel control module 601 is configured to sequentially transmit a device identifier of a current storage device to be accessed to the I2C arbitration module 602 according to an identifier sequence, where the current storage device to be accessed is one of the plurality of storage devices; the I2C arbitration module 602 is configured to control to switch on an I2C data channel between the I2C control module 603 and the current storage device to be accessed according to the device identifier; the time division multiplexing multi-channel control module 601 is further configured to control the current storage device to be accessed and the random access storage unit in the programmable logic device 60 to perform data access by using the I2C data channel.
According to an embodiment of the present application, the time division multiplexing multi-channel control module 601 is further configured to receive an interrupt request for a first storage device, where the first storage device is one of the plurality of storage devices; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to an I2C arbitration module after controlling the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
The I2C arbitration module 602, according to an embodiment of the present application, is specifically configured to distribute the two-wire I2C signal generated by the I2C control module 603 to the data link of the current memory device to be accessed based on the device identifier.
According to an embodiment of the present application, the time division multiplexing multi-channel control module 601 is specifically configured to utilize the I2C data channel to control the current storage device to be accessed to store its own control information or status information into the random access storage unit in the programmable logic device.
According to an embodiment of the present application, the time division multiplexing multi-channel control module 601 is specifically configured to utilize the I2C data channel to control the current storage device to be accessed to obtain control information from a random access memory unit in the programmable logic device.
Similarly, based on the programmable logic device as described above, an embodiment of the present application further provides an electronic device, as shown in fig. 7, where the electronic device 70 includes a motherboard 701 and a backplane 702, and a programmable logic device 7011 on the motherboard 701 is connected to a plurality of storage devices 7021 on the backplane; wherein the programmable logic device 7011 is any of the programmable logic devices 60 described above.
Here, the electronic device according to the embodiment of the present application may be any type of smart device, which is currently developed or to be developed in the future, and is equipped with a programmable logic device, or may be a robot device.
Here, it should be noted that: the above descriptions of the programmable logic device and the electronic device including the programmable logic device are similar to the descriptions of the method embodiments shown in fig. 3 to 5, and have similar beneficial effects to the method embodiments shown in fig. 3 to 5, and therefore are not repeated. For technical details that are not disclosed in the embodiments of the programmable logic device and the electronic device including the programmable logic device of the present application, please refer to the description of the method embodiments shown in fig. 3 to 5 in the present application for understanding, and therefore, for brevity, will not be described again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A data access control method is applied to a programmable logic device, wherein a plurality of storage devices are externally connected to the programmable logic device, and the method comprises the following steps:
the time division multiplexing multi-channel control module sequentially transmits the device identification of the current storage device to be accessed to the I2C arbitration module according to the identification sequence, wherein the current storage device to be accessed is one of the plurality of storage devices;
the I2C arbitration module is controlled to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification;
and the time division multiplexing multi-channel control module controls the current storage equipment to be accessed and a random access storage unit in the programmable logic device to access data by using the I2C data channel.
2. The method of claim 1, further comprising:
the time division multiplexing multichannel control module receives an interrupt request aiming at a first storage device, wherein the first storage device is one of the plurality of storage devices; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to an I2C arbitration module after controlling the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
3. The method as claimed in claim 1 or 2, wherein the I2C arbitration module controls to switch on an I2C data channel between an I2C control module and the current storage device to be accessed according to the device identification, comprising:
the I2C arbitration module distributes the two-wire I2C signal generated by the I2C control module to the data link of the memory device currently to be accessed based on the device identification.
4. The method as claimed in claim 1 or 2, wherein the current memory device to be accessed and the random access memory cell in the programmable logic device perform data access by using the switched on I2C data channel, and the method comprises:
and utilizing the I2C data channel, and storing the control information or the state information of the current storage device to be accessed into a random access storage unit in the programmable logic device.
5. The method as claimed in claim 1 or 2, wherein the current memory device to be accessed and the random access memory cell in the programmable logic device perform data access by using the switched on I2C data channel, and the method comprises:
and acquiring control information from a random access memory unit in the programmable logic device by using the I2C data channel.
6. A programmable logic device having a plurality of memory devices external to the programmable logic device, the programmable logic device comprising:
the time division multiplexing multi-channel control module is used for sequentially transmitting the device identification of the current storage device to be accessed to the I2C arbitration module according to the identification sequence, wherein the current storage device to be accessed is one of the plurality of storage devices;
the I2C arbitration module is used for controlling to switch on an I2C data channel between the I2C control module and the current storage device to be accessed according to the device identification;
the time division multiplexing multi-channel control module is further configured to control the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
7. The programmable logic device of claim 6,
the time division multiplexing multichannel control module is further configured to receive an interrupt request for a first storage device, where the first storage device is one of the plurality of storage devices; and responding to the interrupt request, and directly transmitting the device identification of the first storage device to an I2C arbitration module after controlling the current storage device to be accessed and a random access memory unit in the programmable logic device to perform data access by using the I2C data channel.
8. The programmable logic device of claim 6 or 7,
the I2C arbitration module is specifically configured to distribute the two-wire I2C signal generated by the I2C control module to the data link of the memory device currently to be accessed based on the device identification.
9. The programmable logic device of claim 6 or 7,
the time division multiplexing multi-channel control module is specifically configured to control, by using the I2C data channel, the current storage device to be accessed to store its own control information or state information in a random access storage unit in the programmable logic device.
10. An electronic device, comprising a motherboard and a backplane, wherein a programmable logic device on the motherboard is connected to a plurality of storage devices on the backplane; wherein the programmable logic device is a programmable logic device as claimed in any one of claims 6 to 9 above.
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