CN101398801A - Method and device for expanding internal integrate circuit bus - Google Patents
Method and device for expanding internal integrate circuit bus Download PDFInfo
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- CN101398801A CN101398801A CNA2008102245192A CN200810224519A CN101398801A CN 101398801 A CN101398801 A CN 101398801A CN A2008102245192 A CNA2008102245192 A CN A2008102245192A CN 200810224519 A CN200810224519 A CN 200810224519A CN 101398801 A CN101398801 A CN 101398801A
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- time clock
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Abstract
The invention relates to a method and a device used for extending internal integrated circuit bus; wherein, the method comprises the steps as follows: the serial clock wire of the internal integrated circuit I<2>C bus is extended as a plurality of serial clock wires by a strobe multiplexer; a plurality of serial clock wires are connected with all slave devices; the serial data wires of the I<2>C are directly connected with all slave devices; the device comprises a strobe multiplexer which is connected with a controller by a PIO wire and a serial clock wire of the I<2>C bus; the strobe multiplexer is connected with all slave devices by the extended serial clock wires; the controller is directly connected with all slave devices by the serial data wires of the I<2>C. the extension of I<2>C bus in a modularization design system is achieved by a simple logic device strobe multiplexer, usage of an expensive programmable I<2>C extension device is avoided, the extension cost of the I<2>C bus and the cost of the modularization design system are greatly reduced, and the method and the device are suitable for environments where the cost is strictly controlled.
Description
Technical field
The present invention relates to electronic system Application Design technical field, relate in particular to a kind of expanding internal integrate circuit (Inter-Integrated Circuit, I
2C) method of bus and device.
Background technology
Bus (Bus) refers to the mode by time-sharing multiplex, information is sent to one group of transmission line of one or more purpose parts from one or more source blocks.Mode according to the transmission data is divided, and can be divided into universal serial bus and parallel bus.In the universal serial bus, binary data sends to the purpose device by a data lines by turn; The data line of parallel bus is usually above 2.
I
2The C bus is a kind of simple two-way two-wire serial bus by Philips exploitation, is used for realizing the control between effective microelectronic device or the parts.Each is connected to I
2The unique address that the device of C bus all can be by hardware setting and the simple main frame of existence always/concern the software set address from device.Be connected to I
2In the device of C bus, the device that initialization transmission, clocking and termination send is a main frame; By the device of host addressing is from device.Because sending data to the device of bus is transmitter, the device that receives data from bus is a receiver, and therefore, main frame both can be used as the main frame transmitter and also can be used as the main frame receiver.
I
2The C bus comprises serial data line SDA and serial time clock line SCL.I
2The synoptic diagram of C bus transfer data as shown in Figure 1.Main frame has sent one from address of devices behind start bit or initial conditions S, this address has 7.Back to back the 8th is data direction position R/W, and it is write data that 0 expression sends, and 1 expression request is a read data.Be addressed receive this order from device after, reply to one in main frame and confirm response (ACK).If the current data transmission cycle is to send, then main frame is data the data bus of serving of unit serial with byte (8bit data) after receiving the confirmation ACK; If the current data transmission cycle is a request msg, after send confirming ACK, be data the bus of serving of unit serial with byte (8bit data) then from device; Receiver must provide and confirm ACK after receiving data; Transmitter is receiving that can continue to send next after ACK confirms organizes data.Data transmission is generally stopped by the position of rest P that main frame produces.
I
2The C bus is much used I in the application that the plate level connects
2The electronic system of C bus is all used modular design.As shown in Figure 2, this electronic system often is made up of a motherboard 21 and many daughter boards (or subcard) 24 that is provided with from device.Many subcard connector interfaces 26 are provided on the motherboard 21, and the subcard connector interface 26 of matching various subcards 24 insertion motherboards 21 has promptly constituted a complete electronic system.The connector interface 26 of each motherboard is often supported the subcard of different types.Therefore, when modular electronic systems started, whether motherboard 21 must scan each interface confirmed to have subcard to exist, and judges the particular type and the initialization subcard of subcard.Consider the electronic system storage chip that data are not lost after placing a power down on the subcard 24, i.e. I from cost and practical aspect
2C EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) (for example 24c02) 25.The subcard information of one group of agreement of EEPROM 25 stored.When system start-up, the system controller CPU 22 on the motherboard 21 passes through I
2 C bus 23 reads the appointed information in the EEPROM 25, according to the existence and the type of the information judgement subcard 24 that reads, then finishes corresponding initial work.
Give I according to Philips
2C EEPROM device addresses distributed section: 1,010 000～1,010 111, wherein preceding high four are fixed as 1010, and back three is user's configuration.Such I
2The C bus can connect 8 I at most
2C EEPROM device that is to say, can only articulate 8 subcards 24 on the motherboard 21 of modular electronic systems at most, causes the expansion of electronic system limited., an I
2C bus and connection thereof 8 are referred to as plate level I from device
2The C device.Plate level I
2The C device is arranged on the motherboard.
In the prior art,, adopt I in order to address this problem
2C multiplexer (multiplexer) or I
2The C extended device is to I
2The C bus is expanded.Wherein, multiplexer is realized I by the device that makes different input signal cables can be communicated to an output signal line
2The expansion of C bus.As application number is that the application of China of 200710145378.0 " realizes a plurality of I of visit with programming device
2C is from the method and the device of device ", use I
2C multiplexer PCA954X carries out I
2The expansion of C bus.As shown in Figure 3, Figure 4, PCA9548 expands to a data feedback channel (Upstream) SCL/SDA passage the I of a plurality of descending (Downstream)
2C (SCx/SDx, x=0,1,2...7) passage utilizes among the command selection down going channel SCx/SDx one directly to be communicated with data feedback channel, guarantees that simultaneously data feedback channel and other down going channels disconnect.PCA9548 has 8 down going channels, and each I
2The C down going channel can articulate 8 EEPROM devices, and therefore, PCA9548 can articulate 64 EEPROM devices simultaneously by down going channel SCx/SDx.Utilize I
2The C command selection, data feedback channel can be visited 64 EEPROM devices respectively, has expanded I greatly
2The C bus has guaranteed I
2The C bus is satisfied in modular electronic systems is used.
Though adopt I
2C multiplexer is to I
2The expansion of C bus can be satisfied the application requirements of modular system, but I
2C multiplexer costs an arm and a leg, and is not suitable for the environment to the cost control strictness.And this extended method all switches two signals of bus by extended chip, cause printed circuit board (PCB) (PCB) cabling more, takies the PCB area.
The patent No. is 200410009102.0 patent " a plurality of I of operation in communication facilities
2C is from the devices and methods therefor of device " adopt logical device to replace I
2C multiplexer expands I
2The C bus.Logical device comprises a clock register and a plurality of data register.The output terminal of clock register is connected to the clock line pin.Between the output terminal of each data register and the data line pin electronic switch is set all, its output terminal is connected to the data line pin, respectively with a plurality of I from device
2The serial data line correspondence of C interface, and control the closed and disconnected of this electronic switch by an input-output register.Each is from the I of device
2The serial time clock line of C interface all is connected with the same clock line pin of logical device; Each is from the I of device
2The serial data line of C interface all connects with the corresponding different data line pin of logical device.Controller is realized one or more I by the register of access logic device inside correspondence
2C is from the operation of device.
Adopt logical device expansion I
2The defective of C bus is: owing to the I from device
2The serial time clock line of C interface all is connected with the same clock line pin of logical device, and the pin of each device all has certain capacitive impedance (generally about 10pF), when from device (above 8) more for a long time, the capacity load of clock cable will increase to bigger value on the one hand, because capacitive load has the effect that stops the level saltus step, this will stop level to send quick saltus step, and when signal level from 0 to 1 saltus step, this hopping edge (rising edge) will become very slow; Device increases on the other hand, when the signal level saltus step, a plurality of can be from device simultaneously to skip signal generation multipath reflection, originally slowly the signal of rising retract lower level again.The effect of these two aspects causes producing back on the signal rising edge ditch 5, shown in Fig. 5 A, Fig. 5 B.This distorted signals (Distortion) might make the receiver data sampling make mistakes, this be since clock along on ditch is arranged back, it is two rising edge clocks that receiver may be judged by accident, and is rising edge sampled data at clock from the device sampled data, therefore from device meeting repeated sampling data, cause I
2The C garble causes unpredictable consequence.
Summary of the invention
The objective of the invention is to propose a kind of method and device of expanding internal integrate circuit bus, to reduce I
2The cost of C bus expansion.
For achieving the above object, the invention provides a kind of method of expanding internal integrate circuit bus, comprising:
By strobe multiplexer with internal integrated circuit I
2The serial time clock line of C bus expands to a plurality of serial time clock lines;
Described a plurality of serial time clock lines are connected to respectively from device;
With described I
2The serial data line of C bus directly respectively is connected from device with described.
The present invention also provides a kind of device of expanding internal integrate circuit bus, comprises strobe multiplexer, and described strobe multiplexer is by PIO line and I
2The serial time clock line of C bus is connected with controller; Described strobe multiplexer by the expansion serial time clock line with respectively be connected from device; Described controller is by described I
2The serial data line of C bus directly respectively is connected from device with described.
Such scheme is realized I by simple logic device strobe multiplexer
2Expensive programmable I has been avoided in the expansion of C bus in the modular design system
2The use of C extended device greatly reduces I
2The cost of C bus expansion cost and modular design system is suitable for the environment to the cost control strictness.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is I
2The synoptic diagram of C bus transfer data;
Fig. 2 is I
2The application synoptic diagram that the C bus connects in the plate level;
Fig. 3 is the PCA9548 theory diagram;
Fig. 4 is a PCA9548 application principle synoptic diagram;
Fig. 5 A is normal rising edge signal schematic representation;
Fig. 5 B is the rising edge signal schematic representation of distortion;
Fig. 6 is the process flow diagram of the method embodiment of expanding internal integrate circuit bus of the present invention;
Fig. 7 is the structural representation of the device embodiment one of expanding internal integrate circuit bus of the present invention;
Fig. 8 is the structural representation of the device embodiment two of expanding internal integrate circuit bus of the present invention;
Fig. 9 is the theory diagram of SN74CBTD3126 among the device embodiment two of expanding internal integrate circuit bus of the present invention;
Figure 10 is the connection diagram of SN74CBTD3126 among the device embodiment two of expanding internal integrate circuit bus of the present invention;
Figure 11 is the theory diagram of 74FST3251 among the device embodiment two of expanding internal integrate circuit bus of the present invention;
Figure 12 is the connection diagram of 74FST3251 among the device embodiment two of expanding internal integrate circuit bus of the present invention.
Embodiment
Fig. 6 is the process flow diagram of the method embodiment of expanding internal integrate circuit bus of the present invention, comprising:
Step 61, by strobe multiplexer with I
2The serial time clock line of C bus (SCL) expands to a plurality of serial time clock lines; A strobe multiplexer can be with an I
2The serial time clock line of C bus expands to a plurality of I
2The serial time clock line of C bus; As a plurality of I
2During the C bus, can use and I
2The strobe multiplexer of C bus equal number, corresponding one by one, expand each I
2The SCL of C bus.Strobe multiplexer can see the explanation among the device embodiment two for details by the gating of SCL before and after I/O able to programme (PIO) the interface signal control expansion of controller.
Step 62, described a plurality of serial time clock lines are connected to respectively from device; Wherein, respectively from device for being connected to I
2The device of C bus.
Step 63, with described I
2The serial data line of C bus directly respectively is connected from device with described, finishes I
2The expansion of C bus.
When being connected to I
2The device of C bus before the strobe multiplexer expansion, can be expanded by bus switch more for a long time, the I that expansion is obtained
2The C bus is expanded by strobe multiplexer again, another I that expansion is obtained
2C bus web joint level I
2The C device.So just realized I
2Further expanding of C bus.And the switching of bus switch makes the I that electronic system obtains in expansion of gating
2The C bus disconnects the I that another expansion obtains simultaneously
2The C bus has significantly reduced the number of devices that connects, the distorted signals problem of having avoided number of devices too much to bring, improved have more from the electronic system of device I
2The reliability of C bus work.The switching of bus switch can be controlled by the PIO signal of controller output, sees the explanation of device embodiment two for details.
Said method embodiment will be by using strobe multiplexer expansion I
2The C bus greatly reduces the expansion cost.
Fig. 7 is the structural representation of the device embodiment one of expanding internal integrate circuit bus of the present invention.Expansion I
2The device 78 of C bus comprises strobe multiplexer 76, and strobe multiplexer 76 is by PIO line 72 and I
2The serial time clock line 74 of C bus 73 is connected with controller 71; To strobe multiplexer 76 transmission PIO signals, control strobe multiplexer 76 is selected one to controller 71 from the serial time clock line 77 of expansion by PIO line 72, and the serial time clock line 74 preceding with expansion is communicated with.Strobe multiplexer 76 by the expansion serial time clock line 77 be that subcard 79 is connected respectively from device; Controller 71 passes through I
2The serial data line 75 of C bus 73 directly is connected with each subcard 79.Wherein, controller 71 is the computing machine of chip-scale, is integrated on a slice chip by CPU, RAM, ROM, timing number device and multiple I/O interface with computing machine to form, for doing various combination control in different application scenarios.PIO refers generally to the programmable I/O interface on the controller, can be used for the control or the condition monitoring of peripheral components.
Expansion I
2The device of C bus also can comprise bus switch, the I that controller is drawn
2The C bus is carried out first order expansion, the I that expansion is obtained
2The serial time clock line of C bus is expanded by strobe multiplexer, realizes I
2The second level expansion of C bus.
Fig. 8 is the structural representation of the device embodiment two of expanding internal integrate circuit bus of the present invention.Present embodiment expansion I
2The device of C bus is also to comprise bus switch 808 and plate level I with the difference of device embodiment one
2C device 810.808 couples of I of bus switch
2C bus 805 is carried out first order expansion, with I
2C bus 805 expands to an I
2C bus 806 and the 2nd I
2C bus 807; 809 couples the one I of strobe multiplexer
2C bus 806 is expanded, and extended mode is with device embodiment one.Plate level I
2C device 810 is existing plate level I
2C device, i.e. an I
2The C bus connects 8 and can be arranged on the same circuit board with controller 801 from device, in other words, and plate level I
2C device 810 is arranged on the motherboard of electronic system.Plate level I
2C device 810 has been realized I jointly with strobe multiplexer 809
2The expansion second time of C bus 805 has guaranteed expansion I
2The device of C bus still can satisfy electronic system to I under the more situation of subcard 811
2The demand of C bus.
In the present embodiment, bus switch 808 can be SN74CBTD3126, and strobe multiplexer 809 can be 74FST3251.As shown in Figure 9, when OEn (n=1,2,3,4, down with) be logic level " 1 ", and the OEn switch driven gets through, conducting links to each other data line nA with nB, the information of nA directly is transferred to nB.When using SN74CBTD3126 to carry out first order expansion, as shown in figure 10.Controller 801 connects SN74CBTD3126 by first group of PIO line 803.First group of PIO line 803 comprises two PIO line: PIO1 and PIO2.The PIO1 of use controller and PIO2 are I
2805 switchings of C bus are connected to I
2C bus 806 or I
2C bus 807.Wherein, the PIO1 of controller 801 is connected to OE1 and the OE2 of bus switch (Bus Switch) SN74CBTD3126, and the PIO2 of controller 801 is connected to OE3 and the OE4 of Bus Switch SN74CBTD3126.I
2The SCL0 of C bus 805 is connected to 1A and the 3A input end of SN74CBTD3126, and SDA0 is connected to 2A and the 4A input end of SN74CBTD3126, and output terminal 1B, the 2B of SN74CBTD3126,3B, 4B are connected respectively to an I
2The SCL1 of C bus 806, SDA1, the 2nd I
2The SCL2 of C bus 807, SDA2.
When the PIO1 of controller 801 is output as logic level " 1 ", when PIO2 is output as logic level " 0 ", promptly be input as logic level " 1 " as the OE1 of Bus Switch SN74CBTD3126 and OE2, OE3 and OE4 be input as logic level " 0 " time, the internal switch 1A-1B of SN74CBTD3126,2A-2B conducting.That is the I of slave controller 801 to Bus Switch SN74CBTD3126,
2C bus 805 (SCL0/SDA0) directly is communicated to an I
2C bus 806 (SCL1/SDA1), and the 2nd I
2C bus 807 (SCL2/SDA2) then is in disconnected state; When the PIO1 of controller 801 is output as logic level " 0 ", when PIO2 is output as logic level " 1 ", promptly be input as logic level " 0 " as the OE1 of Bus SwitchSN74CBTD3126 and OE2, OE3 and OE4 be input as logic level " 1 " time, the internal switch 3A-3B of Bus Switch SN74CBTD3126,4A-4B conducting, the i.e. I of slave controller 801 to Bus Switch SN74CBTD3126
2C bus 805 (SCL0/SDA0) directly is communicated to the 2nd I
2C bus 807 (SCL2/SDA2), and an I
2C bus 806 (SCL1/SDA1) then is in disconnected state.
In order to guarantee to expand the I that obtains
2The C bus is in steady state (SS) when not being communicated with, available pull-up resistor places stable logic level one state to SCL1/SDA1 and SCL2/SDA2, to avoid occurring non-steady state.
As shown in figure 11, gating final election device 74FST3251 by signal wire S0, S1, S2 control A end be communicated to Bn (n=0,1,2...7, down with) end.The A of the value control of signal wire S0, S1, S2 logic level is as shown in table 1 to the connected relation of Bn.
The conducting relation table of table 1 A and Bn
OE signal overall situation control signal A is to the conducting of signal Bn.When OE was logic level " 0 ", signal A was conducting to Bn according to the syntagmatic of the logic level values of S0, S1, S2; When OE is logic level " 1 ", signal wire A is not communicated with Bn.
When by 74FST3251 to I
2When C bus 805 is carried out second level expansion, as shown in figure 12.Second group of PIO line 804 of controller 801 is connected to S0, S1, the S2 of 74FST3251.Second group of PIO line 804 comprises three PIO line: PIO3, PIO4 and PIO5.PIO3 is connected to S0, and PIO4 is connected to S1, and PIO5 is connected to S2.The one I
2The SCL2 signal wire of C bus 806 is connected to the input end A of 74FST3251, and output terminal B1～B8 of 74FST3251 is connected respectively to the I after the expansion
2C bus 821～I
2SCL3～the SCL11 of C bus 828.In addition, the OE input pin of 74FST3251 is directly connected to logically, promptly OE be input as logic level " 0 ", guarantee that 74FST3251 all the time can operate as normal.
Signal PIO3, the PIO4 of controller 801 outputs, PIO5 are as input signal S0, S1, the S2 of 74FST3251, promptly, the combinational logic of PIO3, PIO4, PIO5 output is as the input combinational logic of S0, S1, S2, and the input A switching of control 74FST3251 is communicated to output terminal Bn, thus control I
2The SCL1 of C bus 805 is communicated to I
2C bus 821～I
2The SCL of C bus 828 (SCL3～SCL11).It is as shown in table 2 to be communicated with control relation.
Table 2 SCL1 and SCL3～SCL11 communication information
Similarly, the I in order to guarantee to expand to
2C bus 821～I2C bus 828 is in steady state (SS) when not being communicated with, available pull-up resistor places stable logic level one state to SCL3～SCL11, avoids occurring non-steady state.
Plate level I on controller 801 visit motherboards
2During C device 810, when the first order is expanded, by make PIO1 equal logic level " 1 ", PIO2 equals logic level " 0 ", I
2C bus 805 switches to the 2nd I
2C bus 807.I
2A C bus 805 and an I
2C bus 806 does not connect, and can rely on pull-up resistor to make an I
2C bus 806 is in the bus stationary state, that is, and and the 2nd I
2There is not information transmission on the C bus 806.
I on controller 801 visit subcards 811
2During the C device, by make PIO1 equal logic level " 0 ", PIO2 equals logic level " 1 ", I
2C bus 805 switches to an I
2C bus 806 is again by putting PIO3, PIO4, the logic level values of PIO5 for determining, an I
2The SCL of C bus 806 switches to the I in requisition for the subcard of visiting
2C SCL, switching controls is as shown in table 2.The I of like this, accessed subcard
2The C bus is by handover mechanism and I
2C bus 805 is communicated with, and realizes that bus is communicated with, thus controller 801 visit subcards.And not accessed I
2The SCL of C bus is in high level by pull-up resistor, promptly remains static.
When subcard is less, can remove first order expansion, directly adopt second level expansion.In Fig. 7, controller directly links to each other with strobe multiplexer.
When subcard is more, promptly need to connect from device more for a long time, by the first order expansion of bus switch, can be at gating I
2In the time of branch circuit of C bus expansion, disconnect I
2Another branch circuit of C bus 805 expansion, thus significantly reduced the quantity of the device that is electrically connected, thus reduced I
2The capacity load of C bus has been avoided the distorted signals problems such as time ditch to the prevention generation of skip signal, has guaranteed I
2The reliability of C bus work.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (6)
1, a kind of method of expanding internal integrate circuit bus is characterized in that, comprising:
By strobe multiplexer with internal integrated circuit I
2The serial time clock line of C bus expands to a plurality of serial time clock lines;
Described a plurality of serial time clock lines are connected to respectively from device;
With described I
2The serial data line of C bus directly respectively is connected from device with described.
2, the method for expanding internal integrate circuit bus according to claim 1 is characterized in that, described strobe multiplexer is switched described many serial time clock lines under input and output PIO signal controlling able to programme.
3, the method for expanding internal integrate circuit bus according to claim 1 is characterized in that, also comprises:
Described I
2The C bus obtains by the bus switch expansion.
4, the method for expanding internal integrate circuit bus according to claim 3 is characterized in that, described bus switch is the described I of gating under input and output PIO signal controlling able to programme
2The C bus.
5, a kind of device of expanding internal integrate circuit bus is characterized in that, comprises strobe multiplexer, and described strobe multiplexer is by PIO line and I
2The serial time clock line of C bus is connected with controller; Described strobe multiplexer by the expansion serial time clock line with respectively be connected from device; Described controller is by described I
2The serial data line of C bus directly respectively is connected from device with described.
6, the device of expanding internal integrate circuit bus according to claim 5 is characterized in that, is provided with web joint level I between described controller and the strobe multiplexer
2The bus switch of C device;
Pass through PIO line and an I between described bus switch and the described controller
2The C bus connects;
An I who obtains by expansion between described bus switch and the described strobe multiplexer
2The serial time clock line of C bus connects.
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| CN2008102245192A CN101398801B (en) | 2008-10-17 | 2008-10-17 | Method and device for expanding internal integrate circuit bus |
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|---|---|---|---|
| CN2008102245192A CN101398801B (en) | 2008-10-17 | 2008-10-17 | Method and device for expanding internal integrate circuit bus |
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| CN101398801B CN101398801B (en) | 2010-06-02 |
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| CN100353718C (en) * | 2003-09-16 | 2007-12-05 | 华为技术有限公司 | System and method for expanding I2C bus |
| CN100412837C (en) * | 2003-11-22 | 2008-08-20 | 鸿富锦精密工业（深圳）有限公司 | Multichannel internal integrated circuit |
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2008
- 2008-10-17 CN CN2008102245192A patent/CN101398801B/en active Active
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