CN111913904A - Method for automatically assigning mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor - Google Patents

Method for automatically assigning mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor Download PDF

Info

Publication number
CN111913904A
CN111913904A CN201910663602.8A CN201910663602A CN111913904A CN 111913904 A CN111913904 A CN 111913904A CN 201910663602 A CN201910663602 A CN 201910663602A CN 111913904 A CN111913904 A CN 111913904A
Authority
CN
China
Prior art keywords
terminal
clock
data
slave device
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910663602.8A
Other languages
Chinese (zh)
Other versions
CN111913904B (en
Inventor
郑正仁
林兴泽
金太爀
李真宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renis Co ltd
Original Assignee
Renis Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renis Co ltd filed Critical Renis Co ltd
Publication of CN111913904A publication Critical patent/CN111913904A/en
Application granted granted Critical
Publication of CN111913904B publication Critical patent/CN111913904B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

As an I2C system device including a device supporting I2C communication, including: a master device comprising an SCL terminal and an SDA terminal; and a first slave device comprising an SCL terminal and an SDA terminal; the first slave device determines whether an SCL terminal and an SDA terminal of the first slave device are connected to an SCL terminal and an SDA terminal of the master device, respectively, or connected to an SDA terminal and an SCL terminal of the master device, automatically sets to use a first address as an address of the first slave device if it is determined that the SCL terminal and the SDA terminal of the first slave device are connected to the SCL terminal and the SDA terminal of the master device, respectively, and automatically sets to use a second address as the address of the first slave device if it is determined that the SCL terminal and the SDA terminal of the first slave device are connected to the SDA terminal and the SCL terminal of the master device, respectively.

Description

Method for automatically assigning mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor
Technical Field
The present invention relates to a device using a master-slave communication protocol and a system configured by the device, and more particularly to a technique for automatically assigning addresses of slave devices that communicate with a master device.
Background
Recently, chip sets of the same configuration are being used for control of a plurality of devices such as front and rear cameras and dual cameras.
On the other hand, I2C is used as a serial computer bus developed by philips to connect low-speed peripheral devices to a motherboard, a built-in system, a mobile phone, and the like. I2C uses two bidirectional open collector or open drain lines called Serial Data (SDA) and Serial Clock (SCL) with pull-up resistors connected. In the I2C communication scheme, one master (master) device and one or more slave (slave) devices can be used. That is, the I2C communication scheme corresponds to a master-slave communication protocol.
In the I2C communication scheme, when chipsets (i.e., slave chipsets and slave devices) having the same configuration as described above are used, it is preferable to operate the chipsets on a single bus in order to reduce the complexity caused by a communication line connected to a master chipset (i.e., master device).
In order to operate the chipsets of the same configuration on the unified bus, it is necessary to assign different slave addresses to the respective chipsets. As one method for this, a method of fixing different slave addresses to slave chipsets of the same configuration and using them may be used. However, according to this method, the management of the address is inconvenient, and the possibility of misuse of the slave address increases. As another method, a method of assigning slave addresses to slave chipsets of the same configuration, respectively, according to the setting of additional H/W pins may be utilized. However, in this case, there is a problem that the additional H/W pin is required.
As a related patent, there is korean laid-open patent No. 10-2011-. The korean published patent relates to I2C address translation. Is a technique that involves a method of receiving an original I2C address, transforming the original I2C address into a transformed I2C address, and outputting.
Disclosure of Invention
In order to solve the above-described problems, the present invention provides a master-slave communication system apparatus and a communication apparatus capable of automatically assigning slave addresses to slave chip sets having the same configuration, respectively, without requiring additional overhead.
According to an aspect of the present invention, there may be provided a master-slave communication system apparatus including: a master device including a clock terminal and a data terminal; and a first slave device including a clock terminal and a data terminal. In this case, the first slave device uses a first address as the address of the first slave device when the clock terminal of the first slave device and the data terminal of the first slave device are connected to the clock terminal of the master device and the data terminal of the master device, respectively. In addition, when the clock terminal of the first slave device and the data terminal of the first slave device are connected to the data terminal of the master device and the clock terminal of the master device, respectively, a second address is used as the address of the first slave device.
At this time, the master-slave communication system device may further include a second slave device including a clock terminal and a data terminal. In this case, the second slave device uses the first address as the address of the second slave device when the clock terminal of the second slave device and the data terminal of the second slave device are connected to the clock terminal of the master device and the data terminal of the master device, respectively. In addition, when the clock terminal of the second slave device and the data terminal of the second slave device are connected to the data terminal of the host device and the clock terminal of the host device, respectively, the second address is used as the address of the second slave device.
In this case, the clock terminal of the first slave device and the data terminal of the first slave device may be connected to the clock terminal of the main device and the data terminal of the main device, respectively, and the clock terminal of the second slave device and the data terminal of the second slave device may be connected to the data terminal of the main device and the clock terminal of the main device, respectively.
At this time, the first slave device and the second slave device may have the same structure as each other.
At this time, the master-slave communication system device may be an I2C system device supporting I2C communication, the clock terminal of the first slave device may be an SCL terminal of the first slave device, the data terminal of the first slave device may be an SDA terminal of the first slave device, the clock terminal of the second slave device may be an SCL terminal of the second slave device, and the data terminal of the second slave device may be an SDA terminal of the second slave device.
According to another aspect of the present invention, there may be provided a communication apparatus including a data terminal and a clock terminal. The communication apparatus includes: and a control unit including a first terminal connected to the data terminal and a second terminal connected to the clock terminal. The control unit (1) uses the first terminal as a terminal for data use, uses the second terminal as a terminal for clock use, and uses a first address as an address of the communication device, when the terminal receiving the clock signal is the clock terminal, and (2) uses the second terminal as a terminal for data use, uses the first terminal as a terminal for clock use, and uses a second address as an address of the communication device, when the terminal receiving the clock signal is the data terminal.
According to still another aspect of the present invention, there may be provided a communication device including a data terminal and a clock terminal. The communication apparatus includes: a control section including a first terminal for data use and a second terminal for clock use; and a switching unit that selectively connects the data terminal and the clock terminal to the first terminal and the second terminal. In this case, the switching unit (1) connects the first terminal and the second terminal to the data terminal and the clock terminal, respectively, when the terminal receiving the clock signal is the clock terminal, and (2) connects the first terminal and the second terminal to the clock terminal and the data terminal, respectively, when the terminal receiving the clock signal is the data terminal. The control unit (1) uses a first address as the address of the communication device when the terminal receiving the clock signal is the clock terminal, and (2) uses a second address as the address of the communication device when the terminal receiving the clock signal is the data terminal.
According to still another aspect of the present invention, there is provided a communication device including a data terminal and a clock terminal. The communication apparatus includes: a first control unit including a terminal for data and a terminal for clock so as to use a first address as an address of the communication device; a second control section including a terminal for data and a terminal for clock so as to use a second address as an address of the communication apparatus; and a selection unit that selects one of the first control unit and the second control unit so that the selected control unit is activated and the unselected control unit is in an inactive state. In this case, the data-purpose terminal of the first control unit and the clock-purpose terminal of the first control unit are connected to the data terminal and the clock terminal, respectively. The data-purpose terminal of the second control unit and the clock-purpose terminal of the second control unit are connected to the clock terminal and the data terminal, respectively. The selection unit determines, among the first control unit and the second control unit, a control unit capable of decoding a specific packet received via the data terminal or the clock terminal, and activates the determined control unit.
At this time, the communication device may function as a slave device in a master-slave manner communication system.
According to still another aspect of the present invention, there may be provided a communication device including a data terminal and a clock terminal. The communication apparatus includes: and a control unit including a first terminal connected to the data terminal and a second terminal connected to the clock terminal. In this case, the control unit (1) uses the first terminal as a terminal for data use and the second terminal as a terminal for clock use, and uses a first address as an address of the communication device, when the data terminal of the communication device and the clock terminal of the communication device are connected to a data terminal of another communication device and a clock terminal of the another communication device connected to the communication device, respectively, and (2) causes the second terminal to be a terminal for data use, the first terminal to be a terminal for clock use, and the second address to be an address of the communication device, when the data terminal of the communication device and the clock terminal of the communication device are connected to a clock terminal of the another communication device and a data terminal of the another communication device, respectively.
At this time, the communication device may be a slave device in a master-slave manner communication system, and the other communication device may be a master device in the master-slave manner communication system.
According to an aspect of the present invention, there can be provided an I2C system device as an I2C system device including a device supporting I2C communication, including: a master device comprising an SCL terminal and an SDA terminal; and a first slave device including an SCL terminal and an SDA terminal.
At this time, the first slave device determines whether the SCL and SDA terminals of the first slave device are connected to the SCL and SDA terminals of the master device, respectively, or connected to the SDA and SCL terminals of the master device, and automatically sets to use a first address as an address of the first slave device when it is determined that the SCL and SDA terminals of the first slave device are connected to the SCL and SDA terminals of the master device, respectively.
At this time, the first slave device determines whether the SCL terminal and the SDA terminal of the first slave device are connected to the SCL terminal and the SDA terminal of the master device, respectively, or connected to the SDA terminal and the SCL terminal of the master device, and automatically sets to use the second address as the address of the first slave device when it is determined that the SCL terminal and the SDA terminal of the first slave device are connected to the SDA terminal and the SCL terminal of the master device, respectively.
At this time, the I2C system device may further include a second slave device including an SCL terminal and an SDA terminal.
Also, the second slave device may determine whether an SCL terminal and an SDA terminal of the second slave device are connected to an SCL terminal and an SDA terminal of the master device, respectively, or an SDA terminal and an SCL terminal of the master device, and automatically set to use the first address as an address of the second slave device in a case where it is determined that the SCL terminal and the SDA terminal of the second slave device are connected to the SCL terminal and the SDA terminal of the master device, respectively.
Also, the second slave device may determine whether an SCL terminal and an SDA terminal of the second slave device are connected to the SCL terminal and the SDA terminal of the master device, respectively, or connected to the SDA terminal and the SCL terminal of the master device, and automatically set to use the second address as the address of the second slave device in a case where the SCL terminal and the SDA terminal of the second slave device are connected to the SDA terminal and the SCL terminal of the master device, respectively.
At this time, (1) the SCL terminal and the SDA terminal of the first slave device may be connected to the SCL terminal and the SDA terminal of the master device, respectively, and the SCL terminal and the SDA terminal of the second slave device may be connected to the SDA terminal and the SCL terminal of the master device, respectively, or (2) the SCL terminal and the SDA terminal of the second slave device may be connected to the SCL terminal and the SDA terminal of the master device, respectively, and the SCL terminal and the SDA terminal of the first slave device may be connected to the SDA terminal and the SCL terminal of the master device, respectively.
At this time, the first slave device and the second slave device may be devices having the same structure as each other.
According to another aspect of the present invention, an I2C communication device including an SDA terminal and an SCL terminal may be provided.
The I2C communication device includes: an I2C control portion including a first terminal connected to the SDA terminal and a second terminal connected to the SCL terminal; and a terminal connection state detection unit that determines a terminal that receives a clock signal from the outside, from among the SDA terminal and the SCL terminal.
In this case, the I2C control unit (1) uses the first terminal as a data terminal and the second terminal as a clock terminal when determining that the terminal receiving the clock signal is the SCL terminal, and uses a first address as an address of the I2C communication device, and (2) uses the second terminal as a data terminal, the first terminal as a clock terminal, and a second address as an address of the I2C communication device when determining that the terminal receiving the clock signal is the SDA terminal.
According to another aspect of the present invention, an I2C communication device including an SDA terminal and an SCL terminal may be provided. The I2C communication device includes: an I2C control section including a first terminal and a second terminal; a switching part selectively connecting an SDA terminal and an SCL terminal to the first terminal and the second terminal; and a terminal connection state detection unit that determines a terminal that receives a clock signal from the outside, from among the SDA terminal and the SCL terminal.
In this case, the switching unit (1) connects the first terminal and the second terminal to the SDA terminal and the SCL terminal, respectively, when determining that the terminal receiving the clock signal is the SCL terminal, and (2) connects the first terminal and the second terminal to the SCL terminal and the SDA terminal, respectively, when determining that the terminal receiving the clock signal is the SDA terminal.
The I2C control unit (1) uses a first address as the address of the I2C communication device when determining that the terminal receiving the clock signal is the SCL terminal, and (2) uses a second address as the address of the I2C communication device when determining that the terminal receiving the clock signal is the SDA terminal.
According to yet another aspect of the present invention, an I2C communication device including an SDA terminal and an SCL terminal may be provided. The I2C communication device includes: an I2C control portion including a first terminal connected to the SDA terminal and a second terminal connected to the SCL terminal; and a terminal connection state detection unit which, in a state in which the I2C communication device is connected to another I2C communication device outside, determines whether the SDA terminal and the SCL terminal are connected to an SDA terminal and an SCL terminal of the other I2C communication device, respectively, and, otherwise, determines whether the SDA terminal and the SCL terminal are connected to an SCL terminal and an SDA terminal of the other I2C communication device, respectively.
In this case, the I2C control unit (1) may use the first terminal as a data terminal, the second terminal as a clock terminal, and a first address as an address of the I2C communication device when determining that the SDA terminal and the SCL terminal are connected to the SDA terminal and the SCL terminal of the other I2C communication device, respectively, and (2) may use the second terminal as a data terminal, the first terminal as a clock terminal, and a second address as an address of the I2C communication device when determining that the SDA terminal and the SCL terminal are connected to the SCL terminal and the SDA terminal of the other I2C communication device, respectively.
According to yet another aspect of the present invention, an I2C communication device including an SDA terminal and an SCL terminal may be provided. The I2C communication device includes: a first I2C control section including a data terminal and a clock terminal so that a first address is used as an address of the I2C communication device; a second I2C control section having the same structure as the first I2C control section such that a second address is used as an address of the I2C communication apparatus; and a selection unit that selects one of the first I2C control unit and the second I2C control unit such that the selected I2C control unit is activated and the unselected I2C control unit is inactivated.
At this time, the data terminal and the clock terminal of the first I2C control unit are connected to the SDA terminal and the SCL terminal, respectively. A data terminal and a clock terminal of the second I2C control unit are connected to the SCL terminal and the SDA terminal, respectively. The selector unit determines an I2C control unit, which can decode a specific packet received through the SDA terminal and the SCL terminal, among the first I2C control unit and the second I2C control unit, so that the determined I2C control unit is activated.
According to the present invention, when a master-slave communication system apparatus is used, slave addresses different from each other can be automatically assigned to slave chip sets having the same configuration without requiring additional overhead.
Drawings
Fig. 1 is a diagram for explaining a master-slave communication system apparatus of one embodiment of the present invention.
Fig. 2a shows the internal configuration of a first slave device and a second slave device according to a first embodiment of the present invention, and fig. 2b shows the configuration of a master-slave communication system device according to the first embodiment of the present invention.
Fig. 3a shows the internal configurations of a first slave device and a second slave device according to a second embodiment of the present invention, and fig. 3b shows the configuration of a master-slave communication system device according to the second embodiment of the present invention.
Fig. 4a shows the internal configuration of a first slave device and a second slave device according to a third embodiment of the present invention, and fig. 4b shows the configuration of a master-slave communication system device according to the third embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described in the present specification, and may be embodied in various forms. The terms used in the present specification are used to aid understanding of the embodiments, and are not intended to limit the scope of the present invention. In addition, the singular forms used below also include the plural forms as long as the words do not explicitly indicate the opposite meaning.
Fig. 1 is a diagram for explaining a master-slave communication system apparatus of one embodiment of the present invention.
Hereinafter, in the present specification, the master-slave communication system device may be an I2C communication system device. Hereinafter, in the present specification, the I2C system device or the I2C communication system device may be understood by the term of the master-slave communication system device instead.
The I2C system apparatus may include: a master device 1 supporting I2C communication, a first slave device 2, and a second slave device 3 having the same structure as the first slave device 2. The master device and the slave device may be ICs. The I2C system device may also be referred to as an I2C system in the following description.
In the present invention, it is intended to provide a method for automatically setting addresses of slave devices to slave devices having the same structure using the I2C system device. Here, the "slave devices having the same configuration" may mean, for example, an IC using the I2C communication protocol as an IC manufactured in the same process and having the same internal configuration and the same part number (part number).
In the present invention, the slave devices may be referred to as I2C communication devices.
The host device 1 is an IC including an SCL terminal 11 and an SDA terminal 12, and performs a host device function under the I2C communication protocol.
The first slave device 2 may determine whether the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 are connected to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively, or connected to the SDA terminal 12 and the SCL terminal 11 of the master device 1.
In this specification, the case where the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 are connected to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively, may be referred to as "non-cross-connection". In contrast, in the case of the first slave device 2, a case where the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 are connected to the SDA terminal 12 and the SCL terminal 11 of the master device 1, respectively, may be referred to as "cross-connection". In the case of using a chipset supported by the I2C communication protocol to which the present invention is not applied, "non-cross-connect" when the system is expected to operate normally, and "cross-connect" when the system is not likely to operate normally.
Then, the first slave device 2 may automatically set to use the first address as the address of the first slave device 2 when determining that the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 are connected to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively, that is, when determining that the connection is not cross-connected.
In contrast, the first slave device 2 may automatically set to use the second address as the address of the first slave device 2 when determining that the SDA terminal 21 and the SDA terminal 22 of the first slave device 2 are connected to the SDA terminal 12 and the SCL terminal 11 of the master device 1, respectively, that is, when determining that the slave devices are cross-connected.
Wherein the first address and the second address may be mutually different values stored in advance in the first slave device. The first address and the second address may be stored in a storage section provided in the first slave device, respectively.
For example, in fig. 1, since the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 are connected (non-cross-connected) to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively, the first slave device 2 can automatically set to use the first address as the address of the first slave device 2.
As with the first slave device 2, it can be determined whether the SCL terminal 31 and the SDA terminal 32 of the second slave device 3 are connected to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively, i.e., are not cross-connected, otherwise, whether the SDA terminal 12 and the SCL terminal 11 of the master device 1 are connected, i.e., are cross-connected, and the address of the second slave device 3 can be automatically set.
For example, in fig. 1, the second slave device 3 can automatically set to use the second address as the address of the second slave device 3 because the SCL terminal 31 and the SDA terminal 32 of the second slave device 3 are connected (cross-connected) to the SDA terminal 12 and the SCL terminal 11 of the master device 1, respectively.
The first slave device 2 and the second slave device 3 are devices having the same configuration as each other, and are different from each other only in the point of being cross-connected or non-cross-connected to the master device 1.
Fig. 2a shows the internal structure of the first slave device and the second slave device according to the first embodiment of the present invention.
Fig. 2b shows the structure of the I2C system device of the first embodiment of the present invention.
The first slave device 2 may include an SCL terminal 21 and an SDA terminal 22. Further, the first slave device 2 may include an I2C control unit 210, a switching unit 230, and a terminal connection state detection unit 240.
The I2C control section 210 may include a first terminal 211 and a second terminal 212.
The second slave device 3 may include an SCL terminal 31 and an SDA terminal 32. The second slave device 3 may include an I2C control unit 310, a switching unit 340, and a terminal connection state detection unit 340.
The I2C control section 310 may include a first terminal 311 and a second terminal 312.
As described above, the first slave device 2 and the second slave device 3 may have the same structure as each other.
As shown in fig. 2b, the first slave device 2 and the second slave device 3 may be connected to the master device 1.
The host device 1 may include an SCL terminal 11 and an SDA terminal 12.
For example, the SCL terminal 21 and the SDA terminal 22 of the first slave device 2 may be connected (non-cross-connected) to the SCL terminal 11 and the SDA terminal 12 of the master device 1, respectively. The SCL terminal 31 and the SDA terminal 32 of the second slave device 3 may be connected (cross-connected) to the SDA terminal 12 and the SCL terminal 11 of the master device 1, respectively.
The following description will be made with reference to the first slave device 2.
The SCL terminal 21 and the SDA terminal 22 of the first slave device 2 may be connected (non-cross-connected) to the SCL terminal 11 and the SDA terminal 12 of the master device 1 through the 11 th transmission line TL11 and the 12 th transmission line TL12, respectively. The SCL terminal 21 and the SDA terminal 22 of the first slave device 2 can receive the transmission clock signal and the data signal through the 11 th transmission line TL11 and the 12 th transmission line TL12, respectively.
The terminal connection state detecting part 240 of the first slave device 2 may receive signals detected from the SCL terminal 21 and the SDA terminal 22, respectively. The terminal connection state detection unit 240 may determine a terminal that receives a clock signal among the reception signals. The terminal connection state detection unit 240 may transmit a result of the determination to the switching unit 230 and the I2C control unit 210 if the terminal receiving the clock signal is determined. For example, in fig. 2b, the terminal receiving the clock signal may be SCL terminal 21.
The switching part 230 of the first slave device 2 can selectively connect the SCL terminal 21 and the SDA terminal 22 to the first terminal 211 and the second terminal 212 of the I2C control part 210. At this time, the "selection" may be performed according to whether the terminal receiving the clock signal is one of the SCL terminal 21 and the SDA terminal 22. That is, the switching unit 230 may connect the first terminal 211 and the second terminal 212 to the SCL terminal 21 and the SDA terminal 22, respectively, when determining that the terminal receiving the clock signal is the SCL terminal 21, and (2) may connect the first terminal 211 and the second terminal 212 to the SDA terminal 22 and the SCL terminal 21, respectively, when determining that the terminal receiving the clock signal is the SDA terminal 22. For example, in fig. 2b, the switch 230 may connect the first terminal 211 and the second terminal 212 to the SCL terminal 21 and the SDA terminal 22, respectively, corresponding to the case where the terminal receiving the clock signal is determined to be the SCL terminal 21.
The determination of whether to receive a clock signal or a data signal through a specific terminal may be performed in various ways by those skilled in the art, and thus, the method thereof will not be described in detail in the present specification. However, it can be easily understood that the clock signal and the data signal can be distinguished from each other and decided, for example, when an internal clock having a period much faster than the clock signal that needs to be received is used.
The I2C control unit 210 may be configured to use a first address as the address of the first slave device 2 when determining that the terminal receiving the clock signal is the SCL terminal 21, and may be configured to use a second address as the address of the first slave device 2 when determining that the terminal receiving the clock signal is the SDA terminal 22. For example, in fig. 2b, this corresponds to the case where it is determined that the terminal receiving the clock signal is the SCL terminal 21, and thus a first address can be used as the address of the first slave device 2.
In the present specification, the "I2C control unit" may be regarded as a module that functions to determine which of the SCL terminal and the SDA terminal of the slave device is to be used as the clock terminal and which is to be used as the data terminal in the slave device according to the embodiment of the present invention using the I2C communication protocol. Also, at the same time, a function of deciding an address to be used by the corresponding slave device may be performed.
The details described in the first slave device 2 can be applied in the same manner to the second slave device 3.
At this time, the SCL terminal 21, the SDA terminal 22, the I2C control unit 210, the switching unit 230, the terminal connection state detection unit 240, the first terminal 211, and the second terminal 212 of the first slave device 2 may correspond to the SCL terminal 31, the SDA terminal 32, the I2C control unit 310, the switching unit 340, the terminal connection state detection unit 340, the first terminal 311, and the second terminal 312 of the second slave device 3, respectively.
For example, in fig. 2b, if the same principle as the address setting principle of the first slave device 2 is applied to the second slave device 3, the second slave device 3 may use a second address as the address of the second slave device 3.
In summary, in the first embodiment of fig. 2a and 2b, the first slave device 2 and the second slave device 3 can automatically assign the internal address according to the external connection status.
Fig. 3a shows the internal configuration of a first slave device and a second slave device according to a second embodiment of the present invention, and fig. 3b shows the configuration of an I2C system device according to the second embodiment of the present invention.
The first slave device 2 may include an SCL terminal 21 and an SDA terminal 22. Further, the first slave device 2 may include an I2C control section 210 and a terminal connection state detection section 240.
The I2C control unit 210 may include a first terminal 211, a second terminal 212, a switching unit 213, and a clock and data input/output unit 214.
The clock and data input/output portion 214 may include a clock terminal CLK and a data terminal D. The clock and data input/output unit 214 can function to supply the clock and data received from the first terminal 211 and the second terminal 212 to other logic (not shown) present in the first slave device 2 or to supply the clock and data from the first slave device 2 to the master device 1.
The second slave device 3 may include an SCL terminal 31 and an SDA terminal 32. The second slave device 3 may include an I2C control unit 310 and a terminal connection state detection unit 340.
The I2C control unit 310 may include a first terminal 311, a second terminal 312, a switching unit 313, and a clock and data input/output unit 314.
The clock and data input/output unit 314 of the second slave device 3 may have the same function as the clock and data input/output unit 214 of the first slave device 2.
As described above, the first slave device 2 and the second slave device 3 may have the same structure as each other.
As shown in fig. 3b, the first slave device 2 and the second slave device 3 may be connected to the master device 1.
The connection relationship between the master device 1 and the first and second slave devices 2 and 3 may be the same as that shown in fig. 3 b.
The following description will be made with reference to the first slave device 2.
The SCL terminal 21 and the SDA terminal 22 of the first slave device 2 may be connected to the SCL terminal 11 and the SDA terminal 12 of the master device 1 through the 11 th transmission line TL11 and the 12 th transmission line TL12, respectively. The SCL terminal 21 and the SDA terminal 22 of the first slave device 2 can receive the transmission clock signal and the data signal from the master device 1 through the 11 th transmission line TL11 and the 12 th transmission line TL12, respectively.
The terminal connection state detecting part 240 of the first slave device 2 may receive signals transmitted from the SCL terminal 21 and the SDA terminal 22, respectively. The terminal connection state detection unit 240 may determine a terminal that receives a clock signal among the reception signals. The terminal connection state detection unit 240 may transmit a result of the determination to the switching unit 213 of the I2C control unit 210 if the terminal receiving the clock signal is determined. For example, in fig. 3b, the terminal receiving the clock signal may be SCL terminal 21.
The first terminal 211 and the second terminal 212 of the I2C control part 210 of the first slave device 2 may be connected to the SCL terminal 21 and the SDA terminal 22, respectively. Therefore, the switching unit 213 of the I2C control unit 210 can selectively connect the first terminal 211 and the second terminal 212 to the clock terminal CLK and the data terminal D of the clock and data input/output unit 214.
That is, the switching unit 213 may connect the first terminal 211 and the second terminal 212 to the clock terminal CLK and the data terminal D, respectively, when determining that the terminal receiving the clock signal is the SCL terminal 21, and may connect the first terminal 211 and the second terminal 212 to the data terminal D and the clock terminal CLK, respectively, when determining that the terminal receiving the clock signal is the SDA terminal 22. For example, in fig. 3b, the switch 213 may connect the first terminal 211 and the second terminal 212 to the clock terminal CLK and the data terminal D, respectively, corresponding to the case where the terminal for receiving the clock signal is determined to be the SCL terminal 21.
When determining that the terminal receiving the clock signal is the SCL terminal 21, the I2C control unit 210 may use the first terminal 211 as a clock terminal and the second terminal 212 as a data terminal. At this time, the first address may be used as the address of the first slave device 2. Alternatively, when determining that the terminal receiving the clock signal is the SDA terminal 22, the I2C control unit 210 may use the second terminal 212 as a clock terminal and the first terminal 211 as a data terminal. At this time, the second address may be used as the address of the first slave device 2.
The details described in the first slave device 2 can also be applied in the same way to the second slave device 3.
At this time, the SCL terminal 21, the SDA terminal 22, the I2C control section 210, the first terminal 211, the second terminal 212, the switching section 213, the clock and data input/output section 214, and the terminal connection state detection section 240 of the first slave device 2 may correspond to the SCL terminal 31, the SDA terminal 32, the I2C control section 310, the first terminal 311, the second terminal 312, the switching section 313, the clock and data input/output section 314, and the terminal connection state detection section 340 of the second slave device 3, respectively.
For example, in fig. 3b, if the same principle as the address setting principle of the first slave device 2 is applied to the second slave device 3, the second slave device 3 may use a second address as the address of the second slave device 3.
In summary, in the second embodiment of fig. 3a and 3b, it can be automatically set that the first slave device 2 uses the first address and the second slave device 3 uses the second address.
Fig. 4a shows the internal configuration of the first slave device and the second slave device according to the third embodiment of the present invention, and fig. 4b shows the configuration of the I2C system device according to the third embodiment of the present invention.
The first slave device 2 may include an SCL terminal 21 and an SDA terminal 22. Also, the first slave device 2 may include a first I2C control part 210, a second I2C control part 220, and a selection part 250. In addition, the first slave device 2 may comprise further internal circuitry not shown in fig. 4 a.
The first I2C control portion 210 may include a first terminal 211 and a second terminal 212. For example, the first terminal 211 may be a clock terminal and the second terminal 212 may be a data terminal. Also, the first I2C control part 210 may make use of the first address as the address of the first slave device 2.
The second I2C control part 220 may have the same structure as the first I2C control part 210. That is, the second I2C control unit 220 may include a third terminal 221 and a fourth terminal 222. For example, the third terminal 221 may be a clock terminal, and the fourth terminal 222 may be a data terminal. Also, the second I2C control section 220 may cause a second address to be used as the address of the first slave device 2.
The selector 250 may select one of the first I2C control 210 and the second I2C control 220, and activate the selected I2C control 210 or 220, so that the unselected I2C control 220 or 210 is in an inactive state. The meaning of "active" and "inactive" may mean that the I2C control unit that is "active" is used, and the I2C control unit that is "inactive" is not used.
The first slave device 2 and the second slave device 3 may have the same structure as each other.
The second slave device 3 may include an SCL terminal 31 and an SDA terminal 32. Also, the second slave device 3 may include a first I2C control part 310, a second I2C control part 320, and a selection part 350.
The first I2C control section 310 may include a first terminal 311 and a second terminal 312. For example, the first terminal 311 may be a clock terminal, and the second terminal 312 may be a data terminal. Also, the first I2C control part 310 may make use of the first address as the address of the second slave device 3.
The second I2C control part 320 may have the same structure as the first I2C control part 310. That is, the second I2C control unit 320 may include a third terminal 321 and a fourth terminal 322. For example, the third terminal 321 may be a clock terminal, and the fourth terminal 322 may be a data terminal. Also, the second I2C control section 320 may cause a second address to be used as the address of the second slave device 3.
The selector 350 may select one of the first I2C controller 310 and the second I2C controller 320 such that the selected I2C controller 310 or 320 is activated and the unselected I2C controller 320 or 310 is deactivated.
As shown in fig. 4b, the first slave device 2 and the second slave device 3 may be connected to the master device 1. The connection relationship between the master device 1 and the first and second slave devices 2 and 3 may be the same as that shown in fig. 2 b.
The following description will be made with reference to the first slave device 2.
The SCL terminal 21 and the SDA terminal 22 of the first slave device 2 can receive the transmission clock signal and the data signal from the SCL terminal 11 and the SDA terminal 12 of the master device 1 through the 11 th transmission line TL11 and the 12 th transmission line TL12, respectively.
A first terminal (e.g., a clock terminal) 211 and a second terminal (e.g., a data terminal) 212 of the first I2C control part 210 of the first slave device 2 may be connected to the SCL terminal 21 and the SDA22 terminal, respectively. That is, the first terminal (e.g., clock terminal) 211 and the second terminal (e.g., data terminal) 212 of the first I2C control part 210 may receive signals transmitted from the SCL terminal 21 and the SDA terminal 22, respectively.
The third terminal (e.g., clock terminal) 221 and the fourth terminal (e.g., data terminal) 222 of the second I2C control part 220 of the first slave device 2 may be connected to the SDA terminal 22 and the SCL terminal 21, respectively. That is, the third terminal (e.g., clock terminal) 221 and the fourth terminal (e.g., data terminal) 222 of the first I2C control part 210 may receive signals transmitted from the SDA terminal 22 and the SCL terminal 21, respectively.
The selector 250 of the first slave device 2 may determine the I2C controller that can successfully decode the specific packet received through the SCL terminal 21 and the SDA terminal 22 among the first I2C controller 210 and the second I2C controller 220, and activate the determined I2C controller. At this time, successfully decoding the specific packet may mean decoding the packet transmitted from the master device 1 into a data signal instead of a clock signal.
For example, the selection unit 250 may select the first I2C control unit 210, which has the first terminal (e.g., clock terminal) 211 connected to the SCL terminal 21 transmitting the clock signal, as an I2C control unit capable of successfully decoding the specific packet received through the SCL terminal 21 and the SDA terminal 22. Furthermore, the selector 250 may activate the selected first I2C control 210 and deactivate the unselected second I2C control 220. That is, the first I2C control unit 210 may be responsible for the communication function of the first slave device 2.
The details described in the first slave device 2 can also be applied in the same way to the second slave device 3.
At this time, the SCL terminal 21, the SDA terminal 22, the first I2C control part 210, the first terminal 211, the second terminal 212, the second I2C control part 220, the third terminal 221, the fourth terminal 222, and the selection part 250 of the first slave device 2 may correspond to the SCL terminal 31, the SDA terminal 32, the first I2C control part 310, the first terminal 311, the second terminal 312, the second I2C control part 320, the third terminal 321, the fourth terminal 322, and the selection part 350 of the second slave device 3, respectively.
For example, in fig. 4b, if the same principle as the address setting principle of the first slave device 2 is applied to the second slave device 3, the second I2C control part 320 of the second slave device 3 may be responsible for the communication function of the second slave device 3. That is, the second slave device 3 may use the second address as the address of the second slave device 3.
In summary, in the third embodiment of fig. 4a and 4b, it can be automatically set that the first slave device 2 uses the first address and the second slave device 3 uses the second address.
With the above-described embodiments of the present invention, those skilled in the art to which the present invention pertains can easily make various changes and modifications without departing from the essential characteristics of the invention. The contents of the claims may be combined with other claims not referred to within the scope of the specification.

Claims (11)

1. A master-slave communication system apparatus comprising:
a master device including a clock terminal and a data terminal; and
a first slave device comprising a clock terminal and a data terminal;
the first slave device is at
When the clock terminal of the first slave device and the data terminal of the first slave device are connected to the clock terminal of the master device and the data terminal of the master device, respectively, a first address is used as the address of the first slave device,
when the clock terminal of the first slave device and the data terminal of the first slave device are connected to the data terminal of the master device and the clock terminal of the master device, respectively, a second address is made to be used as the address of the first slave device.
2. The master-slave communication system apparatus of claim 1,
also included is a second slave device comprising a clock terminal and a data terminal;
the second slave device is at
The clock terminal of the second slave device and the data terminal of the second slave device are connected to the clock terminal of the master device and the data terminal of the master device, respectively, such that the first address is used as the address of the second slave device,
and a data terminal of the second slave device and a clock terminal of the master device, respectively, such that the second address is used as the address of the second slave device.
3. The master-slave communication system apparatus of claim 2,
the clock terminal of the first slave device and the data terminal of the first slave device are connected to the clock terminal of the master device and the data terminal of the master device, respectively, and,
the clock terminal of the second slave device and the data terminal of the second slave device are connected to the data terminal of the main device and the clock terminal of the main device, respectively.
4. The master-slave communication system apparatus of claim 2,
the first slave device and the second slave device have the same structure as each other.
5. The master-slave communication system apparatus of claim 2,
the master-slave communication system devices are I2C system devices supporting I2C communication,
the clock terminal of the first slave device is the SCL terminal of the first slave device,
the data terminal of the first slave device is the SDA terminal of the first slave device,
the clock terminal of the second slave device is an SCL terminal of the second slave device, and,
the data terminal of the second slave device is an SDA terminal of the second slave device.
6. A communication device, as a communication device including a data terminal and a clock terminal, comprising:
a control unit including a first terminal connected to the data terminal and a second terminal connected to the clock terminal;
the control unit (1) uses the first terminal as a terminal for data use, uses the second terminal as a terminal for clock use, and uses a first address as an address of the communication device, when the terminal receiving the clock signal is the clock terminal, and (2) uses the second terminal as a terminal for data use, uses the first terminal as a terminal for clock use, and uses a second address as an address of the communication device, when the terminal receiving the clock signal is the data terminal.
7. A communication device, as a communication device including a data terminal and a clock terminal, comprising:
a control section including a first terminal for data use and a second terminal for clock use; and
a switching unit that selectively connects the data terminal and the clock terminal to the first terminal and the second terminal;
the switching unit (1) connects the first terminal and the second terminal to the data terminal and the clock terminal, respectively, when a terminal receiving a clock signal is the clock terminal, and (2) connects the first terminal and the second terminal to the clock terminal and the data terminal, respectively, when a terminal receiving the clock signal is the data terminal;
the control unit (1) uses a first address as the address of the communication device when the terminal receiving the clock signal is the clock terminal, and (2) causes a second address to be used as the address of the communication device when the terminal receiving the clock signal is the data terminal.
8. A communication device, as a communication device including a data terminal and a clock terminal, comprising:
a first control unit including a terminal for data and a terminal for clock so as to use a first address as an address of the communication device;
a second control section including a terminal for data and a terminal for clock so as to use a second address as an address of the communication apparatus; and
a selection unit that selects one of the first control unit and the second control unit so that the selected control unit is activated and the unselected control unit is in an inactivated state;
a terminal for data of the first control unit and a terminal for clock of the first control unit are connected to the data terminal and the clock terminal, respectively,
a terminal for data of the second control unit and a terminal for clock of the second control unit are connected to the clock terminal and the data terminal, respectively,
the selection unit determines, among the first control unit and the second control unit, a control unit capable of decoding a specific packet received via the data terminal or the clock terminal, and activates the determined control unit.
9. The communication apparatus according to any one of claims 6 to 8,
the communication device functions as a slave device in a master-slave communication system.
10. A communication device, as a communication device including a data terminal and a clock terminal, comprising:
a control unit including a first terminal connected to the data terminal and a second terminal connected to the clock terminal;
the control part
(1) The communication apparatus includes a first terminal and a second terminal, and the first terminal is used as a terminal for data use and the second terminal is used as a terminal for clock use, and a first address is used as an address of the communication apparatus, when the data terminal of the communication apparatus and the clock terminal of the communication apparatus are connected to a data terminal of another communication apparatus and a clock terminal of the another communication apparatus, respectively, and (2) the second terminal is used as a terminal for data use, the first terminal is used as a terminal for clock use, and the second address is used as an address of the communication apparatus, when the data terminal of the communication apparatus and the clock terminal of the communication apparatus are connected to a clock terminal of the another communication apparatus and a data terminal of the another communication apparatus, respectively.
11. The communication device of claim 10,
the communication device is a slave device in a master-slave mode communication system,
the other communication device is a master device in the master-slave mode communication system.
CN201910663602.8A 2019-05-08 2019-07-19 Method for automatically allocating mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor Active CN111913904B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0053564 2019-05-08
KR1020190053564A KR20200129333A (en) 2019-05-08 2019-05-08 Method for assigning different addresses on a plurality of slave devices using I2C communication protocol and a device for the same

Publications (2)

Publication Number Publication Date
CN111913904A true CN111913904A (en) 2020-11-10
CN111913904B CN111913904B (en) 2024-05-14

Family

ID=73242907

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910663602.8A Active CN111913904B (en) 2019-05-08 2019-07-19 Method for automatically allocating mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor

Country Status (2)

Country Link
KR (1) KR20200129333A (en)
CN (1) CN111913904B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114020673A (en) * 2021-10-14 2022-02-08 上海矽睿科技股份有限公司 Automatic wire jumper device and communication equipment

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114020679B (en) * 2021-11-12 2023-11-07 中国船舶集团有限公司第七一一研究所 I2C bus control circuit and circuit system for ship

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080147941A1 (en) * 2005-04-29 2008-06-19 Nxp B.V. Dynamic 12C Slave Device Address Decoder
US20120191889A1 (en) * 2011-01-24 2012-07-26 Digital Imaging Systems Gmbh Method to differentiate identical devices on a two-wire interface
CN204270294U (en) * 2014-10-17 2015-04-15 技嘉科技股份有限公司 The transmission line module of internal integrated circuit interface

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080147941A1 (en) * 2005-04-29 2008-06-19 Nxp B.V. Dynamic 12C Slave Device Address Decoder
US20120191889A1 (en) * 2011-01-24 2012-07-26 Digital Imaging Systems Gmbh Method to differentiate identical devices on a two-wire interface
CN204270294U (en) * 2014-10-17 2015-04-15 技嘉科技股份有限公司 The transmission line module of internal integrated circuit interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114020673A (en) * 2021-10-14 2022-02-08 上海矽睿科技股份有限公司 Automatic wire jumper device and communication equipment

Also Published As

Publication number Publication date
CN111913904B (en) 2024-05-14
KR20200129333A (en) 2020-11-18

Similar Documents

Publication Publication Date Title
RU2231230C2 (en) Set of interfaces
US7249209B2 (en) System and method for dynamically allocating inter integrated circuits addresses to multiple slaves
US10706000B2 (en) Memory card access module and memory card access method
US10102177B2 (en) Serial communication system, communication control unit, and electronic device for finding and assigning unused addresses
US20080270654A1 (en) Bus System for Selectively Controlling a Plurality of Identical Slave Circuits Connected to the Bus and Method Therefore
US7774511B2 (en) Addressing multiple devices on a shared bus
JP2002232508A (en) Electronic device and method for automatically selecting interface protocol used by the electronic device
EP0619548A1 (en) Interface circuit between a control bus and an integrated circuit suitable for two different protocol standards
CN114385527B (en) Control method and main board of hard disk compatible platform
KR20160037114A (en) Serial peripheral interface
US11921652B2 (en) Method, apparatus and system for device transparent grouping of devices on a bus
CN111913904B (en) Method for automatically allocating mutually different addresses to a plurality of slave devices using a master-slave communication protocol and device therefor
US7945807B2 (en) Communication system for a plurality of I/O cards by using the GPIO and a method thereof
CN114911743A (en) SPI slave device, SPI master device and related communication method
JP2024508592A (en) USB interface multiplexing method, circuit, electronic equipment and storage medium
US20200285598A1 (en) Memory Card Access Module and Memory Card Access Method
CN113641610A (en) Processor interface circuit, time-sharing multiplexing method of processor interface and electronic equipment
CN114996184B (en) Compatible implementation SPI or I 2 Interface module of slave C and data transmission method
KR102044212B1 (en) Method for assigning different addresses on a plurality of slave devices using I2C communication protocol and a device for the same
US7430625B2 (en) Connection of a memory component to an electronic device via a connection bus utilizing multiple interface protocols
JP4906688B2 (en) Control signal communication method and optical transceiver device
KR101816895B1 (en) Management serial bus for chassis type communication equipment
JP4219784B2 (en) Expansion unit for information processing equipment
CN111797583A (en) Pin multiplexing device and method for controlling pin multiplexing device
US11249931B2 (en) Pin multiplexer and method for controlling pin multiplexer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant