CN114020679B - I2C bus control circuit and circuit system for ship - Google Patents
I2C bus control circuit and circuit system for ship Download PDFInfo
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- CN114020679B CN114020679B CN202111338596.2A CN202111338596A CN114020679B CN 114020679 B CN114020679 B CN 114020679B CN 202111338596 A CN202111338596 A CN 202111338596A CN 114020679 B CN114020679 B CN 114020679B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
Abstract
The application provides an I2C bus interface control circuit and a circuit system for a ship, wherein the I2C bus interface control circuit comprises: the system comprises a bus driving unit, a level monitoring unit and a data correction unit, wherein a data transmission link between a main device and a slave device is divided into a sending link and a receiving link through the bus driving unit, the level of a feedback signal sent from the slave device to the main device is monitored, the feedback signal sent from the slave device to the main device is subjected to data correction and then is transmitted to the main device on the receiving link of the bus driving unit, so that erroneous data acquisition caused by the reduction of the level of an I2C bus is avoided, and the safety and the reliability of the whole circuit system are ensured.
Description
Technical Field
The application relates to the technical field of I2C integrated circuits, in particular to an I2C bus control circuit and a circuit system for ships.
Background
The internal integrated circuit (English: inter Integrated Circuit, I2C) bus is a simple bidirectional two-wire synchronous Serial bus, and comprises two signal lines, namely a bidirectional Serial Data (SDA) line and a Serial Clock (SCL) line. The SDA line of all devices accessing the I2C bus are connected to the SDA line of the I2C bus, while the SCL line of all devices accessing the I2C bus are connected to the SCL line of the I2C bus.
The devices accessing the I2C bus include at least one I2C master and at least one I2C slave. The I2C master device is a device configured in a master mode and can initialize transmission, generate clock signals and terminate transmission, namely control data transmission of an I2C bus; and an I2C slave is a device configured in slave mode that is addressed by the I2C master when the I2C bus transfers data.
The I2C bus is widely applied to the design of electronic equipment of an automatic ship control system, and in practice, the level transmitted by a data line of the I2C bus is continuously reduced in a critical state period just before damage of an I2C chip, so that data analysis errors of a receiving end of main equipment are caused, the errors cannot be avoided in a software mode, and the errors can have great influence on the reliability operation of a circuit system and the electronic equipment controlled by the I2C bus.
Therefore, it is necessary to provide an I2C bus control circuit and a circuit system for a ship, so as to overcome the above drawbacks, and realize data correction when an I2C bus level is abnormal, so as to ensure the safety and reliability of the whole circuit system.
Disclosure of Invention
In order to overcome the defects of the prior art, the application aims to provide an I2C bus control circuit and a circuit system for a ship, so as to solve the problem of error data acquisition caused by abnormal I2C bus level in the prior art.
The application adopts the following technical scheme:
according to an aspect of the present application, there is provided a semiconductor device including: the bus driving unit is connected to an I2C bus between a master device and a slave device, and the master device and the slave device communicate through the I2C bus, wherein the bus driving unit directly sends a data signal output by the master device to the slave device through a data line of the I2C bus and directly sends a clock signal output by the master device to the slave device through a clock line of the I2C bus; the level monitoring unit is electrically connected with the data line of the I2C bus, so as to receive a feedback signal sent by the slave device to the master device and output a first signal and a second signal based on the feedback signal, wherein the first signal and the second signal reflect the feedback signal and the voltage range of the feedback signal; and a data correction unit electrically connected to the bus driving unit and the level monitoring unit, respectively, to receive the first signal and the second signal, and generate a corrected feedback signal based on the first signal and the second signal, and transmit the corrected feedback signal to the master device via the bus driving unit.
Further, the bus driving unit enhances the corrected feedback signal and transmits the enhanced feedback signal to the master device.
Further, the control circuit further comprises an alarm processing unit, wherein the alarm processing unit is electrically connected with the level monitoring unit, so as to receive the first signal and the second signal, and generate an alarm signal based on the first signal and the second signal to trigger the upper computer to implement alarm operation.
Further, the level monitoring unit includes a first comparator and a second comparator, each having a positive input and a negative input, and each for receiving the feedback signal;
the negative input end of the first comparator is connected to an intermediate node after a third resistor and a fourth resistor are connected in series, and the third resistor and the fourth resistor are connected in series and then electrically connected between a power supply and ground so as to input voltage divided by the third resistor and the fourth resistor to the negative input end of the first comparator; the negative input end of the second comparator is connected to an intermediate node after the sixth resistor and the seventh resistor are connected in series, and the sixth resistor and the seventh resistor are connected in series and then electrically connected between a power supply and the ground so as to input the voltage divided by the sixth resistor and the seventh resistor to the negative input end of the second comparator; the output end of the first comparator outputs the first signal, and the output end of the second comparator outputs the second signal.
Further, the level monitoring unit further comprises a first resistor, a second resistor and a fifth resistor; the first end of the first resistor is connected with a power supply, and the second end of the first resistor is electrically connected with a data line for transmitting the feedback signal; the first end of the second resistor is connected with a power supply, and the second end of the second resistor is electrically connected with the output end of the first comparator for outputting the first signal; the first end of the fifth resistor is connected with a power supply, and the second end of the fifth resistor is electrically connected with the output end of the second comparator for outputting the second signal.
Further, the data correction unit includes a logic or gate, two input ends of the logic or gate respectively receive the first signal and the second signal, and an output end of the logic or gate outputs the corrected feedback signal.
Further, the alarm processing unit comprises a logic exclusive-or gate, two input ends of the logic exclusive-or gate respectively receive the first signal and the second signal, and an output end of the logic exclusive-or gate outputs the alarm signal.
Further, the values of the first signal and the second signal reflect the voltage range of the feedback signal, wherein the voltage range comprises a normal area, an abnormal early warning area and a failure area.
Further, under the condition that the logic level of the alarm signal is 1, the alarm signal triggers the upper computer to alarm, and under the condition that the logic level of the alarm signal is 0, the alarm signal does not trigger the upper computer to alarm.
According to another aspect of the application there is provided circuitry for a watercraft, the circuitry comprising the I2C bus control circuit described above.
Compared with the prior art, the I2C bus control circuit and the circuit system for the ship provided by the embodiment of the application, wherein the I2C bus interface control circuit comprises: the system comprises a bus driving unit, a level monitoring unit and a data correction unit, wherein a data transmission link between a main device and a slave device is divided into a sending link and a receiving link through the bus driving unit, the level of a feedback signal sent from the slave device to the main device is monitored, the feedback signal sent from the slave device to the main device is subjected to data correction and then is transmitted to the main device on the receiving link of the bus driving unit, so that erroneous data acquisition caused by the reduction of the level of an I2C bus is avoided, and the safety and the reliability of the whole circuit system are ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an overall architecture of an I2C bus control circuit provided by an embodiment of the present application;
FIG. 2 is a block diagram of the general architecture of yet another I2C bus control circuit provided by an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of the bus driving unit in FIG. 1;
FIG. 4 is a schematic circuit diagram of the level monitor unit in FIG. 1;
FIG. 5 is a schematic circuit diagram of the data correction unit of FIG. 1;
FIG. 6 is a schematic circuit diagram of the alarm processing unit of FIG. 2;
FIG. 7 is a schematic diagram of a simulation of an anomaly in voltage level from a device data level;
fig. 8 is a schematic diagram of a simulation of still another slave device data level voltage value anomaly.
Detailed Description
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application, as well as the preferred embodiments thereof, together with the following detailed description of the application, given by way of illustration only, together with the accompanying drawings.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 1 is a general block diagram of an I2C bus control circuit according to an embodiment of the present application, fig. 3 is a schematic circuit diagram of the bus driving unit in fig. 1, fig. 4 is a schematic circuit diagram of the level monitoring unit in fig. 1, and fig. 5 is a schematic circuit diagram of the data correction unit in fig. 1.
Referring to fig. 1, 3-5, the present application provides an I2C bus control circuit 100, comprising: a bus driving unit 50, a level monitoring unit 60, and a data correcting unit 70; the bus driving unit 50 is connected to an I2C bus between a master device 1 and a slave device 2, the master device 1 and the slave device 2 communicate via the I2C bus, wherein the bus driving unit 50 directly transmits a data signal output by the master device 1 to the slave device 2 via a data line 3 of the I2C bus, and directly transmits a clock signal output by the master device 1 to the slave device 2 via a clock line 4 of the I2C bus; a level monitoring unit 60, the level monitoring unit 60 being electrically connected to the data line 3 of the I2C bus to receive a feedback signal transmitted from the slave device 2 to the master device 1 and to output a first signal 61 and a second signal 62 based on the feedback signal, the first signal 61 and the second signal 62 reflecting the feedback signal and a level range thereof; the data correction unit 70 is electrically connected to the bus driving unit 50 and the level monitoring unit 60 to receive the first signal 61 and the second signal 62, respectively, and generates a corrected feedback signal based on the first signal 61 and the second signal 62, and transmits the corrected feedback signal to the host device 1 via the bus driving unit 50.
In the prior art, when the I2C bus transmits data, the data signal is transmitted from the master device to the slave device and the response signal is fed back from the slave device to the master device under different time slots by the cooperation of clock pulses of a clock signal line (SCL line) when the data is transmitted on the same data line (SDA line) between the master device and the slave device; for example, each time the master 1 transmits a byte, the data line (SDA line) is released during the 9 th clock pulse, and then a reply signal is fed back by the slave, which is specified as an active reply bit (ACK) when the reply signal is low, indicating that the slave has successfully received the byte; when the acknowledgement signal is high, it is specified as a non-acknowledgement bit (NACK), which generally indicates that the reception of the byte from the device was not successful. After receiving the last byte, the slave transmits a NACK signal to control the master to end data transmission and releases the data line (SDA line) so that the master 1 transmits a stop signal. After releasing the I2C bus, the level on the data line (SDA line) should remain high all the time if there is no reply signal.
In the embodiment of the present application, the bus driving unit 50 divides the data transmission link between the Master 1 and the Slave 2 in the I2C bus into a transmitting link and a receiving link, wherein the transmitting link is used for transmitting a transmitting signal (data signal) transmitted by the Master 1 to the Slave 2, the receiving link is used for transmitting a receiving signal (feedback signal) transmitted by the Slave 2 to the Master 1, the data signal (sda_master) transmitted by the Master 1 on the data line 3 is converted into (sda_master_tx) by the bus driving unit 50 and directly transmitted to the SDA interface of the Slave 2 on the transmitting link of the bus driving unit 50, and the feedback signal (sda_rx_slave) transmitted by the Slave 2 to the Master 1 is transmitted to the SDA interface of the Master 1 on the receiving link of the bus driving unit 50 after passing through the level monitoring unit 60 and the data correcting unit 70. The clock signal (scl_master) issued by the Master device 1 on the clock line 4 is sent directly to the SCL interface of the slave device 2 via said bus driving unit 50.
Wherein the level monitoring unit 60 outputs two signals (a first signal 61 and a second signal 62) based on the reception of a feedback signal (sda_rx_slave) from the device 2 to the main device 1, and then inputs the two signals into the data correction unit 70.
Wherein a data correction unit 70 is electrically connected to the bus driving unit 50 and the level monitoring unit 60, respectively, i.e. the data correction unit 70 is electrically connected between the bus driving unit 50 and the level monitoring unit 60, the data correction unit 70 outputs a corrected feedback signal (sda_slave_or) based on the received first signal 61 and second signal 62, and transmits the corrected feedback signal (sda_slave_or) to the master device 1 on a receiving link of the bus driving unit 50.
The embodiment of the application provides an I2C bus control circuit, wherein the I2C bus interface control circuit comprises: the system comprises a bus driving unit, a level monitoring unit and a data correction unit, wherein a data transmission link between a main device and a slave device is divided into a sending link and a receiving link through the bus driving unit, the level of a feedback signal sent from the slave device to the main device is monitored, the feedback signal sent from the slave device to the main device is subjected to data correction and then is transmitted to the main device on the receiving link of the bus driving unit, so that erroneous data acquisition caused by the reduction of the level of an I2C bus is avoided, and the safety and the reliability of the whole circuit system are ensured.
Further, the bus driving unit 50 amplifies the corrected feedback signal and transmits the amplified feedback signal to the host device 1.
Fig. 2 is a general block diagram of another I2C bus control circuit according to an embodiment of the present application. As shown in fig. 2, the control circuit 100 further includes an Alarm processing unit 80, where the Alarm processing unit 80 is electrically connected to the level monitoring unit 60 to receive the first signal 61 and the second signal 62, and generate an Alarm signal (I2C Alarm) based on the first signal 61 and the second signal 62 to trigger the upper computer 9 to implement an Alarm operation. If the level is abnormal, the level output by the alarm processing unit 80 will be inverted to feed back the health status of the current I2C bus data level transmission to the outside, and the upper computer 9 is used for receiving and displaying the abnormal status, and meanwhile, the corresponding alarm operation processing can be implemented through the operation interface of the upper computer 9, for example, the I2C bus circuit is cut off or the I2C bus chip is replaced in time.
Referring to fig. 4, the level monitoring unit 60 includes a first comparator 63 and a second comparator 64, each of the first comparator 63 and the second comparator 64 having a positive input terminal and a negative input terminal, and the positive input terminals of the first comparator 63 and the second comparator 64 being used for receiving the feedback signal (sda_rx_slave); the negative input end of the first comparator 63 is connected to an intermediate node after the third resistor R3 and the fourth resistor R4 are connected in series, and the third resistor R3 and the fourth resistor R4 are connected in series and then electrically connected between a power supply (VCC, D5V) and Ground (GND), so as to input the voltage divided by the third resistor R3 and the fourth resistor R4 to the negative input end of the first comparator 63; the negative input end of the second comparator 64 is connected to an intermediate node after the sixth resistor R6 and the seventh resistor R7 are connected in series, and the sixth resistor R6 and the seventh resistor R7 are connected in series and then electrically connected between a power supply (VCC, D5V) and Ground (GND), so as to input the voltage divided by the sixth resistor R6 and the seventh resistor R7 to the negative input end of the second comparator 64; wherein the output end of the first comparator 63 outputs the first signal 61, and the output end of the second comparator 64 outputs the second signal 62.
Illustratively, the voltage divided by the third resistor R3 and the fourth resistor R4 is VH, which is calculated according to the dividing resistance: the voltage value of VH isVCC is working voltage, the effective value is 5V, and the minimum effective value of VH is 4.3V through calculation; the voltage divided by the sixth resistor R6 and the seventh resistor R7 is VL, and is calculated according to the dividing resistance: electricity of VLThe pressure value is +.>Where VCC is the operating voltage and the effective value is 5V, the minimum effective value of VL is calculated to be 3.5V.
When the logic high level of the feedback signal (sda_rx_slave) output from the Slave device 2 to the master device 1 is between 4.7V and 5V, the communication on the I2C bus is maintained normal. When the chip performance of the Slave device 2 decreases, and the logic high level of the feedback signal (sda_rx_slave) output to the master device 1 decreases, the minimum value of the logic high level of the feedback signal that the master device 1 can receive is vcc×0.7=3.5v, so when the voltage value of the feedback signal (sda_rx_slave) is lower than the VH minimum effective value of the negative input terminal of the first comparator 63 by 4.3V, the output terminal of the first comparator 63 outputs an incorrect level, and at this time, the output terminal of the first comparator 63 outputs a low level signal to the data correction unit 70; and since the VL minimum effective value of the negative input terminal of the second comparator 64 is 3.5V, when the voltage value of the feedback signal (sda_rx_slave) output from the device 2 to the main device 1 is greater than the VL minimum effective value of the negative input terminal of the second comparator 64 by 3.5V, the waveform output from the output terminal of the second comparator 64 will be consistent with the logic high level of the feedback signal (sda_rx_slave) output from the device 2 to the main device 1, and at this time, the output terminal of the second comparator 64 will output a high level signal to the data correction unit 70.
With continued reference to fig. 4, the feedback signal (sda_rx_slave) output from the Slave device 2 to the master device 1 is also connected to the transmit signal (sda_slave_tx) on the transmit link of the bus driving unit 50, so as to be used for reference voltage comparison.
The level monitoring unit 60 further includes a first resistor R1, a second resistor R2, and a fifth resistor R5; the first end of the first resistor R1 is connected with a power supply, and the second end of the first resistor R1 is electrically connected with a data line for transmitting the feedback signal; a first end of the second resistor R2 is connected to a power supply, and a second end of the second resistor R2 is electrically connected to an output end of the first comparator 63 for outputting the first signal; a first end of the fifth resistor R5 is connected to a power source, and a second end of the fifth resistor R5 is electrically connected to an output end of the second comparator 64 for outputting the second signal. The first resistor R1, the second resistor R2 and the fifth resistor R5 are pull-up resistors, and because the data line transmission on the I2C bus is in an open collector or open drain structure, only "0" can be output, and "1" cannot be output, the pull-up resistors need to be connected with a power supply, so that when the data line on the I2C bus outputs a low level, the pull-up resistors will be in a working state all the time.
The I2C bus is divided into three ranges, i.e., a normal region (voltage range of 4.3V to 5V), an abnormal early warning region (voltage range of 3.5V to 4.3V), and a failure region (voltage range of 0 to 3.5V) according to the logic level range of the feedback signal (sda_rx_slave) output from the Slave device 2 to the master device 1. In these three ranges, the level results output from the output terminals of the first comparator 63 and the second comparator 64 are changed accordingly, and the results are shown in the following table one. Since the output terminal of the first comparator 63 and the output terminal of the second comparator 64 are electrically connected to the pull-up resistor R2 and the pull-up resistor R5, respectively, the output level thereof is 5V when the feedback signal is not input.
Table I, I2C bus feedback signal voltage range and judgment conclusion
With continued reference to fig. 5, the data correction unit 70 includes a logic OR gate 71, two input terminals of the logic OR gate 71 respectively receive the first signal 61 and the second signal 62, and an output terminal of the logic OR gate 71 outputs the corrected feedback signal (sda_slave_or).
Illustratively, the output first signal 61 (y_a) and the output second signal 62 (y_b) of the first comparator 63 and the second comparator 64 are input to two input terminals of the logic or gate 71, and if the logic high level of the feedback signal (sda_rx_slave) output from the device 2 to the main device 1 is in the range of 4.3V to 5V (in the normal area) and 3.5V to 4.3V (in the abnormal early warning area), the output result of the output terminal of the first comparator 63 and the output result of the output terminal of the second comparator 64 are both restored to the logic level of the feedback signal (sda_rx_slave) output from the device 2 to the main device 1 after the data correction by the data correction unit 70, that is, the output high level voltage value is 5V, and the data logic value and the level value of the input to the I2C main device are corrected to be correct values.
Referring to fig. 6, the alarm processing unit 80 includes a logic exclusive-or gate 81, two input terminals of the logic exclusive-or gate 81 respectively receive the first signal 61 and the second signal 62, and an output terminal of the logic exclusive-or gate 81 outputs the alarm signal.
Illustratively, outputs of the first and second comparators 63 and 64 are first and second signals 61 (Y_A) and 64
The two signals 62 (Y_B) are input to two input terminals of the logical exclusive OR gate 81 according to the exclusive OR formulaWhen the output level of the first comparator 63 is different from the output level of the second comparator 64, the alarm signal output by the output end of the logic exclusive-or gate 81 has a logic "1" level, and the upper computer 9 can determine that the output data level of the data line of the I2C slave device is abnormal by monitoring the logic level of the alarm signal, so as to achieve the purpose of alarm.
Further, the values of the first signal 61 and the second signal 62 reflect the logic level and the voltage range of the feedback signal (sda_rx_slave) sent from the Slave device 2 to the master device 1, where please continue to refer to table one, the voltage range includes a normal area, an abnormal early warning area, and a failure area.
Further, under the condition that the logic level of the alarm signal is 1, the alarm signal triggers the upper computer 9 to alarm, and under the condition that the logic level of the alarm signal is 0, the alarm signal does not trigger the upper computer 9 to alarm.
By adopting the I2C bus control circuit provided by the embodiment of the application, not only the level on the I2C bus can be monitored in real time, but also the current level output range can be corrected in time when the level on the I2C bus is reduced due to the abnormality of the I2C chip, and the alarm processing unit 80 is triggered to send an alarm signal to remind a user to replace or maintain equipment, so that the erroneous data acquisition caused by the performance reduction of the chip is avoided, and the safety and reliability of the whole circuit system are improved.
Fig. 7 and 8 are schematic diagrams of simulation of abnormality of the voltage value of the data level of the slave device, respectively. As shown in fig. 7 and 8, the I2C bus control circuit simulating 100KHz frequency transmits square waves of 0-4V peak-to-peak, the reference voltages of the first comparator 63 and the second comparator 64 are 4.3V (VH) and 3.5V (VL), respectively, the waveform of blue in the oscilloscope in fig. 7 is the level anomaly data simulating the output from the device 2, the waveform of yellow is the low level of 0V after passing through the first comparator 63, the waveform of red is the square wave after passing through the second comparator 64, and the waveform of green is the square wave after being corrected by the data correction unit 70. The red waveform in the oscilloscope of fig. 8 is a waveform after passing through the alarm processing unit 90, and when the oscilloscope of fig. 8 appears in the red waveform, it indicates that there is a level abnormality alarm.
The embodiment of the application also provides a circuit system for a ship, which comprises the I2C bus control circuit in the embodiment.
As can be seen from the above, the I2C bus control circuit and the circuit system for a ship according to the embodiments of the present application, wherein the I2C bus interface control circuit includes: the system comprises a bus driving unit, a level monitoring unit and a data correction unit, wherein a data transmission link between a main device and a slave device is divided into a sending link and a receiving link through the bus driving unit, the level of a feedback signal sent from the slave device to the main device is monitored, the feedback signal sent from the slave device to the main device is subjected to data correction and then is transmitted to the main device on the receiving link of the bus driving unit, so that erroneous data acquisition caused by the reduction of the level of an I2C bus is avoided, and the safety and the reliability of the whole circuit system are ensured.
The foregoing description of the preferred embodiments of the present application is not intended to limit the scope of the application, but rather to cover all equivalent variations and modifications in shape, construction, characteristics and spirit according to the scope of the present application as defined in the appended claims.
Claims (10)
1. An I2C bus control circuit, comprising:
the bus driving unit is connected to an I2C bus between a master device and a slave device, and the master device and the slave device communicate through the I2C bus, wherein the bus driving unit directly sends a data signal output by the master device to the slave device through a data line of the I2C bus and directly sends a clock signal output by the master device to the slave device through a clock line of the I2C bus;
the level monitoring unit is electrically connected with the data line of the I2C bus, so as to receive a feedback signal sent by the slave device to the master device, and output a first signal and a second signal based on the feedback signal, wherein the first signal and the second signal reflect the feedback signal and the voltage range thereof, and the level monitoring unit is used for receiving the feedback signal through a first comparator and a second comparator and comparing the feedback signal with a reference voltage to realize level monitoring;
the data correction unit is respectively and electrically connected with the bus driving unit and the level monitoring unit to receive the first signal and the second signal, generate a corrected feedback signal based on the first signal and the second signal, and send the corrected feedback signal to the main device through the bus driving unit, wherein the data correction unit is used for respectively receiving the first signal and the second signal through two input ends of a logic OR gate to realize signal correction.
2. The I2C bus control circuit of claim 1, wherein the bus driver unit augments the corrected feedback signal and sends the augmented feedback signal to the master device.
3. The I2C bus control circuit of claim 2, further comprising an alarm processing unit electrically coupled to the level monitoring unit to receive the first signal and the second signal and generate an alarm signal based on the first signal and the second signal to trigger the host computer to perform an alarm operation.
4. The I2C bus control circuit of any of claims 1-3, wherein the level monitoring unit comprises a first comparator and a second comparator, each having a positive input and a negative input, and wherein the positive inputs of the first comparator and the second comparator are each for receiving the feedback signal;
the negative input end of the first comparator is connected to an intermediate node after a third resistor and a fourth resistor are connected in series, and the third resistor and the fourth resistor are connected in series and then electrically connected between a power supply and ground so as to input voltage divided by the third resistor and the fourth resistor to the negative input end of the first comparator;
the negative input end of the second comparator is connected to an intermediate node after the sixth resistor and the seventh resistor are connected in series, and the sixth resistor and the seventh resistor are connected in series and then electrically connected between a power supply and the ground so as to input the voltage divided by the sixth resistor and the seventh resistor to the negative input end of the second comparator;
the output end of the first comparator outputs the first signal, and the output end of the second comparator outputs the second signal.
5. The I2C bus control circuit of claim 4 wherein,
the level monitoring unit further comprises a first resistor, a second resistor and a fifth resistor;
the first end of the first resistor is connected with a power supply, and the second end of the first resistor is electrically connected with a data line for transmitting the feedback signal;
the first end of the second resistor is connected with a power supply, and the second end of the second resistor is electrically connected with the output end of the first comparator for outputting the first signal;
the first end of the fifth resistor is connected with a power supply, and the second end of the fifth resistor is electrically connected with the output end of the second comparator for outputting the second signal.
6. The I2C bus control circuit of claim 5 wherein,
the data correction unit comprises a logic or gate, two input ends of the logic or gate respectively receive the first signal and the second signal, and an output end of the logic or gate outputs the corrected feedback signal.
7. The I2C bus control circuit of claim 6, wherein the alarm processing unit comprises a logic exclusive-or gate, two input terminals of the logic exclusive-or gate respectively receiving the first signal and the second signal, and an output terminal of the logic exclusive-or gate outputting the alarm signal.
8. The I2C bus control circuit of claim 7 wherein,
the values of the first signal and the second signal reflect the voltage range of the feedback signal, wherein the voltage range comprises a normal area, an abnormal early warning area and a failure area.
9. The I2C bus control circuit of claim 8, wherein the alarm signal triggers an upper computer alarm if the logic level of the alarm signal is "1", and the alarm signal does not trigger an upper computer alarm if the logic level of the alarm signal is "0".
10. A circuit system for a marine vessel, characterized in that the circuit system comprises an I2C bus control circuit according to any of claims 1-9.
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