CN109739790B

CN109739790B - General input/output interface module

Info

Publication number: CN109739790B
Application number: CN201811515490.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Zhuhai Eeasy Electronic Tech Co ltd
Current assignee: Zhuhai Eeasy Electronic Tech Co ltd
Priority date: 2018-12-12
Filing date: 2018-12-12
Publication date: 2020-07-14
Anticipated expiration: 2038-12-12
Also published as: CN109739790A

Abstract

The invention discloses a general input/output interface module, which comprises a general input module GPI, a general output module GPO and an anti-static module ESD, wherein the output end of the general output module GPO is connected with a pin processing module IO pad through the anti-static module ESD, the connection node of the general output module and the anti-static module ESD is a node A, the input end of the general input module GPI is connected with the node A, the general input interface module further comprises a high-resistance state driving module and a high-resistance state detection module which are connected together, and the output end of the high-resistance state driving module and the input end of the high-resistance state detection module are respectively connected with the node A. The invention drives and detects the state of the interface through the built-in high-resistance state driving module and the high-resistance state detecting module respectively, thereby obtaining the information whether the interface is in the high-resistance state, and the invention can identify 3 different states of the GPIO module: logic 1, logic 0 and high impedance state, thereby greatly reducing the development difficulty of the system scheme.

Description

General input/output interface module

Technical Field

The invention relates to the technical field of interface circuits, in particular to a universal input/output interface module.

Background

A General Purpose Input/Output module (GPIO) is an essential module in a System On Chip (SOC) and is a "bridge" for internal circuits to communicate with the outside world. Referring to fig. 1, a general GPIO includes two sub-functions: general Purpose input GPI (general Purpose input) and general Purpose output GPO (general Purpose output). Generally, GPIO does not process signal logic, but simply applies appropriate driving to logic received from an internal circuit to transmit the logic, i.e., a function of general-purpose output, or converts received electrical signals into appropriate logic to transmit the logic to the internal circuit, i.e., a function of general-purpose input.

In modern large-scale integrated circuit design and packaging processes, along with the progress of integrated circuit manufacturing processes, the SOC is larger and larger in scale, more and more in functions, the speed and the number of interfaces are improved in multiples, and the system scheme is more flexible. GPIO is the most basic general purpose interface, and the physical layer of the wired communication protocol of a plurality of low-speed or medium-speed interfaces is realized by relying on GPIO. For a general GPIO, the interface voltage is high or low to represent a logic state of 1bit, usually the voltage is greater than Vih to represent a logic 1, and the voltage is less than Vil to represent a logic 0, and when the interface voltage value Vpad is between Vih and Vil, i.e., Vil < Vpad < Vih, for a GPIO that is an abnormal input state, a system error may be caused and needs to be avoided. General GPIO can only distinguish logic 1 and logic 0, and the interface is in the high resistance state, and the voltage on it receives the influence of multiple factors such as electric leakage, thermal noise, interference coupling, can make the voltage fall into between Vih and Vil, easily causes the mistake. To put it back, even if the GPI function recognizes this high impedance state as a logic 0 or a logic 1, it is necessary in practice to avoid such misleading situations. It is therefore generally necessary to connect unused input and output terminals to power or ground in a substrate design or pcb design to avoid internal circuitry identifying high impedance states as undesirable logic, which greatly increases the complexity of the solution application.

For general GPIOs, one way to prevent this is to avoid high impedance states at the interface. It is common practice to incorporate a weak driver circuit to pull the interface voltage down to ground or up to the power supply. This approach can completely avoid the effects of the high resistance state, but still has two problems: 1) the high-resistance state cannot be detected, namely whether the interface is driven by the GPO and the external equipment cannot be distinguished; 2) certain static power consumption exists during normal operation.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a general input/output interface module which is used for solving the problem that the prior art cannot detect the high impedance state of a GPIO module.

The invention comprises the following contents:

the utility model provides a general input/output interface module, including general input module GPI, general output module GPO and prevent static module ESD, general output module GPO's output is connected with pin processing module IO pad through preventing static module ESD, general output module is node A with the connected node of preventing static module ESD, general input module GPI's input is connected with node A, still including high resistance state drive module and the high resistance state detection module that link together, high resistance state drive module's output and high resistance state detection module's input are connected with node A respectively.

Preferably, the high resistance state driving module comprises a code pattern generator, an intensity adjusting module and a delay control module, the output end of the code pattern generator is connected with the intensity adjusting module, the output end of the intensity adjusting module is connected with the anti-static module ESD, the intensity adjusting module is further connected with the high resistance state detection module through the delay control module, the code pattern generator is used for generating a code pattern, the code pattern is transmitted to the intensity adjusting module, the intensity adjusting module is used for adjusting the driving intensity, and the delay control module is used for realizing code pattern delay.

Preferably, the high-resistance state detection module comprises an exclusive or operation unit and a state control unit, wherein the input end of the exclusive or operation unit is respectively connected with the high-resistance state driving module and the node a, the output end of the exclusive or operation unit is connected with the state control unit, and the state control unit is used for realizing time sequence adjustment, filtering and amplification of signals.

Preferably, the state control unit comprises a time sequence adjusting unit, a filtering unit and a driving unit which are connected in sequence, wherein the input end of the time sequence adjusting unit is connected with the exclusive or operation unit, the time sequence adjusting unit is used for adjusting the time sequence of the signal, the filtering unit is used for filtering an interference signal, and the driving unit is used for amplifying the effective signal.

The invention has the beneficial effects that: the invention drives and detects the state of the interface through the built-in high-resistance state driving module and the high-resistance state detecting module respectively, thereby obtaining the information whether the interface is in the high-resistance state, and the invention can identify 3 different states of the GPIO module: logic 1, logic 0 and high impedance state, thereby greatly reducing the development difficulty of the system scheme.

Drawings

FIG. 1 is a schematic block diagram of a prior art GPIO module;

fig. 2 is a schematic block diagram 1 of a GPIO module according to an embodiment of the present invention;

fig. 3 is a schematic block diagram 2 of a GPIO module according to an embodiment of the present invention.

Detailed Description

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Referring to fig. 2, the present embodiment discloses a general purpose input/output interface module, which includes a general purpose input module GPI, general output module GPO and prevent static module ESD, general output module GPO's output is connected with pin processing module IO pad through preventing static module ESD, general output module is node A with the connected node of preventing static module ESD, general input module GPI's input is connected with node A, general input module GPI's output and enable end are connected with internal circuit 4 respectively, general output module GPO's input is connected with internal circuit 4, the GPIO module still includes high resistance state drive module 5 and high resistance state detection module 6 that link together, high resistance state drive module 5's output and high resistance state detection module 6's input are connected with node A respectively, high resistance state drive module 5's input and high resistance state detection module 6's output are connected with internal circuit 4 respectively.

When the circuit works normally, if the pin processing module IO pad has a voltage level from the general purpose output module GPO or an external driver (generally, a voltage level greater than Vih or a voltage level less than Vil), the general purpose input module GPI will recognize the pin processing module IO pad as a desired logic level and send the logic level to the internal circuit 4; when the pin processing module IO pad does not receive a drive from an internal GPO or an external drive, the high resistance state driving module 5 may drive the pin processing module IO pad with a weaker strength and a specific code pattern, the high resistance state detecting module 6 may detect a signal from the pin processing module IO pad, and compare the signal from the pin processing module IO pad with the specific code pattern from the high resistance state driving module 5 by using the xor operation unit 6-2 and other auxiliary circuits, if the signal from the pin processing module IO pad is consistent with the specific code pattern from the high resistance state driving module 5, it indicates that the pin processing module IO pad is in a high resistance state, and if the signal from the pin processing module IO pad is inconsistent with the specific code pattern from the general output module GPO or the external drive, it indicates that the pin processing module IO pad has the drive.

Referring to fig. 2, the general purpose input module GPI includes a schmitt input detection module 2-1, an input end of the schmitt input detection module 2-1 is connected to the node a, an output end and a control end of the schmitt input detection module 2-1 are respectively connected to the internal circuit 4, the general purpose output module GPO includes an output control module 1-1, a pull-up driving MOS transistor 1-2 and a pull-down driving MOS transistor 1-3, a base of the pull-up driving MOS transistor 1-2 and a base of the pull-down driving MOS transistor 1-3 are respectively connected to an output end of the general purpose output module GPO, and a drain of the pull-up driving MOS transistor 1-2 and a drain of the pull-down driving MOS transistor 1-3 are connected to the node a.

The high-resistance state driving module 5 comprises a code type generator 5-1, a strength adjusting module 5-2 and a delay control module 5-3, the input end of the code type generator 5-1 is connected with an internal circuit 4, the output end of the code type generator 5-1 is connected with the strength adjusting module 5-2, the output end of the strength adjusting module 5-2 is connected with an anti-static module ESD, the strength adjusting module 5-2 is also connected with a high-resistance state detection module 6 through the delay control module 5-3, the code type generator 5-1 is used for receiving an enabling signal or a control signal from the internal circuit 4, generating a code type and transmitting the code type to the strength adjusting module 5-2, the control signal comprises a code type control model, a strength control signal and a delay control signal, and the strength adjusting module 5-2 is used for adjusting driving strength, and the delay control module 5-3 is used for realizing code type delay.

Referring to fig. 3, the high impedance state detection module 6 includes an exclusive or operation unit 6-2 and a state control unit 6-1, an input end of the exclusive or operation unit 6-2 is connected to the high impedance state driving module 5 and the node a, an output end of the exclusive or operation unit 6-2 is connected to the state control unit 6-1, and the state control unit 6-1 is configured to implement timing adjustment, filtering, and amplification of a signal.

The state control unit 6-1 comprises a time sequence adjusting unit, a filtering unit and a driving unit which are sequentially connected, wherein the input end of the time sequence adjusting unit is connected with the exclusive-or operation unit 6-2, the output end of the driving unit is connected with the internal circuit 4, the time sequence adjusting unit is used for adjusting the time sequence of signals, the filtering unit is used for filtering interference signals, and the driving unit is used for amplifying effective signals.

When the pin processing module IO pad is not driven from the internal GPO or the external driver, the high resistance state driving module 5 may drive the pin processing module IO pad with a weaker strength and a specific code pattern: firstly, a specific code pattern is generated by a code pattern generator 5-1 and is sent to a pin processing module IO pad through an intensity adjusting unit, so that a high-resistance state driving module 5 can send signals to the pin processing module IO pad with specific intensity and code pattern, and meanwhile, the specific code pattern with certain delay is sent to a high-resistance state detection module 6 through a delay control unit; the high-resistance state detection module 6 receives signals from the pin processing module IO pad and the high-resistance state driving module 5, compares the signals with the xor operation unit 6-2, and sends the comparison result to the internal circuit 4 as a high-resistance state indicating bit after certain state control.

Compared with a conventional GPIO module, the state of the pin processing module IO pad is respectively driven and detected by the built-in high-resistance state driving module 5 and the high-resistance state detecting module 6, so that the information whether the interface is in the high-resistance state is obtained, and the situation that an unused input/output terminal is connected to a power supply or the ground when a substrate is designed or a pcb is designed is avoided, so that the development difficulty of a system scheme is greatly reduced.

The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and the present invention shall fall within the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.

Claims

1. The utility model provides a general input/output interface module, includes general input module GPI, general output module GPO and prevents static module ESD, and general output module GPO's output is connected with pin processing module IO pad through preventing static module ESD, and general output module is node A with the connected node of preventing static module ESD, and general input module GPI's input is connected its characterized in that with node A: the high-resistance state detection device is characterized by further comprising a high-resistance state driving module (5) and a high-resistance state detection module (6) which are connected together, wherein the output end of the high-resistance state driving module (5) and the input end of the high-resistance state detection module (6) are respectively connected with a node A, the high-resistance state driving module (5) comprises a code pattern generator (5-1), the high-resistance state detection module (6) comprises an exclusive OR operation unit (6-2) and a state control unit (6-1), the input end of the exclusive OR operation unit (6-2) is respectively connected with the high-resistance state driving module (5) and the node A, the output end of the exclusive OR operation unit (6-2) is connected with the state control unit (6-1), and the state control unit (6-1) is used for achieving time sequence adjustment, filtering and.

2. The gpio interface module of claim 1, wherein: the high-resistance state driving module (5) further comprises a strength adjusting module (5-2) and a time delay control module (5-3), the output end of the code pattern generator (5-1) is connected with the strength adjusting module (5-2), the output end of the strength adjusting module (5-2) is connected with the anti-static module ESD, the strength adjusting module (5-2) is further connected with the high-resistance state detecting module (6) through the time delay control module (5-3), the code pattern generator (5-1) is used for generating code patterns and transmitting the code patterns to the strength adjusting module (5-2), the strength adjusting module (5-2) is used for adjusting driving strength, and the time delay control module (5-3) is used for achieving code pattern time delay.

3. The gpio interface module of claim 1, wherein: the state control unit (6-1) comprises a time sequence adjusting unit, a filtering unit and a driving unit which are sequentially connected, the input end of the time sequence adjusting unit is connected with the exclusive-or operation unit (6-2), the time sequence adjusting unit is used for adjusting the time sequence of signals, the filtering unit is used for filtering interference signals, and the driving unit is used for amplifying effective signals.