KR20090004508A - Pci express interface apparatus - Google Patents

Abstract

A PCI(Peripheral Component Interconnection) express interface apparatus is provided to have USB interface standard and compatibility which are prevalently used and to support PCle interface standard of high data transmission rate. A power terminal and a grounding terminal of interface follows a standard of USB interface. The positions of two terminals among 4 data terminals are overlapped with the position of not D-terminal but D+terminal of standard USB interface. The positions of the rest two terminal among the 4 data terminals are overlapped with the position of D-terminal of standard USB interface but are not overlapped with the position of D+terminal of standard USB interface.

Description

High speed peripheral interface device {PCI express interface apparatus}

The present invention relates to data interfaces for accessing peripherals and personal computers, and more particularly, to Peripheral Component Interconnect Express (PCI Express) interfaces.

Universal Serial Bus (USB) is a common interface standard for accessing peripherals and personal computers. In recent years, the application of USB has already been extended to mass consumer electronics and mobile devices. Currently, the USB 2.0 standard interface is being applied in large quantities. Since the maximum speed of the USB 2.0 interface is 480Mb / S and power can be provided, the USB2.0 interface is very popular in the field of PC interface. high. But as storage and Internet speeds enter G (Giga) generations, data connections between PCs and peripherals demand higher transfer rates, so USB2.0 does not meet the demand for ever-increasing access speeds. As a result, there is an urgent need to use new interface specifications for data connections between PCs and peripherals.

One solution is to use an eSATA (e Serial Advanced Technology Attachment) interface to withdraw the SATA interface from the computer case. These interfaces can support 3Gb / S bandwidth. However, because it does not provide a power signal, it cannot power the device, and because it only supports simple storage, many consumer electronics cannot connect to a computer using this interface. In addition, the above method has a disadvantage that is incompatible with many conventional USB devices.

Another solution is the ExpressCard interface, which is widely used in notebooks. This interface is capable of supporting data rates of 3Gb / S. The ExpressCard interface can power storage devices and support PCI Express (Express) interfaces and USB interfaces simultaneously. The PCI Express interface is sometimes abbreviated as PCIe interface. The PCI Express interface continues to adopt the conventional PCI communication standard, but is based on a faster serial communication system. The ExpressCard interface is divided into two types, ExpressCard | 34 and ExpressCard | 54, and its appearance is as shown in Figs. 1A and 1B, respectively. As can be seen from the figure, the relatively small ExpressCard | 34 interface also has a relatively large outline size 75x4 mm. In addition, these interfaces support USB devices, but the USB device's interface can only achieve this support using the ExpressCard interface specification, and traditional USB devices do not support them, making them incompatible with the vast majority of USB interface peripherals.

Accordingly, a main object of the present invention is to provide a data interface device for accessing a peripheral device and a personal computer, which is compatible with the widely used USB interface standard and can support the PCIe interface specification of a high data rate. .

Technical solutions for realizing the object of the present invention are as follows.

In a high speed peripheral connection interface having a power terminal, a ground terminal, and four data terminals including two data transmission terminals and two data reception terminals,

The power terminal and the ground terminal of the interface match the corresponding terminals in the USB interface standard,

Of the four data terminals, the position and width of two terminals overlap with the position of the D + terminal in the USB interface standard and do not overlap with the position of the D- terminal in the USB interface standard,

High speed peripheral device characterized in that the position and width of the remaining two terminals of the four data terminals overlap the position of the D-terminal in the USB interface standard and does not overlap the position of the D + terminal in the USB interface standard. Provide a connection interface.

According to a preferred embodiment of the present invention, in the correspondence relationship between the positions of the four data terminals of the interface and the position of the USB interface terminal, the PT-terminal and the PR + terminal correspond to the D + terminal of the USB interface and the PT + terminal and the PR It is preferable that the terminal corresponds to the D terminal of the USB interface.

According to a preferred embodiment of the present invention, it is preferable that the interface further comprises an interface detecting unit for detecting an interface type suitable for the interface and controlling an output of an interface permission signal corresponding to the detected interface type.

According to a preferred embodiment of the invention, it is preferred that the interface detection unit is integrated in the southbridge of the computer.

According to a preferred embodiment of the present invention, it is preferable that the interface detection unit is integrated in a custom semiconductor.

According to a preferred embodiment of the present invention, the interface detecting unit includes a signal transmitting module, a signal comparing module and a switching control module, wherein the signal transmitting module is connected to the signal comparing module and the signal comparing module is connected to the switching control module. It is preferable that the output signal is compared with the input signal received from the interface input terminal, the comparison result is transmitted to the switching control module, and the switching control module controls the output of different interface permission signals.

The PCIe interface device compatible with the USB interface according to the present invention can provide a data rate of 3Gb / S according to the PCIe interface standard and can support a conventional USB peripheral device without device change.

According to the present invention, it is possible to automatically detect whether a peripheral device is a device conforming to the PCIe interface standard or a USB interface standard, and provide a transmission protocol suitable for the two different types of devices, respectively.

In addition, since the external appearance of the interface according to the present invention is completely the same as the conventional USB interface, the size is small, and the peripheral device using the interface has advantages of being portable and easy to use.

The present invention will be described in more detail by combining the drawings and specific embodiments below.

The PCIe interface, which is compatible with the universal serial bus interface according to the present invention, supports not only various existing USB interface devices but also supports the PCIe interface specification of a high data rate. For convenience of explanation, the Plug of the PCIe interface standard compatible with the USB interface according to the present invention will be abbreviated as a new plug below, and the socket of the PCIe interface standard compatible with the USB interface according to the present invention. Is abbreviated as a new socket.

In order to be compatible with the conventional USB interface, the connection terminal of the interface according to the present invention adopts the structure shown in FIG. The D + and D- terminals of the USB interface are divided into two parts, and four data terminals are used to output PCIe signals. The four data terminals correspond to PT +, PT-, PR + and PR-, respectively, and there is no change in the definition of the other terminals of the USB interface. The data terminal division method is not limited to one as shown in the drawing. For example, split D + on the USB interface into PT + and PR- and split D- into PT- and PR +, split D + into PT + and PT- and D- into PR + and PR-, or else The division method can also be used. In the preferred embodiment of the present invention shown in FIG. 2, it can be seen that D + of the USB interface is divided into PT + and PR-, and D- is divided into PT- and PR +.

In addition, in this division, the PT + terminal and the PR- terminal do not necessarily correspond to the width of the D + terminal of the USB interface, or the PT-terminal and the PR + terminal do not necessarily correspond to the width of the D- terminal of the USB interface. In fact, the power and ground terminals of the interface match the corresponding terminals in the USB interface standard, and the position and width of two of the four data terminals overlap with the position of the D + terminal in the USB interface standard. It can be ensured that it does not overlap with the location of the D-terminal in the USB interface specification. In addition, it is necessary to ensure that the positions and widths of the remaining two terminals overlap with the position of the D-terminal in the USB interface specification and not overlap with the position of the D + terminal in the USB interface specification.

PT-terminal and PR + terminal, PT + terminal, and PR-terminal in PCIe interface compatible with USB interface do not use the parallel arrangement as shown in FIG. The D-terminal in the USB interface may be in contact with the D + terminal. The PT + and PR-terminals may be arranged in other ways, provided they ensure a corresponding correspondence.

Part A of FIG. 2 shows the correspondence relationship between the conventional USB socket and the traditional USB plug. When introducing a PCIe interface compatible with the USB interface according to the present invention, a variety of various custom relationships are possible. That is, a new socket fits into a traditional USB plug, a new socket fits into a new plug, or a traditional USB socket fits into a new socket. These various fitting relationships are as shown in parts B, C and D in FIG.

As shown in part B of FIG. 2, when the conventional USB plug is inserted into a new socket, the widths of the D + and D- terminals of the conventional USB plug are wider than the respective widths of PT +, PT-, PR + and PR- of the new socket. Therefore, the PT + and PR- terminals of the new socket are shorted by the D + terminal of the USB interface, and the PT- and PR + terminals of the new socket are shorted by the D- terminal of the USB interface. If the detection device detects a short between PT- and PR +, PT + and PR- of the new socket, you will see that a traditional USB plug has been inserted into the new socket. On the other hand, as can be seen from the portion C of Fig. 2, when the new plug is inserted into the new socket, both PCIe terminals correspond one-to-one, so that the PCIe interface standard of high data rate can be used.

In order to identify the adaptability of the interface, the side providing the new socket must provide the interface detection unit as a PC. The interface detection unit is connected to the input terminals PR + and PR- of the PCIe interface, and provides a USB output enable signal line and a PCIe output enable signal line, and according to the USB data line and the PCIe data line of the PC according to the USB interface protocol. The signal is transmitted to the D + and D-terminals of the USB interface, and is actually transmitted simultaneously from the PT + and PR-terminals, the PT- and the PR + terminals, and is transmitted to the PT + and PT-terminals of the PCIe interface by the PCIe interface protocol. The interface detecting unit detects whether the PT + and PR + terminals of the new socket are shorted, and also detects whether the PT- and PR + terminals of the new socket are shorted. If a short circuit relationship is detected between the terminals, it is recognized that a traditional USB device has been inserted into the new socket, and the new socket side communicates with the USB plug side by the USB interface protocol and transmits data. If the interface detecting unit does not detect the above short-circuit relationship, it is determined that a new plug is inserted into the new socket, and the new socket side communicates with the new plug side by the PCIe interface protocol and transmits data.

As shown in FIG. 3, the interface detection unit is integrated in a south bridge of a computer to perform a short circuit detection function in the south bridge, and after completion of detection, a USB output permission signal or PCIe according to the short circuit detection result. It can send output enable signal and communicate with PC and peripheral device by using corresponding transmission interface protocol according to PC's USB data line or PCIe data line.

In addition, as illustrated in FIG. 4, the interface detection unit may be implemented as an application-specific integrated circuit (ASIC). The on-demand semiconductor is connected to the USB data pin and PCIe transmit and receive pins of the PC's PCIe slot to perform short-circuit detection inside the on-demand semiconductor. After performing the detection function, the interface detection unit transmits the USB output enable signal or the PCIe output enable signal according to the short circuit detection result, and uses the corresponding transmission interface protocol in accordance with the USB data line or the PCIe data line of the PC and the peripherals with the PC. Proceed with communication and data transfer between devices.

The detection method of the interface is various, for example, the interface detection unit directly transmits one high or low level to the PT + or PT- terminal and then detects the level of the PR- or PR + terminal to detect whether there is a short circuit between the two sets of terminals. Can be detected.

The interface detection unit according to an embodiment of the present invention, as shown in Figure 5, includes a signal transmission module, a signal comparison module and a switching control module, where the signal transmission module is connected to the signal comparison module PCIe output terminal PT + Or transmits one output signal conforming to the PCIe protocol to PT- and provides the output signal to the signal comparison unit. The signal comparison module is connected to the PCIe input terminals PR- or PR + to obtain input signals from the two terminals. The signal comparison module is also connected to the switching control module to compare the output signal with the input signal received from the PR- or PR + and transmit the comparison result to the switching control module. The changeover control module controls the output of the different interface permission signals. Here, the interface permission signal includes a USB output permission signal and a PCIe output permission signal.

6 illustrates a more specific embodiment. The signal transmission module is realized as a waveform generator, the signal comparison module is realized as an XOR gate circuit and a pulse counter, and the switching control module is realized as an OR gate circuit and a NOT gate circuit. In order to detect whether the inserted plug is a USB plug or a new plug, the waveform generator transmits a set of predetermined output waveform signals, which are also simultaneously transmitted to the XOR gate circuit. When the USB device is inserted, since the PCIe output terminal and the input terminal of the slot are shorted, the output waveform signal to be transmitted is directly transmitted to the XOR gate circuit by the shorted PCIe input terminals PR + and PR-.

The XOR gate circuit compares the output waveform signal with the input signal received at the input terminal. If the two signals are identical, it means that PT- and PR +, PT + and PR- of PCIe are shorted, and always outputs 0. If the two signals are different, it means that PT- and PR +, PT + and PR- of PCIe are not shorted. Output the pulse waveform. The pulse counter counts pulses on this waveform. If the count result is zero, the counter output is zero; otherwise, the counter output is greater than zero. The OR gate circuit performs an OR operation on the output of the pulse counter. If it is 0, 0 is output and 1 is output through the NOT gate circuit. At this time, a USB output permission signal is transmitted. If the output of the pulse counter is greater than zero, the OR gate circuit computes one and a PCIe output enable signal is transmitted.

Referring to part D in FIG. 2, when a new plug is inserted into a conventional USB slot, the device on the new plug side includes the interface detecting unit and the control circuit, and the device simultaneously supports the USB interface protocol and the PCIe interface protocol. As long as it can support, the device with the new plug can select whether to transmit data using the USB interface protocol method or the PCIe interface protocol method.

The foregoing descriptions merely describe preferred embodiments of the present invention, and do not limit the protection scope of the present invention. The PCIe interface having various correspondences between the data terminal of the PCIe interface and the data terminal of the USB interface, the PCIe interface composed of data terminals of different shape characteristics, and the interface detection unit of different internal configuration are also included within the protection scope of the present invention. Those skilled in the art will be able to easily think of it.

1A is an external view of an ExpressCard | 34 interface standard according to the prior art,

1B is an external view of an ExpressCard | 54 interface standard according to the prior art,

2 illustrates various customizable cases of a PCIe interface compatible with a USB interface according to the present invention,

3 is a schematic diagram of an embodiment of a PCIe interface compatible with the USB interface according to the present invention,

4 is a functional block diagram of an interface detection unit of the PCIe interface compatible with the USB interface according to the present invention,

5 and 6 illustrate one embodiment of an interface detection unit of a PCIe interface that is compatible with the USB interface according to the present invention.

Claims (6)

In a high speed peripheral connection interface having a power terminal, a ground terminal, and four data terminals including two data transmission terminals and two data reception terminals,  The power terminal and the ground terminal of the interface match the corresponding terminals in the USB interface standard,  Of the four data terminals, the position and width of two terminals overlap with the position of the D + terminal in the USB interface standard and do not overlap with the position of the D- terminal in the USB interface standard,  The positions and widths of the other two terminals of the four data terminals overlap with the position of the D + terminal in the USB interface standard, and do not overlap with the position of the D- terminal in the USB interface standard,  High-speed peripheral device characterized in that the position and width of the remaining two terminals of the four data terminals overlap the position of the D-terminal in the USB interface standard and does not overlap the position of the D + terminal in the USB interface standard Connection interface device. The method of claim 1, In the correspondence relationship between the positions of the four data terminals of the interface and the position of the USB interface terminal, the PT- terminal and the PR + terminal correspond to the D + terminal of the USB interface, and the PT + terminal and the PR- terminal are the D- terminal of the USB interface. A high speed peripheral device connection interface device, characterized in that corresponding to the terminal. The method according to claim 1 or 2, The interface, And an interface detecting unit for detecting an interface type corresponding to the interface and controlling an output of an interface permission signal corresponding to the detected interface type. The method of claim 3, And the interface detection unit is integrated in the southbridge of the computer. The method of claim 3, And the interface detection unit is integrated into a custom semiconductor. The method of claim 3, The interface detection unit includes a signal transmission module, a signal comparison module and a switching control module, The signal transmission module is connected to the signal comparison module to provide an output signal to the signal comparison module and the interface output terminal. The signal comparison module is connected to the switching control module to compare the output signal with the input signal received from the interface input terminal and transmit the comparison result to the switching control module,  The switching control module is a high-speed peripheral connection interface device, characterized in that for controlling the output of the different interface permission signal.

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