TWI246801B - Virtual USB flash memory storage device with a PCI express bus - Google Patents

Virtual USB flash memory storage device with a PCI express bus Download PDF

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Publication number
TWI246801B
TWI246801B TW94101041A TW94101041A TWI246801B TW I246801 B TWI246801 B TW I246801B TW 94101041 A TW94101041 A TW 94101041A TW 94101041 A TW94101041 A TW 94101041A TW I246801 B TWI246801 B TW I246801B
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Taiwan
Prior art keywords
interface
flash memory
storage device
bus
universal serial
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TW94101041A
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Chinese (zh)
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TW200625727A (en
Inventor
Kian-Leng Lee
Wee-Kuan Gan
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Phison Electronics Corp
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Priority to TW94101041A priority Critical patent/TWI246801B/en
Priority to MYPI20054483A priority patent/MY164803A/en
Priority to JP2005289633A priority patent/JP4509906B2/en
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Publication of TWI246801B publication Critical patent/TWI246801B/en
Publication of TW200625727A publication Critical patent/TW200625727A/en

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Abstract

A virtual USB flash memory storage device with a PCI express bus is disclosed. There is a micro controller in the storage device. The micro controller is connected to the flash memory and the interface connector of the PCI express bus, respectively. The micro controller has a flash memory interface, a PCI express bus interface, and a virtual USB interface module. The virtual USB interface module comprises a virtual control terminal and a virtual device terminal of the USB interface. When a computer host issues a USB interface command through its PCI express bus to store/read the information in the storage device, the command is transmitted to the virtual USB interface module and is processed in the virtual USB interface module. The data processing operation for the stored/read information is processed in the flash memory via the flash memory interface. The information in the storage device is transmitted at a speed as high as the transmission speed of the PCI express bus, so the computer host looks the storage device as a USB interface device but not simply a PCI express bus interface device.

Description

1246801 五、發明說明(1) 【發明所屬之技術領域】 本發明為提供一種具高速週邊元件内連接匯流排( TT ^ ^、E X P r e s S )之虛擬萬用串列匯流排介面( 快閃記憶體儲存裝置’尤指利用高速週邊元件内 連接匯流排(p C I E X n r。 ^ K . P r e s s )作為傳輸介面的 虚擬4用串列匯流排介面(ϋ s B )儲存裝 【先前技術】 ·子、。 按,現今電腦科技以日新月異的速度成長,苴雷腦之 么展趨勢亦朝運算功能強及速度 八 的中央處理器(CPU)之時方向邁進,且因時下 傅輸速度根本無法跟上中央處理"^又㈣ 算中央處理器的效能繼續提昇,=速度,因此,就 是因為電腦的效能取決於整個 β有太大的改善,這 做-改良’才能令中央處理心二必須將整個電腦架構 然而,傳輸資料的速度=能發揮到極至。 了能使電腦的效能提昇,相=去匯流排的傳輸速度,為 度上改良,例如連接硬碟機的無不在匯流排的傳輸速 1 DE)的傳輸速度已達、二式驅動電子介面( 〇Mb/s提升到lQb/ ,〇MB/s、網路線由工 被傳輸速率480Mb串接埠的Rs~232更 所取代,且目前傳輪速率言、查f用串列匯流排(ϋ S B ) 連接匯流排(PC j ) = 3 3MB/S週邊元件内 】5rp0MB/s,成為新通道的傳輸速率提高到 排(PCI EXpres,迷週邊元件内連接匯流 且此種高速週邊元件内 12468011246801 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field The present invention provides a virtual universal serial bus interface (flash memory) with a high-speed peripheral component connection busbar (TT ^ ^, EXP res S ) The body storage device 'is especially a virtual 4 serial busbar interface (ϋ s B ) storage device using a high-speed peripheral component connection bus bar (p CIEX nr. ^ K . P ress ) as a transmission interface. [Prior Art] Nowadays, computer technology is growing at an ever-changing speed. The trend of the thunderstorm is also moving toward the central processing unit (CPU) with strong computing power and speed, and it is impossible to follow the current speed. On the central processing " ^ and (four) calculate the performance of the central processor continues to improve, = speed, therefore, because the performance of the computer depends on the overall improvement of β, this can be done - the improvement of the central processing must be The entire computer architecture, however, the speed of data transfer = can be used to the extreme. Can improve the performance of the computer, phase = transfer speed of the bus, for the improvement of the degree, such as The transmission speed of the hard disk drive's all-in-one bus is 1 DE), the transmission speed of the two-drive electronic interface (〇Mb/s is increased to lQb/, 〇MB/s, and the network route is connected by the transmission rate of 480Mb).埠Rs~232 is replaced, and the current transmission rate, check f serial bus (ϋ SB) connection bus (PC j ) = 3 3MB / S peripheral components] 5rp0MB / s, become a new channel The transmission rate is increased to the row (PCI EXpres, the peripheral components connected to the sink and the high-speed peripheral components within the 1246801

五、發明說明(2) 連接匯流排(P C I p 插拔的控制功能,所以 f r e s s )更提供了支援熱 PC ! Εχρ Γ :以,此高速週邊元件内連接匯流排( 再者,自快閃記。2能^吏用者所接受。 耐震、高儲存密度等以來已以低耗能非揮發性、 漸漸取性’在許多可攜性裝置中, 半導體技術日益精進,^聞1供電的s己憶體,更由於目前 是有突飛猛進的成長'Af憶體的儲存密度與傳輸速更 取代硬式磁碟機等^ 快閃記憶體在許多應用更可以V. Description of the invention (2) The connection bus (the control function of the PCI p plug and play, so fress) provides a support hot PC! Εχρ Γ : In this high-speed peripheral component, the busbar is connected (again, since flashing. 2 can be accepted by users. Shock-resistant, high storage density, etc. have been low-energy, non-volatile, and gradually taken'. In many portable devices, semiconductor technology is becoming more and more sophisticated. Body, but also because of the rapid growth of the current 'Af memory density and transmission speed to replace the hard disk drive, etc. ^ Flash memory can be used in many applications

Τ)或整合用萬用串列匯流排(USB 用串列匯流排(U S ^β 〇 E )作為傳輸介面,而萬 )的傳輸速率以=式驅動電子介面(IDE 傳輪诖盎48〇Mb/s和16〇MB/s ,立 用比μ 、“、、法跟上快閃記憶體的讀寫速度,使彳n Ζ H〇st)的萬用串歹丨厂六、, 上會被主機端( 子介面((usb)或整合式驅動電 態。 斤限制住,而無法達到其本身最好的狀 供某ί種;開發的罢系統或是軟體程式中,都會提 體的環境;:Γ上錯、.棺案管理和執行為-應用程弋斛. 衣兄,I面可讓私式设汁師執行開發一個 軟體:要的大部分工作,因此,在主機端所L: 借以Γ 特疋的環境介面與周邊設備做溝通,所IU Μ、直% ^、頊具備主機端的環境介面,才可埶扞由m週邊設 1246801 五、發明說明(3) 的指令。 是以’要如 傳輸速度更快的 設置之環境介面 從事此行業之相 【發明内容】 故,發明人 料,經由多方評 經驗,經由不斷 件内連接匯流排 串列匯流排介面 利誕生者。 本發明之主 流排(P C I 之間的傳輪介面 制器為設置有虛 使儲存裝置之快 週邊元件内連接 匯流排介面特性 根據上述之 控制器分別連接 兩速週邊元件内 連接介面,而微 件内連接匯流排 何使快 匯流排 做溝通 關廠商 有鑑於 估及考 試作及 (PC (US 要目的 Exp ,且儲 擬萬用 閃記憶 匯流排 〇 目的, 有快閃 連接匯 控制器 介面及 閃記憶體所製成之儲存裝置可利用 作為其傳輸介面’並可與主機端所 ’以達到其本身的最好狀態,即為 所亟欲研究改善之方向所在者。# 上述之問題與缺失,乃搜集相關資 量’並以從事於此行業累積之多年 修改,始設計出此種具高速週邊元 I Express)之虛擬萬用 B )快閃記憶體儲存裝置的發明專 乃在於利用高速週邊元件内連接匯 r e s s )作為主機端與儲存裝置 存裝置為设置有微控制器,而微控 串列匯流排介面(U S B )模組, 體與主機端存取資料時可達到高速 的最佳速率,同時亦擁有萬用串列 該儲存裝置係具有微控制器,且微 記憶體及可連接至主機端所設置之 流排的高速週邊元件内連接匯流排 具有快閃記憶體介面、高速週邊元 虛擬萬用串列匯流排介面模組,俾Τ) or integrated with the universal serial bus (USB with serial bus (US ^ β 〇 E) as the transmission interface, and 10,000) transmission rate with = drive electronic interface (IDE transmission 诖 〇 48 〇 Mb /s and 16〇MB/s, the ratio of μ, ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The host side (sub-interface (usb) or integrated drive state. The limit is limited, but can not reach its own best shape for a certain kind; in the development of the stop system or software program, the environment will be lifted; : Γ 错 、 棺 棺 管理 管理 管理 管理 管理 管理 应用 应用 应用 应用 应用 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣 衣. Γ The special environment interface communicates with peripheral devices. The IU Μ, 直 % ^, 顼 has the host interface environment interface, can be set by the m surrounding 1268081 five, invention instructions (3) instructions. For example, the environmental interface of the setting with faster transmission speed is engaged in the industry [invention content]. Therefore, the inventor expects to pass the multi-party evaluation. Experience, through the continuous connection of the bus bar serial bus interface to benefit the birth. The mainstream row of the invention (the transfer interface between PCIs is the fast peripheral component connected bus interface interface with virtual storage device) According to the above-mentioned controller, respectively, the connection interface of the two-speed peripheral component is connected, and the connection bus in the widget is used to make the quick busbar to communicate. The manufacturer has an evaluation of the test (PC (US purpose Exp, and the storage plan) For the purpose of flash memory bus, a flash memory connection controller interface and a flash memory memory device can be utilized as its transmission interface 'and can be connected to the host side to achieve its own best state, ie For those who want to study the direction of improvement. # The above problems and lacks, is to collect relevant resources' and to design a virtual million with high-speed peripheral I Express) The invention of B) flash memory storage device is to use the high-speed peripheral component to connect the ress as the host end and the storage device. It is equipped with a microcontroller, and the micro-control serial bus interface (USB) module can achieve the highest speed at the high speed when accessing data between the body and the host, and also has a universal serial array. The storage device has micro-control. And the micro memory and the high-speed peripheral component connection bus that can be connected to the flow line set on the host end have a flash memory interface, a high-speed peripheral virtual universal serial bus interface module,

第8頁 1246801 五、發明說明(4) 使主機端對儲存裝置下 面指令時,該指令為會傳:J卜取之萬用串列匯流排介 組,並由虛擬萬用串列ί 萬用串列匯流排介面模 存裝置内之快閃記憶體的;:乂:模組來完成指令’而儲 器所設置之快閃記憶體會根據指令並藉由微控制 (p C ! 迷週邊元件内連接匯流排 憶體或高速週邊元件内連,會將資料轉換為快閃記 再傳至主機端或快閃記匯能接,的資料格式, 列匯流排介面模組對儲“置端可透過虛擬萬用串 流排介面指令,且資下達存取貧料之萬用串列匯 接匯“ΜΗ輸:週邊元件㈣ 【實施方式ί 列匯流排介面的特質。 其構i,: t ::二::效’本發明所採用之技術手段及 功能如下,俾利完全瞭解。 叶力說明其特徵與 =閱第-圖所示,係為本創作較佳 .:可清楚看出,本創作之儲存襞置i A ,之方塊圖 邊兀件内連接匯流排(Pc I EXp r 1為具有高速週 面1 ^二微控制器i 2及快閃記憶體i ^ :8 ).連接介 4巧速週邊元件内連接匯流排(p C丨/、中· = = s s)連接介面1 1為可供連接 ό又置之向速週邊元件内連接匯流排(p 主機端2所Page 8 1246801 V. Description of the invention (4) When the host side commands the storage device below, the instruction is a general transmission: the JB is used in the serial bus-communication group, and is used by the virtual universal serial port. The flash memory in the serial bus interface device;:乂: the module completes the instruction' and the flash memory set by the memory is controlled according to the instruction and by the micro control (p C ! Connected to the busbar memory or high-speed peripheral components, the data will be converted into flash memory and then transmitted to the host or flash memory. The data format of the bus interface module is stored. Use the serial interface command, and the unilateral serial concatenation of the access to the poor material. "Transmission: Peripheral components (4) [Implementation ί The characteristics of the bus interface. Its configuration i,: t :: 2: : Effect 'The technical means and functions adopted by the present invention are as follows, and the profit is fully understood. Ye Li's description of its characteristics and = reading the first picture shows that this is a better creation.: It can be clearly seen that the storage of this creation Ii A , the block diagram is connected to the bus bar (Pc I EXp r 1 is a high-speed peripheral 1 ^ 2 microcontroller i 2 and flash memory i ^ : 8 ). Connection 4 smart peripheral components inside the bus (p C 丨 /, medium = = ss) connection The interface 1 1 is a connection busbar for the connection of the slewing peripheral component (p host terminal 2

Express)2l。Express) 2l.

第9頁 1246801 五、發明說明(5) 該微控制器1 2為具有快閃記憶體介面1 2 1 、高速 週邊元件内連接匯流排(PC I Exp r e s s)介面 1 2 2及虛擬萬用串列匯流排介面模組(U S B Μ o d u 1 e ) 1 2 3 ,而虛擬萬用串列匯流排介面模組 (USB Modu1e)123為具有萬用串列匯流排 介面主控端(USB Host)1231及萬用串列匯 流排介面裝置端(USB Devi ce) 1232 ,且 微控制器1 2為連接於高速週邊元件内連接匯流排(P C I Express)連接介面11,而虛擬萬用串列匯 j流排介面模組(U S Β Μ 〇 d u 1 e ) 1 2 3並非實體 ,而是由設計者利用韌體程式模擬的一個虛構體。 該快閃記憶體1 3為連接於微控制器1 2。 當儲存裝置1所設置之高速週邊元件内連接匯流排( PCI Exp r e s s)連接介面1 1連接至主機端2 所設置之高速週邊元件内連接匯流排(P C I 'Express) 21時,該儲存裝置1之微控制器12 為會對主機端1宣告儲存裝置1為一個萬用串列匯流排介 面主機端,如此,主機端2雖以高速週邊元件内連接匯流 排(P C I E X p r e s s )架構來和微控制器1 2做 〇溝通,但會認定微控制器1 2是一個萬用串列匯流排介面 的主機端。 而當主機端2下達萬用串列匯流排介面之儲存指令時 ,該指令為會先傳送至微控制器1 2之虛擬萬用串列匯流 排介面模組(USB Modu 1 e) 123所設置之萬Page 9 1246801 V. Description of the Invention (5) The microcontroller 12 has a flash memory interface 1 2 1 , a high-speed peripheral component connection bus (PC I Express) interface 1 2 2 and a virtual universal string. The serial bus interface module (USB Μ odu 1 e ) 1 2 3 , and the virtual universal serial bus interface module (USB Modu1e) 123 has a universal serial bus interface host (USB Host) 1231 And the universal serial bus interface device terminal (USB Devi ce) 1232, and the microcontroller 12 is connected to the high speed peripheral component connection bus (PCI Express) connection interface 11, and the virtual universal serial port j stream The interface module (US Β Μ 〇du 1 e ) 1 2 3 is not an entity, but a fictional body simulated by the designer using the firmware program. The flash memory 13 is connected to the microcontroller 12. When the high-speed peripheral component connection bus (PCI Express) connection interface 1 1 of the storage device 1 is connected to the high-speed peripheral component connection bus (PCI 'Express) 21 provided by the host terminal 2, the storage device 1 The microcontroller 12 announces that the storage device 1 is a universal serial bus interface host to the host terminal 1, so that the host terminal 2 is connected to the PCIEX press architecture and the micro-controller in a high-speed peripheral component. Device 1 2 communicates, but it is assumed that the microcontroller 12 is the host side of a universal serial bus interface. When the host terminal 2 releases the storage instruction of the universal serial bus interface, the command is set to the virtual universal serial bus interface module (USB Modu 1 e) 123 which is first transmitted to the microcontroller 12. Ten thousand

第10頁 1246801 11 排令接件1 憶 3 > C流指連元1記 2t端匯成内邊面閃 1 S置列完件週介快 }o裝串2元速接之 tH面用3邊高連置 S 介萬2週及}設 OB 排由1速1 S 所 H S流而}高2 S 2 U匯, 0->由}0;1 BC列2C經 Sr 器 S端串3i先 s P制 U控用 2V會 ex控 C 主萬1 e 為 rE 微 端面至}0料口 且 控介送 e 資 XI , 主排傳 CB 的ECCXI 面流令 i s 2 p 1 介匯指VU端1C器 排列此ec機C排制 ⑹流串將D端主P流控 ^(匯用會 置,C 匯微 J列萬1B裝時排接至 |串且3 S面此流連送 、用,2U 介,匯内傳 受 料1 控介送} 接 資器 主排傳 e 能 之制 面流令 c B 所 存控 介匯指i S 3 儲微 排列此VU 1 所至 流串將 ec 體。内送B匯用會D端 憶内1傳S 列萬1 置 記3置先U 串且 3B 裝 閃1裝會{用,2S 面 快體存為組萬11U介 為憶儲令模的3}c排 換記取指面置2t端流 轉閃讀面介設1 S置匯 料快欲介者所ο裝9 資至2排流3tH面串 此存端流匯2S 介用 將儲機匯列1 OB排萬 會而主列串}HS流由 1 ,當串用 eU匯而 2式,用萬1BC列, 1格者萬擬 US 端串2 面料再該虛du控用3 介資 ,之 O C主萬2 體的 時2M端面至1Page 10 1246801 11 Order connector 1 Recall 3 > C flow refers to Lianyuan 1 note 2t end merge into inner side flash 1 S set finish piece Zhou Jie fast} o string 2 yuan speed connection tH surface 3 sides high connection S jie 2 weeks and} set OB row by 1 speed 1 S HS flow} high 2 S 2 U sink, 0-> by }0; 1 BC column 2C via Sr S end string 3i first s P system U control with 2V will ex control C main 10,000 1 e for rE micro end to } 0 mouth and control to send e XI, the main CB ECCXI surface flow is 2 p 1 VU end 1C device arrangement ec machine C row system (6) stream string D terminal main P flow control ^ (meeting will be set, C sink micro J column million 1B installed when the line is connected to | string and 3 S face this stream, Use, 2U media, sink transfer material 1 control media to send} Receiver main row pass e energy noodle flow order c B storage control interface sink i S 3 storage micro-arrangement VU 1 to stream string will ec Body. Incoming B sinks will use D-end memory 1 pass S Lewan 1 Set 3 first U string and 3B install flash 1 will be {use, 2S face fast body save as group 10,000 11U for memory order mode 3 }c 换换指指面面2t端流转闪读面介介1 S 置料料快要介者所装9 资到2排流3tH面串This save end stream sink 2S The machine column 1 OB row and the main column string}HS flow by 1, when the string uses eU sink and 2 type, with 10,000 1BC column, 1 grid, the US US end string 2 fabric and then the virtual du control 3 Capital, the OC main 10,000 body 2M end face to 1

體2 邊能 憶1 週所 記器 速1 閃制 高2 快控 為} 該微I換S ,且 C轉 S 時,P 料 e 此 2 C資 Γ ,1 排此 P 令器流將X 指制匯會E 成控接2 第11頁 五、發明說明(7) 夠接受之格式’再透過高速週邊元件内連接匯 PCT PYnress)連接介面11及高 Express) 2 !246801 p C I Exp 内連接匯流排(P c 機端2。 由上述可知’主機端2對儲存裝置1進行 ;出=料是二接;過微控制器12從快閃記 取出或寫入,而項取或健六 排介面模組(ϋ S Β Μ 、〒令是由虛擬萬 用串列匯流排介面主控娘=d u 1 e ) 1 2 3 及萬用串列匯流排介面 S B Host 1 2 3 2 完成,因此 DeBody 2 can recall 1 week of record speed 1 Flash high 2 Fast control is} The micro I change S, and when C turns S, P material e this 2 C resource, 1 row of this P command flow will X Refers to the meeting of the meeting E. Control page 2 Page 11 V. Invention description (7) Acceptable format 'Re-connected through high-speed peripheral components PCT PYnress CONNECTION 11 and high Express) 2 !246801 p CI Exp Internal connection Bus bar (P c terminal 2. It can be seen from the above that 'host 2 is for storage device 1; output = material is two; over controller 12 is taken out or written from flash, and item or healthy six-row interface The module (ϋ S Β 〒 , 〒 是 is from the virtual universal serial bus interface master control mother = du 1 e ) 1 2 3 and the universal serial bus interface SB Host 1 2 3 2 is completed, so De

一個高速週邊元件内2即可認定此儲 p v $接匯流排(p r T E x p "")介面的萬用“ p c 1 再者,當主機端2 =用/列匯流排介面 指令將在虛擬萬用串列 i之指令不包含資A high-speed peripheral component can be identified as 2 in the high-speed peripheral component (p TE xp "") interface "pc 1 again, when the host 2 = with / column bus interface instructions will be virtual The instruction of universal serial i does not include capital

M 0 d u 1 e ) 1 2 3匯ί排介面模組(U S 閃記憶體1 3做溝通。中完成而微控制器1 2 請參閱第二圖所示 料時之示意圖,由圖中二^本創作較佳實施 1在傳輸資料的實體屉:看出’主機端2 端(丁 X)與接收端::由7組單工通道2 1 用一組或一組以上。 早工通道2M 0 du 1 e ) 1 2 3 ί 排 interface module (US flash memory 1 3 to communicate. Completed in the microcontroller 1 2 See the diagram in the second figure, from the figure 2 ^ This creation is preferably implemented in the physical drawer of the transmission data: see 'host end 2 end (D) X and receiving end:: 7 sets of simplex channels 2 1 with one or more sets. Early work channel 2

疋以,本發明之I ΡΓΤ r 具高速週邊元株咖土 PCI E X p r e 〇 、迓兀件内連接匯 s )之虛擬萬用串列匯 流排( 速週邊元件 1傳送至主 讀取或儲存 憶體1 3内 用串列匯流 所設置之萬 )12 3 1 vice) 存裝置1為 儲存裝置。 料處理,此 B 將不會和快 例於傳輸資 與儲存裝置 1組成發送 1 1亦可使 流排( 流排介面(疋 , 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 PCI 虚拟 PCI PCI 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟 虚拟In the body 1 3, the arbitrarily arranged by the serial confluence is 12). The storage device 1 is a storage device. Material processing, this B will not be combined with the fast transmission and storage device 1 to send 1 1 or the flow row (flow interface (

$ 12頁 贫明說明(8) U S B )快 於’本發明 主控端及萬 的指令,並E X p r e ’讓資料於 供之傳輸速 上述詳 明而已,惟 ’凡其它未 變化與修飾 閃記憶體儲 為利用儲存 用串列匯流 使用局速週 s s )作為 傳輸時可達 率’而使儲 細說明為針 該實施例並 脫離本發明 變更’均應 存裝置 裝置所 排介面 邊元件 主機端 到面速 存裝置 對本發 非用以 所揭示 包含於 為可改善 設置之萬 裝置端來 内連接匯 與儲存裝 週邊元件 可達到最 明一種較 限定本發 之技藝精 本發明所 習用之技 用串列匯 執行主機 流排(p 置之間的 内連接匯 佳的傳輸 佳之可行 明之申請 神下所完 涵蓋之專 術闕鍵在 流排介面 端所下達 C I 傳輸介面 流排所提 速率。 實施例說 專利範圍 成之均等 利範圍中 綜上所述,本發明之罝 PCI E虛擬匯流排( 閃記憶體儲存裝置於使料==串龍流排介面快 新穎性、創作性及進步性之;要:”效增進’誠符合 盼審委早日賜准本案,以保障發明人2法提出申請, 鈞局有任何稽疑,請不吝來函指辛告發明,倘若 合,實感德便。 θ '、發明人定當竭力配 1246801 圖式簡單說明 圖式簡單說明 第第 圖圖 圖 意 示 之 時 。料 圖資 塊輸 方傳 之於 rnj rn^ 施施 實實 L-vtLt-㊆ $ 較較 一· Je一· 作作 本本 為為 係係$12 page of poor description (8) USB) faster than 'the main control terminal of the invention and 10,000 instructions, and EX pre 'allow the data for the transmission speed of the above detailed, but 'other unchanged and modified flash memory The storage is performed by using the serial stream ss of the storage using the speed ss) as the transmission reachability rate, and the storage specification is described as the embodiment and the invention is changed from the host device to the interface side of the interface device The surface-storing device can be used to connect the sinking and storing peripheral components to the device device for improving the setting, and the technical string used in the present invention can be achieved. The execution of the host stream is performed by the column. The transmission of the internal connection between the p-sets is better. The application of the special-purpose key that is covered by the application is released at the rate of the CI transmission interface at the stream interface. In summary, the scope of the patent range is equal to the above, the PCI E virtual busbar of the present invention (flash memory storage device in the material == string torrent interface is fast and novel , creative and progressive; to: "effectiveness improvement" is in line with the expectation of the trial committee to grant the case as soon as possible, in order to protect the inventor's 2 law application, the bureau has any doubts, please do not hesitate to refer to the invention, if θ ', the inventor will try his best to match 1246801. The simple explanation of the diagram shows the moment when the diagram is shown. The source of the map is transmitted to rnj rn^. vtLt-seven $ is more than one · Je I · as the book for the department

明 說 teb # 符 件 元 要 主 rL l、儲存裝置 1 1、高速週邊元件内連接匯流排(P C I Exp r e s s)連接介面 1 2、微控制器 1 2 1 、快閃記憶體介面 1 2 2、高速週邊元件内連接匯流排(P C I Express)介面 1 2 3 、虛擬萬用串列匯流排介面模組(U S B Module ) 1 2 3 1 、萬用串列匯流排介面主控端(U S B Host) 1 2 3 2 、萬用串列匯流排介面裝置端(U S B Device) 1 3、快閃記憶體 2、主機端Ming said teb # symbol element to main rL l, storage device 1 1, high-speed peripheral components connected to the bus (PCI Exp ress) connection interface 1 2, microcontroller 1 2 1 , flash memory interface 1 2 2, high speed Peripheral component connection bus (PCI Express) interface 1 2 3 , virtual universal serial bus interface module (USB Module) 1 2 3 1 , universal serial bus interface host (USB Host) 1 2 3 2, universal serial bus interface device (USB Device) 1 3, flash memory 2, host side

2 1 、高速週邊元件内連接匯流排(P C I2 1 , high-speed peripheral components connected to the bus bar (P C I

第14頁 1246801 圖式簡單說明Page 14 1246801 Schematic description

Express 2 1 1、單工通道 〇Express 2 1 1. Simplex channel 〇

讀I 第15頁Read I第15页

Claims (1)

1246801 六、申請專利範圍 1、一種具高速週邊元件内連接匯流排(P C I Exp r e s s)之虛擬萬用串列匯流排介面( U S B )快閃記憶體儲存裝置,該儲存裝置係具有微 控制器、快閃記憶體及兩速週邊元件内連接匯流排連 接介面;其中: ~ 該微控制器具有可將資料轉換為快閃記憶體格式之快 閃記憶體介面、可將資料轉換為高速週邊元件内連接 ί ^ ^袼式之尚速週邊元件内連接匯流排介面、及虛 )介^串列匯流排介面模組’且虛擬萬用帛列匯流排 排介而魬為設置有可接收主機端所下達萬用串列匯流 萬用电<指令的萬用串列匯流排介面主控端及可完成 置端;列匯流排介面之指令的萬用串列匯流排介面裝 %丨穴内 控制器 記憶體 該高迷 主機端 週邊元 藉此當 制器為 排介面 面指令 由虛擬 記憶體為 ’且快閃 中讀出; 週邊元件 所設置之 件内連接 儲存裝置 會對主機 主機端, 為會傳送 4用串列 經虛擬萬用串列匯流排介面連接於微 S憶體為可儲存資料或將資料由快閃 内連接 高速週 匯流排 連接於 端宣告 且主機 至虛擬 匯流排1246801 VI. Patent Application Area 1. A virtual universal serial bus interface (USB) flash memory storage device with a high-speed peripheral component connected to a bus (PCI Exp ress), the storage device has a microcontroller, The flash memory and the two-speed peripheral components are connected to the busbar connection interface; wherein: ~ The microcontroller has a flash memory interface that converts data into a flash memory format, and converts the data into high-speed peripheral components. Connect ί ^ ^ 之 尚 周边 周边 周边 周边 周边 周边 周边 周边 周边 周边 及 及 及 及 及 及 串 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且The universal serial port of the multi-purpose serial communication bus < command is used to terminate the bus interface interface and the terminal can be completed; the universal serial bus interface of the column bus interface command is installed in the memory of the controller The fascinating host peripheral element is used as the interface interface command by the virtual memory as 'and flashing out; the peripheral component is connected to the storage device The host host side is connected to the micro-S memory to store data or to connect the data to the end of the high-speed weekly bus and is connected to the host by virtual serial port bus interface. Busbar 第16頁 匯流排連接介面為可供連接至 邊元件内連接匯流排,且高速 連接介面為連接於微控制器, 主機端時’該儲存裝置之微控 儲存裝置為一個萬用串列匯流 端所下達之萬用串列匯流排介 萬用串列匯流排介面模組,並 介面模組來完成指令,而儲存 1246801 六、申請專利範圍 裝置内之快閃記憶體的資料為會根據指令並藉由微控 制器所設置之快閃記憶體介面及高速週邊元件内連接 匯流排介面會將資料轉換為快閃記憶體或高速週邊元 件内連接匯流排所能接受的資料格式,再傳至主機端 或快閃記憶體儲存。 2、 如申請專利範圍第1項所述之具高速週邊元件内連接 匯流排(P C I E X p r e s s )之虛擬萬用串列 匯流排介面快閃記憶體儲存裝置,其中該主機端與儲 存裝置在傳輸資料的實體層可由一組單工通道組成發 送端(Tx)與接收端(Rx)。 3、 如申請專利範圍第2項所述之具高速週邊元件内連接 匯流排(P C I E X p r e s s )之萬用串列匯流 排介面快閃記憶體儲存裝置,其中該單工通道可為一 組或一組以上。 4、 如申請專利範圍第1項所述之具高速週邊元件内連接 匯流排(PCI Expr e s s)之虛擬萬用串列 匯流排介面快閃記憶體儲存裝置,其中該虛擬萬用串 列匯流排介面模組並非實體,而是由設計者利用韌體 程式模擬的一個虛構體。The busbar connection interface on page 16 is connected to the inner busbar of the side component, and the high-speed connection interface is connected to the microcontroller. When the host end is used, the micro-control storage device of the storage device is a universal serial convergent terminal. The issued universal serial bus is connected to the universal serial bus interface module, and the interface module is used to complete the instruction, and the stored 1246801 6. The data of the flash memory in the patent application device is based on the instruction. The flash memory interface set by the microcontroller and the high-speed peripheral component connection bus interface convert the data into a data format acceptable for the flash memory or the high-speed peripheral component connection bus, and then transmitted to the host. End or flash memory storage. 2. A virtual universal serial bus interface flash memory storage device with a high-speed peripheral component connection bus (PCIEX press) as claimed in claim 1, wherein the host device and the storage device are transmitting data. The physical layer can be composed of a set of simplex channels (Tx) and receiver (Rx). 3. A universal serial bus interface flash memory storage device with a high speed peripheral component interconnect bus (PCIEX press) as claimed in claim 2, wherein the simple channel can be a group or a Above group. 4. The virtual universal serial bus interface flash memory storage device with a high-speed peripheral component connection bus (PCI Expr ess) according to the first application of the patent scope, wherein the virtual universal serial bus is arranged. The interface module is not an entity, but a fictitious body that is simulated by the designer using a firmware program. 第17頁Page 17
TW94101041A 2005-01-13 2005-01-13 Virtual USB flash memory storage device with a PCI express bus TWI246801B (en)

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JP2005289633A JP4509906B2 (en) 2005-01-13 2005-10-03 Virtual USB flash memory storage device having PCI Express

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