CN110618958A - GPIO circuit and chip - Google Patents

GPIO circuit and chip Download PDF

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Publication number
CN110618958A
CN110618958A CN201910884109.9A CN201910884109A CN110618958A CN 110618958 A CN110618958 A CN 110618958A CN 201910884109 A CN201910884109 A CN 201910884109A CN 110618958 A CN110618958 A CN 110618958A
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CN
China
Prior art keywords
circuit
sub
chip
pull
logic control
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CN201910884109.9A
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Chinese (zh)
Inventor
宋登明
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Chengdu Rui Core Micro Polytron Technologies Inc
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Chengdu Rui Core Micro Polytron Technologies Inc
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Priority to CN201910884109.9A priority Critical patent/CN110618958A/en
Publication of CN110618958A publication Critical patent/CN110618958A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a GPIO circuit and a chip, and relates to the technical field of integrated circuits. The GPIO circuit is used for connecting a chip and realizing communication between the chip and the outside, the circuit comprises a sending module, a receiving module and a pull-up and pull-down resistance module, the chip sends a signal to the outside of the chip through the sending module and receives a signal outside the chip through the receiving module, and the pull-up and pull-down resistance module is used for pulling up and down the chip; the receiving module comprises a first receiving submodule working in a first power supply voltage domain, a second receiving submodule working in a second power supply voltage domain and a third receiving submodule working in a third power supply voltage domain; the priority of the third power supply voltage domain is greater than that of the second power supply voltage domain, and the priority of the second power supply voltage domain is greater than that of the first power supply voltage domain. The technical scheme of the invention can work under low power consumption and ultra-low power consumption, can meet the requirement of the existing low-power-consumption system, and realizes the low-power-consumption management of the circuit.

Description

GPIO circuit and chip
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a GPIO circuit and a chip.
Background
GPIO (General-purpose input/output) is a pin of a chip, and is connected to an external device, thereby implementing functions of communication, control, and data acquisition between the chip and the outside. The GPIO PIN can be directly controlled by software, and can support a plurality of applications in a programming mode, and the PIN PIN can be used as General Purpose Input (GPI), General Purpose Output (GPO) or General Purpose Input and Output (GPIO) according to actual needs; when the output is used, the control circuit can be used for controlling a relay, a buzzer, an LED and the like; as input, it can be used to acquire sensor status, high and low levels, interrupt signals, low speed signals, etc.
The GPIO in the prior art is used as a port expander, has a single function effect, and cannot support a chip with ultra-low power consumption.
Disclosure of Invention
The invention mainly aims to provide a GPIO circuit and a chip, aiming at realizing low power consumption management of the circuit.
In order to achieve the above object, the present invention provides a GPIO circuit for connecting a chip and implementing communication between the chip and the outside, the GPIO circuit including a transmitting module, a receiving module, and a pull-up and pull-down resistor module, wherein the chip transmits a signal to the outside of the chip through the transmitting module and receives a signal from the outside of the chip through the receiving module, and the pull-up and pull-down resistor module is configured to pull up and pull down the chip; the receiving module comprises a first receiving submodule working in a first power supply voltage domain, a second receiving submodule working in a second power supply voltage domain and a third receiving submodule working in a third power supply voltage domain; the priority of the third power supply voltage domain is greater than that of the second power supply voltage domain, and the priority of the second power supply voltage domain is greater than that of the first power supply voltage domain.
Preferably, the first receiving submodule comprises a first level conversion sub-circuit, a first logic control sub-circuit, a first trigger and a second level conversion sub-circuit; the first level conversion sub-circuit receives a first group of logic control signals and carries out level conversion, the converted first group of logic control signals are input to the first logic control sub-circuit, and the first trigger is controlled to be turned on or turned off through the first logic control sub-circuit; the first trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the first trigger is started, the first trigger sends the chip external signal to the second level conversion sub-circuit and inputs the chip external signal after level conversion to the chip.
Preferably, the second receiving sub-module comprises a third level conversion sub-circuit, a second logic control sub-circuit, a second trigger and a fourth level conversion sub-circuit; the third level conversion sub-circuit receives a second group of logic control signals and carries out level conversion, the converted second group of logic control signals are input to the second logic control sub-circuit, and the second trigger is controlled to be turned on or turned off through the second logic control sub-circuit; the second trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the second trigger is started, the second trigger sends the chip external signal to the fourth level conversion sub-circuit and inputs the chip external signal after level conversion to the chip.
Preferably, the third receiving sub-module comprises a third logic control sub-circuit, a third flip-flop and a buffer output sub-circuit; the third logic control sub-circuit receives a third group of logic control signals to control the third trigger to be turned on or turned off; the third trigger is connected to the PAD end and receives a chip external signal through the PAD end, when the second trigger is started, the second trigger sends the chip external signal to the buffer output sub-circuit, and the buffer output sub-circuit inputs a signal to the chip.
Preferably, the first, second and third flip-flops are schmitt flip-flops.
Preferably, the pull-up and pull-down resistor module comprises a pull-up resistor and a pull-down resistor which are connected in series, and the end of the pull-up resistor connected with the pull-down resistor is further connected to the sending module, the receiving module and the PAD end; the other end of the pull-up resistor is connected to a third power supply voltage domain through a first switch, and the other end of the pull-down resistor is grounded through a second switch.
Preferably, the transmitting module comprises a fifth level shift sub-circuit, a fourth logic control sub-circuit and a driving sub-circuit; the fifth level conversion sub-circuit receives a fourth group of logic control signals and carries out level conversion, the converted fourth group of logic control signals are input into the fourth logic control sub-circuit, and the fourth logic control sub-circuit is used for switching on and selecting a driving gear of the driving sub-circuit or switching off the driving sub-circuit.
Preferably, the driving sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; the gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected with each other and the fourth logic control module, and the gates of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are connected with each other and the fourth logic control module; the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected to the third power supply voltage domain; the source electrodes of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are grounded; the drain electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube are mutually connected and connected with the fourth logic control module, the end where the pull-up resistor and the pull-down resistor are connected and the PAD end.
Preferably, the first power voltage domain is a core voltage, the second power voltage domain is a normally open power voltage, and the third power voltage domain is an IO voltage.
The invention also provides a chip which comprises the GPIO circuit as the pin and is communicated with the outside.
According to the technical scheme, the three receiving sub-modules working in different voltage domains are used for respectively receiving the external signals of the chip, so that the GPIO circuit can work under low power consumption and ultra-low power consumption, and can meet the requirements of the existing low-power-consumption system:
in the low power consumption mode, the power down of a first power supply voltage domain can be supported; when the first power supply voltage domain is powered down, the second receiving submodule and the third receiving submodule are still in a working state, and signals can be continuously input into the chip;
in the ultra-low power consumption mode, the power failure of a first power supply voltage domain and a second power supply voltage domain can be supported; when the first power supply voltage domain and the second power supply voltage domain are powered down, the third receiving sub-module is still in a working state, and signals can be continuously input into the chip.
Drawings
FIG. 1 is a schematic diagram of a GPIO circuit of the present invention;
FIG. 2 is a schematic circuit diagram of a first receiving sub-circuit in the GPIO circuit of the present invention;
FIG. 3 is a schematic circuit diagram of a second receiving sub-circuit in the GPIO circuit of the present invention;
FIG. 4 is a schematic circuit diagram of a third receiving sub-circuit in the GPIO circuit according to the present invention;
FIG. 5 is a schematic circuit diagram of an up-down pull-down resistor module in the GPIO circuit of the present invention;
fig. 6 is a schematic circuit diagram of a transmitting module in the GPIO circuit of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a GPIO circuit for connecting a chip and implementing communication between the chip and the outside, where the GPIO circuit includes a sending module, a receiving module, and a pull-up and pull-down resistor module, where the chip sends a signal to the outside of the chip through the sending module and receives a signal from the outside of the chip through the receiving module, and the pull-up and pull-down resistor module is used to pull up and pull down the chip; the receiving module comprises a first receiving submodule working in a first power supply voltage domain VDD, a second receiving submodule working in a second power supply voltage domain VDD _ AON and a third receiving submodule working in a third power supply voltage domain VDDIO; the priority of the third power voltage domain VDDIO is greater than that of the second power voltage domain VDD _ AON, and the priority of the second power voltage domain VDD _ AON is greater than that of the first power voltage domain VDD.
The GPIO circuit can work under low power consumption and ultra-low power consumption by using the three receiving sub-modules working in different voltage domains to respectively receive external signals of a chip, and can meet the requirement of an existing low-power-consumption system.
Under a low power consumption mode, the GPIO circuit of the embodiment of the invention can support the power failure of a first power supply voltage domain VDD; when the first power supply voltage domain VDD is powered down, the second receiving submodule and the third receiving submodule are still in a working state, and signals can be continuously input into the chip; in an ultra-low power consumption mode, the GPIO circuit of the embodiment of the invention can support the power failure of a first power supply voltage domain VDD and a second power supply voltage domain VDD _ AON; when the first power supply voltage domain VDD and the second power supply voltage domain VDD _ AON are powered off, the third receiving sub-module is still in a working state, and signals can be continuously input into the chip.
Specifically, the first power voltage domain VDD is a core voltage, the second power voltage domain VDD _ AON is a normally open power voltage, and the third power voltage domain VDDIO is an IO voltage.
As shown in fig. 1 and fig. 2, the first receiving submodule includes a first level shift sub-circuit, a first logic control sub-circuit, a first flip-flop, and a second level shift sub-circuit; the first level conversion sub-circuit receives a first group of logic control signals and carries out level conversion, the converted first group of logic control signals are input to the first logic control sub-circuit, and the first trigger is controlled to be turned on or turned off through the first logic control sub-circuit; the first trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the first trigger is started, the first trigger sends the chip external signal to the second level conversion sub-circuit and inputs the chip external signal after level conversion to the chip. The PAD end is the end of GPIO circuit connection chip outside.
Specifically, as shown in fig. 2, the first set of logic control signals includes a first control signal SH _ VDD and a second control signal DC _ VDD, which go from low to high through the first level shift sub-circuit and are output through the first logic control sub-circuit to obtain SH _ VDD _ HV and DC _ VDD _ HV to control the first flip-flop and the second level shift sub-circuit to be turned on or off, respectively.
When the GPIO circuit is used as the input of the chip, the PAD end receives an external signal of the chip and sends the external signal to the chip through the receiving module. In the first power supply voltage domain VDD, the first receiving sub-circuit receives a chip external signal sent by the PAD end and sends the chip external signal into the chip.
Specifically, as shown in fig. 2, the first set of logic control signals includes a first control signal SH _ VDD and a second control signal DC _ VDD, which are turned from low to high by the first level shift sub-circuit and output by the first logic control sub-circuit to control the first flip-flop and the second level shift sub-circuit to be turned on or off, respectively. When the first control signal SH _ VDD and the second control signal DC _ VDD are 1, the first trigger is switched on, the second level conversion sub-circuit is switched on, and a chip external signal sent by the PAD end is output to the chip; when the first control signal SH _ VDD and the second control signal DC _ VDD are 0, the first flip-flop is turned off, the second level shifter sub-circuit is turned off, and the output is reset.
As shown in fig. 1 and fig. 3, the second receiving submodule includes a third level shift sub-circuit, a second logic control sub-circuit, a second flip-flop, and a fourth level shift sub-circuit; the third level conversion sub-circuit receives a second group of logic control signals and carries out level conversion, the converted second group of logic control signals are input to the second logic control sub-circuit, and the second trigger is controlled to be turned on or turned off through the second logic control sub-circuit; the second trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the second trigger is started, the second trigger sends the chip external signal to the fourth level conversion sub-circuit and inputs the chip external signal after level conversion to the chip.
As shown in fig. 3, the second set of logic control signals includes PU _ AON, PD _ AON, SH _ AON, and DC _ AON, where PU _ AON and PD _ AON pass through the fourth level shifter sub-circuit and the second logic control sub-circuit to respectively control the pull-up and pull-down resistor module to pull up and down the circuit; SH _ AON and DC _ AON are obtained through the fourth level conversion sub-circuit and the second logic control sub-circuit, and then SH _ AON _ HV and DC _ AON _ HV are obtained and used for respectively controlling the on/off of the second trigger and the fourth level conversion sub-circuit.
In the second power supply voltage domain VDD _ AON, the second receiving sub-circuit receives a chip external signal sent by the PAD end and sends the chip external signal to the chip, and at the moment, the power failure of the first power supply voltage domain VDD can be supported. The operating principle of the second receiving sub-circuit is the same as that of the first receiving sub-circuit.
As shown in fig. 1 and 4, the third receiving sub-module includes a third logic control sub-circuit, a third flip-flop and a buffer output sub-circuit; the third logic control sub-circuit receives a third group of logic control signals to control the third trigger to be turned on or turned off; the third trigger is connected to the PAD end and receives a chip external signal through the PAD end, when the second trigger is started, the second trigger sends the chip external signal to the buffer output sub-circuit, and the buffer output sub-circuit inputs a signal to the chip.
As shown in fig. 4, the third set of logic control signals includes a third control signal SH _ HV, a fourth control signal DC _ CNT, a PU _ HV, and a PD _ HV, and the third control signal SH _ HV and the fourth control signal DC _ CNT are converted and output by the third logic control sub-circuit to control the third flip-flop and the buffer output sub-circuit to be turned on or off, respectively; the PU _ HV and the PD _ HV are converted and output through the third logic control sub-circuit so as to respectively control the pull-up and pull-down resistance module to pull up and pull down the circuit.
As shown in fig. 4, in the third power voltage domain VDDIO, the third receiving sub-circuit receives the chip external signal sent by the PAD terminal and sends the chip external signal to the chip, where the first power voltage domain VDD and the second power voltage domain VDD _ AON may be powered down. Specifically, the third set of logic control signals includes a third control signal SH _ HV and a fourth control signal DC _ CNT, which respectively control the third flip-flop and the buffer output sub-circuit to be turned on or off through the third logic control sub-circuit. When the third control signal SH _ HV and the fourth control signal DC _ CNT are 1, the third trigger is switched on, the buffer output sub-circuit is switched on and outputs a chip external signal sent by the PAD end to the chip; when the third control signal SH _ HV and the fourth control signal DC _ CNT are low, the third contactor is closed, the buffer output sub-circuit is closed, and the output is reset.
Preferably, the first, second and third flip-flops are schmitt flip-flops. The Schmitt trigger adopts a potential triggering mode, the state of the Schmitt trigger is maintained by the potential of an input signal, and different threshold voltages exist in two different changing directions of negative decrement and positive increment of the input voltage, so that the Schmitt trigger has stronger anti-jamming capability.
As shown in fig. 5, the pull-up and pull-down resistor module includes a pull-up resistor Rup and a pull-down resistor Rdown connected in series, and a connection end of the pull-up resistor Rup and the pull-down resistor Rdown is further connected to the transmitting module, the receiving module and the PAD end; the other end of the pull-up resistor Rup is connected to the third power voltage domain VDDIO through a first switch S1, and the other end of the pull-down resistor Rdown is grounded through a second switch S2.
In a specific embodiment, the pull-up and pull-down resistance module implements a pull-up and pull-down function when a transmitting function of the transmitting module and a receiving function of the receiving module are turned off. Specifically, when pull-up is required, an enable signal is sent to the first switch S1 to close it, so as to turn on the pull-up resistor Rup; when a pull-down is required, an enable signal is sent to the second switch S2 to close it, turning on the pull-down resistor Rdown. Specifically, the first switch S1 and the second switch S2 cannot be closed at the same time.
As shown in fig. 3, 4, 5 and 6, the enable signal for controlling the pull-down and pull-up resistor module to pull up and pull down includes PU _ AON and PD _ AON in the second group of logic control signals converted by the third level conversion sub-circuit, PU _ HV and PD _ HV converted by the third level conversion sub-circuit, and PU _ VDD _ HV and PD _ VDD _ HV in the fourth group of logic control signals converted by the fifth level conversion sub-circuit. The circuit comprises a first power supply voltage domain VDD, a second power supply voltage domain VDD, a third power supply voltage domain VDDIO, a circuit, a first power supply voltage domain VDD, a second power supply voltage domain VDD, a third power supply voltage domain VDDIO, a first power supply voltage domain VDD, a second power supply voltage domain VDD, a third power supply voltage domain VDDIO, a second power supply voltage domain VDD, a third power supply voltage domain VDDIO.
Specifically, the pull-up resistor Rup and the pull-down resistor Rdown are both P-Poly resistors, and are controlled to be turned on or off through a switch tube.
As shown in fig. 1 and fig. 6, the transmitting module includes a fifth level shift sub-circuit, a fourth logic control sub-circuit and a driving sub-circuit; the fifth level conversion sub-circuit receives a fourth group of logic control signals and carries out level conversion, the converted fourth group of logic control signals are input into the fourth logic control sub-circuit, and the fourth logic control sub-circuit is used for switching on and selecting a driving gear of the driving sub-circuit or switching off the driving sub-circuit.
Specifically, as shown in fig. 6, the fourth set of logic control signals includes a first enable signal OE operating in the first power voltage domain VDD, an input signal DI operating in the first power voltage domain VDD, a shift selection signal DR, pull-up and pull-down control signals PU and PD, and OE _ HV, DI _ HV, DR _ HV, PU _ VDD _ HV and PD _ VDD _ HV are obtained after low level conversion to high level is performed by the fifth level conversion sub-circuit.
As shown in fig. 6, the driving sub-circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN 3; the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to each other and to the fourth logic control module, and the gates of the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 are connected to each other and to the fourth logic control module; the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to the third supply voltage domain VDDIO; the sources of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 are grounded; the drains of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 are connected to each other, and are connected to a terminal where the fourth logic control module, the pull-up resistor Rup, and the pull-down resistor Rdown are connected to each other, and a PAD terminal.
In a specific embodiment, the sizes of the first PMOS transistor MP1 and the first NMOS transistor MN1 are smaller than the sizes of the second PMOS transistor MP2 and the second NMOS transistor MN2, and the sizes of the second PMOS transistor MP2 and the second NMOS transistor MN2 are smaller than the sizes of the third PMOS transistor MP3 and the third NMOS transistor MN 3.
Specifically, when three groups of MOS transistors are all turned on, the driving capability of the GPIO circuit is the largest, and when only the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on, the driving capability of the GPIO circuit is the smallest. The three groups of MOS tubes included in the driving sub-circuit are used as ESD (Electro-Static discharge) protection devices, and the ESD capability of the GPIO circuit can be enhanced.
The GPIO circuit of the embodiment of the invention comprises at least 8 working modes:
the first mode of operation: the GPIO circuit is used as an input IO, the sending module is closed, and the first receiving submodule works in a first power supply voltage domain VDD. The first power supply voltage domain VDD and the second power supply voltage domain VDD _ AON are normally powered on; disconnecting the pull-up resistor Rup and the pull-down resistor Rdown, and closing the second receiving submodule and the third receiving submodule; when the first control signal SH _ VDD and the second control signal DC _ VDD are 1, the first trigger is turned on, the second level conversion sub-circuit is turned on, and at the moment, an external signal input by the PAD end is input to the Core through the first trigger and the second level conversion sub-circuit to input a signal of a first power supply voltage domain VDD. When the first control signal SH _ VDD is 0 and the second control signal DC _ VDD is 0, the first receiving submodule turns off the input function.
The second working mode is as follows: the GPIO circuit is used as an input IO, the sending module is closed, and the second receiving sub-module works in a second power supply voltage domain VDD _ AON. Normally powering on a second power supply voltage domain VDD _ AON and a third power supply voltage domain VDDIO; disconnecting the pull-up resistor Rup and the pull-down resistor Rdown, and closing the first receiving sub-module and the third receiving sub-module; the second group of logic control signals are 1, the second trigger is turned on, the fourth level conversion sub-circuit is turned on, and at the moment, an external signal input by the PAD end passes through the second trigger and the fourth level conversion sub-circuit to input a signal of a second power supply voltage domain VDD _ AON to the Core. When the second group of logic control signals is 0, the second receiving submodule closes the input function.
The third mode of operation: the GPIO circuit is used as input IO, the sending module is closed, and the third receiving submodule works in a third power supply voltage domain VDDIO. Normally powering on a third power supply voltage domain VDDIO, disconnecting a pull-up resistor Rup and a pull-down resistor Rdown, and closing a first receiving submodule and a second receiving submodule; when the third control signal SH _ HV and the fourth control signal DC _ CNT are 1, the third flip-flop is turned on, and the buffer output sub-circuit is turned on, an external signal is input to the PAD terminal, and a signal of the third power supply voltage domain VDDIO is input to the Core through the third flip-flop and the buffer output sub-circuit. When the third group of logic control signals is 0, the third receiving submodule closes the input function.
A fourth mode of operation: the GPIO circuit is used as output IO, and the receiving module is closed; disconnecting the pull-up resistor Rup and the pull-down resistor Rdown; the fourth group of logic control signals comprises a first enable signal OE working in the first power supply voltage domain VDD, an input signal DI working in the first power supply voltage domain VDD and a gear selection signal DR; when the first enable signal OE is 1, the input signal DI is used as an input of an output IO, is converted to a third power voltage domain VDDIO through the fifth level conversion sub-circuit, is sent to the driving sub-circuit, and is output by the PAD; the drive gear of the drive sub-circuit is controlled by a gear selection signal DR: when the range selection signal DR < 1: when the voltage is greater than 1, the driving capability is strongest, at the moment, the branch of the first PMOS tube MP1 and the first NMOS tube MN1 is connected, the branch of the second PMOS tube MP2 and the second NMOS tube MN2 is connected, and the branch of the third PMOS tube MP3 and the branch of the third NMOS tube MN3 are connected; when the range selection signal DR < 1: when the voltage is greater than 0, the driving capability is the second time, at the moment, the branch of the first PMOS tube MP1 and the first NMOS tube MN1 is disconnected, the branch of the second PMOS tube MP2 and the second NMOS tube MN2 is disconnected, and the branch of the third PMOS tube MP3 and the third NMOS tube MN3 is connected; when the gear selection signal DR <0:1>, the driving capability is again, at the moment, the branch of the first PMOS tube MP1 and the first NMOS tube MN1 is disconnected, the branch of the second PMOS tube MP2 and the second NMOS tube MN2 is connected, and the branch of the third PMOS tube MP3 and the third NMOS tube MN3 is disconnected; when the range selection signal DR <0: when the driving capability is the weakest, the branch of the first PMOS transistor MP1 and the first NMOS transistor MN1 is turned on, the branch of the second PMOS transistor MP2 and the second NMOS transistor MN2 is turned off, and the branch of the third PMOS transistor MP3 and the third NMOS transistor MN3 is turned off. When the first enable signal OE is 0, the transmitting module does not operate.
The fifth working mode: the GPIO circuit is used as an output-input IO to disconnect a pull-up resistor Rup and a pull-down resistor Rdown, the second receiving submodule and the third receiving submodule are closed, the sending module is switched on, and the first receiving submodule is switched on and works in a first power supply voltage domain VDD; the first enable signal OE, the first control signal SH _ VDD, and the second control signal DC _ VDD are 1, the input signal DI is used as an input of the output IO, and is converted to the third power voltage domain VDDIO by the fifth level conversion sub-circuit, and then is sent to the driving sub-circuit, and the first flip-flop receives the input and sends the input to the second level conversion sub-circuit, and the input is input to the chip by the second level conversion sub-circuit.
Sixth mode of operation: the GPIO circuit is used as an output-input IO to disconnect a pull-up resistor Rup and a pull-down resistor Rdown, the first receiving sub-module and the third receiving sub-module are closed, the sending module is switched on, and the second receiving sub-module is switched on and works in a second power supply voltage domain VDD _ AON; the first enable signal OE and the second group of logic control signals are 1, the input signal DI is used as the input of the output IO, is converted into a third power supply voltage domain VDDIO through the fifth level conversion sub-circuit and then is sent to the driving sub-circuit, and the second trigger receives the input and sends the input to the fourth level conversion sub-circuit and the fourth level conversion sub-circuit is input to the chip.
Seventh mode of operation: the GPIO circuit is used as an output-input IO to disconnect a pull-up resistor Rup and a pull-down resistor Rdown, the first receiving submodule and the second receiving submodule are closed, the sending module is switched on, and the third receiving submodule is switched on and works in a third power supply voltage domain VDDIO; the first enable signal OE and the third group of logic control signals are 1, the input signal DI is used as the input of the output IO, is converted into a third power supply voltage domain VDDIO through the fifth level conversion sub-circuit and then is sent to the driving sub-circuit, and the third trigger receives the input and sends the input to the buffer output sub-circuit, and the input is input to the chip through the buffer output sub-circuit.
The eighth mode of operation: the GPIO circuit is used as an upper pull-down resistor, the first enabling signal OE is 0, the first group of logic control signals, the second group of logic control signals and the third group of logic control signals are all 0, and the PAD end outputs a floating state to prevent electric leakage; when the enabling signal of the first switch S1 is high and the enabling signal of the second switch S2 is low, the pull-up is realized; when the enable signal of the first switch S1 is low and the enable signal of the second switch S2 is high, pull-down is realized. The first switch S1 enable signal and the second switch S2 enable signal are converted by the fifth level conversion sub-circuit and then input in the first power voltage domain VDD; the enabling signal of the first switch S1 and the enabling signal of the second switch S2 are input after being converted by the second level conversion sub-circuit when the second power supply voltage domain VDD _ AON exists; the first switch S1 enable signal and the second switch S2 enable signal are input by the third logic control sub-circuit when the third power supply voltage domain VDDIO.
The embodiment of the invention can also support working modes including open-drain output, multiplexing push-pull output and the like, and can be realized by setting different logic controls by a user.
The GPIO circuit of the embodiment of the invention realizes low power consumption management, 4-gear drive capability selection, has the functions of pull-up and pull-down resistors, can meet the output of three power domains when being used as input IO, has stronger ESD capability, comprises at least eight working modes and can meet different application environments.
The invention also provides a chip, which comprises the GPIO circuit as the pin for communicating with the outside, wherein the GPIO circuit can be used as an input IO, an output-input IO, a pull-up and pull-down resistor open-drain output, a multiplexing push-pull output and the like of the chip.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. The GPIO circuit is used for connecting a chip and realizing communication between the chip and the outside, and is characterized by comprising a sending module, a receiving module and a pull-up and pull-down resistance module, wherein the chip sends a signal to the outside of the chip through the sending module and receives a signal outside the chip through the receiving module, and the pull-up and pull-down resistance module is used for pulling up and down the chip; the receiving module comprises a first receiving submodule working in a first power supply voltage domain, a second receiving submodule working in a second power supply voltage domain and a third receiving submodule working in a third power supply voltage domain; the priority of the third power supply voltage domain is greater than that of the second power supply voltage domain, and the priority of the second power supply voltage domain is greater than that of the first power supply voltage domain.
2. The GPIO circuit of claim 1, wherein the first receive sub-module includes a first level shift sub-circuit, a first logic control sub-circuit, a first flip-flop, and a second level shift sub-circuit; the first level conversion sub-circuit receives a first group of logic control signals and carries out level conversion, the converted first group of logic control signals are input to the first logic control sub-circuit, and the first trigger is controlled to be turned on or turned off through the first logic control sub-circuit; the first trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the first trigger is started, the first trigger sends the chip external signal to the second level conversion sub-circuit and inputs the chip external signal after level conversion to the chip.
3. The GPIO circuit of claim 2, wherein the second receive sub-module includes a third level shifting sub-circuit, a second logic control sub-circuit, a second flip-flop, and a fourth level shifting sub-circuit; the third level conversion sub-circuit receives a second group of logic control signals and carries out level conversion, the converted second group of logic control signals are input to the second logic control sub-circuit, and the second trigger is controlled to be turned on or turned off through the second logic control sub-circuit; the second trigger is connected to the PAD end and receives a chip external signal through the PAD end, and when the second trigger is started, the second trigger sends the chip external signal to the fourth level conversion sub-circuit and inputs the chip external signal after level conversion to the chip.
4. The GPIO circuit of claim 3, wherein the third receive sub-module comprises a third logic control sub-circuit, a third flip-flop and a buffer output sub-circuit; the third logic control sub-circuit receives a third group of logic control signals to control the third trigger to be turned on or turned off; the third trigger is connected to the PAD end and receives a chip external signal through the PAD end, when the second trigger is started, the second trigger sends the chip external signal to the buffer output sub-circuit, and the buffer output sub-circuit inputs a signal to the chip.
5. The GPIO circuit of claim 4, wherein the first, second and third flip-flops are Schmitt flip-flops.
6. The GPIO circuit of claim 1, wherein the pull-up and pull-down resistor module comprises a pull-up resistor and a pull-down resistor connected in series, and wherein the end of the pull-up resistor connected with the pull-down resistor is further connected to the transmit module, the receive module and the PAD end; the other end of the pull-up resistor is connected to a third power supply voltage domain through a first switch, and the other end of the pull-down resistor is grounded through a second switch.
7. The GPIO circuit of claim 6, wherein the transmit module comprises a fifth level shift sub-circuit, a fourth logic control sub-circuit and a drive sub-circuit; the fifth level conversion sub-circuit receives a fourth group of logic control signals and carries out level conversion, the converted fourth group of logic control signals are input into the fourth logic control sub-circuit, and the fourth logic control sub-circuit is used for switching on and selecting a driving gear of the driving sub-circuit or switching off the driving sub-circuit.
8. The GPIO circuit of claim 7, wherein the driver sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; the gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected with each other and the fourth logic control module, and the gates of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are connected with each other and the fourth logic control module; the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected to the third power supply voltage domain; the source electrodes of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are grounded; the drain electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube are mutually connected and connected with the fourth logic control module, the end where the pull-up resistor and the pull-down resistor are connected and the PAD end.
9. The GPIO circuit of claim 1, wherein the first power supply voltage domain is a core voltage, the second power supply voltage domain is a normally-on power supply voltage, and the third power supply voltage domain is an IO voltage.
10. A chip comprising the GPIO circuit of any one of claims 1-9 as a pin to communicate externally.
CN201910884109.9A 2019-09-19 2019-09-19 GPIO circuit and chip Pending CN110618958A (en)

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