CN211043633U

CN211043633U - L VDS transmission open circuit detection circuit

Info

Publication number: CN211043633U
Application number: CN201920812948.5U
Authority: CN
Inventors: 张楠; 卢建和
Original assignee: Huizhou Desay SV Automotive Co Ltd
Current assignee: Huizhou Desay SV Automotive Co Ltd
Priority date: 2019-05-31
Filing date: 2019-05-31
Publication date: 2020-07-17
Anticipated expiration: 2029-05-31

Abstract

The application relates to an L VDS transmission open circuit detection circuit, wherein a L VDS deserializing chip is connected with a first detection circuit and a second detection circuit, the first detection circuit and the second detection circuit receive potential signals transmitted from a L VDS deserializing chip and perform on-off feedback through a first L ED lamp and a second L ED lamp so as to judge whether the circuit abnormity is a hardware problem or a software problem, and the circuit has the beneficial effects that (1) the first L ED lamp and the second L ED lamp visually feed back whether the system abnormity is a software problem or a hardware problem, so that a large amount of debugging and testing time is greatly saved, and (2) the circuit is simple in structure, obvious in effect and easy to realize, and saves a large amount of detection cost.

Description

L VDS transmission open circuit detection circuit

Technical Field

The application relates to the technical field of automotive electronics, in particular to an L VDS transmission open circuit detection circuit.

Background

With the rise of electric automobiles, the functions of automobile electronics are more and more abundant at present; the map display scheme for the vehicle-mounted liquid crystal instrument is that the map data is serialized by the navigation host computer, transmitted to the instrument and then deserialized by the instrument into data which can be processed in the instrument for display. If problems occur in the process from serialization to deserialization, whether hardware connection is in problem or software serialization is in problem or not is difficult to quickly locate, and a large amount of time is consumed for troubleshooting.

Disclosure of Invention

In order to solve the technical problems, the application provides an L VDS transmission open circuit detection circuit, which aims to position whether a L VDS deserializing chip is a software problem or a hardware problem through detection feedback of a first detection circuit and a second detection circuit, saves a large amount of debugging and testing time, and at least comprises a first detection circuit and a second detection circuit, wherein the first detection circuit is used for detecting whether software and hardware of a navigation host are abnormal, the first detection circuit is connected in series between a first potential signal output end L OCK of a L VDS deserializing chip U1 of the navigation host and a ground network, the second detection circuit is connected in series between a second potential signal output end ERR of a L VDS deserializing chip U1 of the navigation host and the ground network, and the first detection circuit and the second detection circuit carry out detection feedback by receiving potential signals from a L VDS deserializing chip U1.

Optionally, the first detection circuit comprises a first L ED lamp D1 connected in series between the first potential signal output terminal L OCK and a ground network, and the first L ED lamp D1 receives L VDS deserializing chip U1 potential signal and performs detection feedback through a lighting-up and lighting-down state.

Optionally, a first pull-up voltage VDD1 is further connected between the first L ED lamp D1 and the first potential signal output terminal L OCK, and is used for supplying power to the first L ED lamp D1.

Optionally, a first resistor R1 is further connected between the first pull-up voltage VDD1 and the loop between the first L ED lamp D1 and the first potential signal output terminal L OCK.

Optionally, when the L VDS deserializing chip U1 detects hardware abnormality of the navigation host, the first potential signal output terminal L OCK outputs a low level signal to turn off the first L ED lamp D1.

Optionally, the first pull-up voltage VDD1 has a voltage value of 3V.

Optionally, the second detection circuit comprises a second L ED lamp D2 connected in series between the second potential signal output terminal ERR and a ground network, and the second L ED lamp D2 receives L VDS deserializing chip U1 potential signal and performs detection feedback through a lighting-up and lighting-down state.

Optionally, a second pull-up voltage VDD2 is further connected between the second L ED lamp U1 and the second potential signal output terminal ERR, and is used for supplying power to the second L ED lamp D2.

Optionally, a second resistor R2 is further connected between the second pull-up voltage VDD2 and the loop of the second L ED lamp D2 and the second potential signal output terminal ERR.

Optionally, when the L VDS deserializing chip U1 detects that the navigation host is abnormal, the second potential signal output terminal ERR outputs a high level signal to turn on the second L ED lamp D2.

Optionally, the second pull-up voltage VDD2 has a voltage value of 3V.

The L VDS transmission open circuit detection circuit has the beneficial effects that (1) the system is intuitively fed back to judge whether the circuit is a hardware problem or a software problem through the first L ED lamp and the second L ED lamp, so that a large amount of debugging and testing time is greatly saved, and (2) the circuit is simple in structure, obvious in effect and easy to implement, and a large amount of detection cost is saved.

Drawings

FIG. 1 is a circuit diagram of a detection circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an L VDS chip according to an embodiment of the present application;

the detection circuit comprises a U1-L VDS deserializing chip, a L OCK first potential signal output end, an ERR second potential signal output end, a VDD1 first pull-up voltage, a VDD2 second pull-up voltage, a NAV 1L VDS _ L OCK first potential signal input end of external detection equipment, a NAV 1L VDS _ ERR second potential signal input end of the external detection equipment, a D1 first L ED lamp, a D2 second L ED lamp, a R1 first resistor and a R2 second resistor.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will make the advantages and features of the present application more readily appreciated by those skilled in the art, and thus will more clearly define the scope of the invention.

Example 1:

referring to fig. 1, the present application provides an L VDS transmission open circuit detection circuit, which aims to locate whether L VDS deserializing chip is a software problem or a hardware problem through detection feedback of a first detection circuit and a second detection circuit, so as to save a great deal of debugging and testing time, and at least comprises:

the first detection circuit is connected in series between a first potential signal output end L OCK of an L VDS deserializing chip U1 of the navigation host and a ground network and used for detecting the abnormity of software or hardware of the navigation host, the first detection circuit comprises a first L ED lamp D1 connected in series between the first potential signal output end L OCK and the ground network, and the first L ED lamp D1 receives L VDS deserializing chip U1 potential signals and carries out detection feedback through the on-off state.

A first pull-up voltage VDD1 is further connected between the first L ED lamp D1 and the first potential signal output terminal L OCK and used for supplying power to the first L ED lamp D1, a first resistor R1 is further connected between the first pull-up voltage VDD1 and a loop of the first L ED lamp D1 and the first potential signal output terminal L OCK, and the voltage value of the first pull-up voltage VDD1 is 3V.

The second detection circuit is connected between a second potential signal output end ERR of an L VDS de-string chip U1 of the navigation host and a ground network in series and used for detecting whether the navigation host is abnormal or not, the second detection circuit comprises a second L ED lamp D2 connected between the second potential signal output end ERR and the ground network in series, a second L ED lamp D2 receives a potential signal of an L VDS de-string chip U1 and carries out detection feedback through a lighting and extinguishing state, a second pull-up voltage VDD2 is further connected between the second L ED lamp U1 and the second potential signal output end ERR and used for supplying power to the second L ED lamp D2, a second resistor R2 is further connected between the second pull-up voltage VDD2 and the second L ED lamp D2 as well as the second potential signal output end ERR loop, and the voltage value of the second pull-up voltage VDD2 is 3V.

The circuit is characterized in that a first detection circuit and a second detection circuit are connected to a L VDS deserializing chip U1 and used for receiving potential signals from a L VDS deserializing chip U1 to perform detection feedback, the first detection circuit and the second detection circuit are used for performing on-off feedback through a first L ED lamp D1 and a second L ED lamp D2 by receiving the potential signals from a L VDS deserializing chip U1 to judge whether the circuit abnormity is a hardware problem or a software problem, and the first L ED lamp D1 and the second L ED lamp D2 are used for intuitively feeding back whether the system abnormity is a software problem or a hardware problem, so that a large amount of debugging and testing time is greatly saved.

Example 2:

based on embodiment 1, the detection circuit is connected to L VDS deserializing chip U1, see fig. 2, where the deserializing chip of the instrument is L VDS deserializing chip U1, and L0 VDS deserializing chip U1 is provided with a first potential signal output terminal L OCK, when a map transmission failure occurs due to a problem in any part of hardware in the deserializing chip module of the navigation host, the deserializing chip module of the instrument, and the transmission line bundle of the two, the first potential signal output terminal L OCK outputs a low level, otherwise, if all the hardware is normal, the first potential signal output terminal L OCK outputs a high level, and according to the characteristic of the first potential signal output terminal L OCK, a first detection circuit is connected in series between the first potential signal output terminal L OCK and the ground network, the first detection circuit is driven by the first potential signal output terminal L OCK level for detection feedback, and when the first potential signal output terminal L OCK is high, the first potential signal output terminal L ED lamp set in the first detection circuit is turned on.

Example 3:

based on the embodiment 2, the L VDS deserializing chip U1 is further provided with a second electric potential signal output terminal ERR, when the navigation host normally operates, the second electric potential signal output terminal ERR outputs a low level, when the navigation host causes a map transmission failure, the second electric potential signal output terminal ERR outputs a high level, according to characteristics of the second electric potential signal output terminal ERR, a second detection circuit is connected in series between the second electric potential signal output terminal and a ground network, the second detection circuit is driven by the level of the second electric potential signal output terminal ERR to perform detection feedback, and when the second electric potential signal output terminal ERR is at a high level, a second L ED lamp arranged in the second detection circuit is turned on.

Example 4:

based on embodiment 2, the detection circuit can separately adopt a first detection circuit for detecting abnormality of a VDS string chip and hardware connected to the VDS string chip U, or a software system arranged on the 0VDS string chip U and an adjacent functional module thereof, the first detection circuit includes a first 2ED lamp D connected in series between a first potential signal output terminal 1OCK and a ground network, the first 3ED lamp D receives a potential signal of the 4VDS string chip U and performs detection feedback through a lighting and extinguishing state, a first pull-up voltage VDD is further connected between the first 5ED lamp D and a first potential signal output terminal 6OCK and used for supplying power to the first 7ED lamp D, the first pull-up voltage VDD and a loop between the first 8ED lamp D and the first potential signal output terminal OCK are connected with a first resistor R1, the voltage value of the first pull-up voltage is 3v, the first lamp D is an increased detection lamp, the first resistor R is a pull-up resistor R, the first pull-up circuit is used for enhancing voltage of the first pull-up voltage VDD, and if the first led lamp D is connected with a host computer navigation software, the abnormal detection circuit detects that the first led lamp D is a failure, and if the first led lamp D is a failure, the host computer navigation software module is connected with the first pull-up voltage error detection circuit.

Example 5:

based on the embodiment 3-4, the detection circuit can also adopt the first detection circuit and the second detection circuit to carry out combined detection on the navigation host, firstly adopts the second detection circuit to judge whether the navigation host works normally, and then adopts the first detection circuit to judge whether the navigation host in an abnormal state has a software problem or a hardware problem, when the system works normally, the second potential signal output end ERR outputs a low level, the second L ED lamp D2 is in an off state, which indicates that the L VDS of the navigation host works normally, when the system works abnormally, the second potential signal output ERR outputs a high level, the second L ED lamp D2 is in an on state, if the first potential signal output end L OCK outputs a high level, and the first L D1 is in an on state, which indicates that the system software is the system software, namely the software system software arranged in the L3 VDS string U1 and the adjacent function module is used for detecting whether the hardware system abnormal problem is detected by the software system abnormality, namely, the hardware string 355 is connected with a great deal of hardware fault detection result that the hardware fault detection is detected by the first potential signal output end software, the hardware string 4642, the hardware fault detection circuit is a great deal of the hardware fault detection circuit, and the hardware fault detection circuit detects that the hardware fault is detected by the hardware fault of the hardware connected with the first potential signal output end L, and the hardware connected with the hardware connected by the hardware string L, and the hardware string 4642, and the hardware fault detection circuit is easily detected by the hardware fault detection circuit.

The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.

Claims

1. An L VDS transmission open circuit detection circuit is characterized in that the detection circuit at least comprises a first detection circuit for detecting whether software and hardware of a navigation host are abnormal and a second detection circuit for detecting whether the navigation host is abnormal, the first detection circuit is connected in series between a first potential signal output end (L OCK) of a L VDS deserializing chip (U1) of the navigation host and a ground network, the second detection circuit is connected in series between a second potential signal output End (ERR) of a L VDS deserializing chip (U1) of the navigation host and the ground network, and the first detection circuit and the second detection circuit carry out detection feedback by receiving potential signals from a L VDS deserializing chip (U1).

2. An L VDS transmission open-circuit detection circuit as claimed in claim 1, wherein the first detection circuit comprises a first L ED lamp (D1) connected in series between the first voltage signal output terminal (L OCK) and ground network, the first L ED lamp (D1) receives the voltage signal of L VDS deserializing chip (U1), and the detection feedback is performed by the on-off state.

3. An L VDS transmission open circuit detection circuit as claimed in claim 2, wherein a first pull-up voltage (VDD 1) is further connected between the first L ED lamp (D1) and the first potential signal output terminal (L OCK) for supplying power to the first L ED lamp (D1).

4. An L VDS transmission open circuit detection circuit according to claim 3, wherein a first resistor (R1) is connected between the first pull-up voltage (VDD 1) and the loop of the first L ED lamp (D1) and the first potential signal output terminal (L OCK).

5. An L VDS transmission open-circuit detection circuit according to claim 3, wherein when the L VDS deserializing chip (U1) detects hardware abnormality of the navigation host, the first L ED lamp (D1) is turned off by outputting a low signal through the first potential signal output terminal (L OCK).

6. An L VDS transmission open-circuit detection circuit as claimed in claim 1, wherein the second detection circuit comprises a second L ED lamp (D2) connected in series between the second voltage signal output terminal (ERR) and the ground network, the second L ED lamp (D2) receives L VDS de-string chip (U1) voltage signal, and the detection feedback is performed by the ON/OFF state.

7. An L VDS transmission open circuit detection circuit as claimed in claim 6, wherein a second pull-up voltage (VDD 2) is further connected between the second L ED lamp (D2) and the second potential signal output terminal (ERR) for supplying power to the second L ED lamp (D2).

8. An L VDS transmission open circuit detection circuit according to claim 7, wherein a second resistor (R2) is connected between the second pull-up voltage (VDD 2) and the loop of the second L ED lamp (D2) and the second potential signal output terminal (ERR).

9. An L VDS transmission open-circuit detection circuit according to claim 6, wherein when the L VDS deserializing chip (U1) detects abnormality of the navigation host, the second L ED lamp (D2) is turned on by outputting a high level signal through the second potential signal output terminal (ERR).