CN220913285U - Signal transmission processing circuit and test system - Google Patents
Signal transmission processing circuit and test system Download PDFInfo
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- CN220913285U CN220913285U CN202321097718.8U CN202321097718U CN220913285U CN 220913285 U CN220913285 U CN 220913285U CN 202321097718 U CN202321097718 U CN 202321097718U CN 220913285 U CN220913285 U CN 220913285U
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- 238000012360 testing method Methods 0.000 title claims abstract description 99
- 238000012545 processing Methods 0.000 title claims abstract description 83
- 230000008054 signal transmission Effects 0.000 title claims abstract description 39
- 238000004891 communication Methods 0.000 claims abstract description 23
- 238000001514 detection method Methods 0.000 claims description 18
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 230000000739 chaotic effect Effects 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The utility model discloses a signal transmission processing circuit and a test system, wherein the signal transmission processing circuit comprises a processing unit and a plurality of connecting units for electrically connecting a test main board; the connecting unit is provided with a first signal interface and is used for outputting a test result of the test main board; the processing unit is provided with a plurality of second signal interfaces and a communication interface for communicating with the upper computer, the second signal interfaces are in one-to-one correspondence with the connecting units, and the second signal interfaces are electrically connected with the first signal interfaces of the corresponding connecting units; the processing unit is used for outputting the test results received by each second signal interface from the communication interface. According to the technical scheme, the number of transmission lines is greatly reduced, the lines are simplified, and the problems that the lines are very chaotic and complex when a plurality of test mainboards are tested are effectively solved; meanwhile, the number of the circuits is greatly reduced, so that the circuit cost is reduced.
Description
Technical Field
The present utility model relates to the field of product testing technologies, and in particular, to a signal transmission processing circuit and a testing system.
Background
Product testing is required before the chip product leaves the factory. For example, when testing an LPDDR (Low Power Double DATA RATE SDRAM) chip, the LPDDR chip is usually assembled on a test motherboard for testing, and the test motherboard feeds back the test result of the LPDDR chip to an upper computer (e.g., a server) through a serial port. In order to improve the testing efficiency of chips, a plurality of test boards are generally adopted to test a plurality of chips simultaneously, and when the test boards are many, serial transmission lines which need to be connected to a server are very many, so that lines are very chaotic and complex, and the line cost is too high.
Disclosure of utility model
The utility model provides a signal transmission processing circuit and a testing system, which aim to simplify a circuit when a plurality of chips are tested simultaneously and reduce the circuit cost.
In order to achieve the above object, the signal transmission processing circuit provided by the present utility model includes a processing unit and a plurality of connection units for electrically connecting to a test motherboard;
The connecting unit is provided with a first signal interface and is used for outputting a test result of the test main board;
The processing unit is provided with a plurality of second signal interfaces and a communication interface for communicating with the upper computer, the second signal interfaces are in one-to-one correspondence with the connecting units, and the second signal interfaces are electrically connected with the first signal interfaces of the corresponding connecting units;
the processing unit is used for outputting the test results received by each second signal interface from the communication interface.
In some embodiments, the signal transmission processing circuit further includes a plurality of level conversion units, the level conversion units are in one-to-one correspondence with the connection units, and the first signal interfaces of the connection units are electrically connected with the second signal interfaces through the corresponding level conversion units.
In some embodiments, the signal transmission processing circuit further includes a serial port-to-network port unit, the communication interface is electrically connected to a serial port end of the serial port-to-network port unit, and a network port end of the serial port-to-network port unit is connected to the host computer.
In some embodiments, the connection unit further has a power supply input terminal and an enable terminal for electrically connecting with a power supply, and the processing unit further includes a plurality of control signal terminals, the control signal terminals being in one-to-one correspondence with the connection units, and the control signal terminals being electrically connected with the enable terminals of the corresponding connection units.
In some embodiments, the signal transmission processing circuit further includes a plurality of detection units electrically connected to the processing units, the detection units are in one-to-one correspondence with the connection units, each detection unit is electrically connected to a power supply input end of the corresponding connection unit, and the detection unit is used for detecting a power supply condition of the power supply input end and feeding back to the processing unit.
In some embodiments, the signal transmission processing circuit further includes an IIC bus electrically connected to the processing unit, and the power supply detected by each of the detecting units is fed back to the processing unit through the IIC bus.
The utility model also provides a test system which comprises a plurality of test mainboards and the signal transmission processing circuit, wherein the test mainboards are correspondingly connected with the connecting units one by one.
In some embodiments, the test system further comprises a host computer, and the communication interface is connected with the host computer.
When the technical scheme of the utility model is applied to a scene of simultaneous testing of a plurality of test mainboards, each connecting unit is respectively and correspondingly and electrically connected with one test mainboard, each test mainboard outputs the test result of the test mainboards on a chip (or other devices) to the processing unit through the first signal interface of the connecting unit, and the processing unit receives the test result output by each test mainboard through the corresponding connecting unit and then uniformly outputs each test result from the communication interface to be fed back to an upper computer (such as a server, an industrial computer and the like). Therefore, by adopting the technical scheme of the signal transmission circuit, the test results of a plurality of test mainboards can be fed back to the upper computer through one communication interface, and only one transmission line is needed. Meanwhile, the number of the circuits is greatly reduced, so that the circuit cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a first embodiment of a signal transmission processing circuit according to the present utility model;
fig. 2 is a schematic diagram of a signal transmission processing circuit according to a second embodiment of the present utility model;
FIG. 3 is a schematic diagram of a signal transmission processing circuit according to a third embodiment of the present utility model;
Fig. 4 is a schematic diagram of a signal transmission processing circuit according to a fourth embodiment of the present utility model;
Fig. 5 is a schematic diagram of a signal transmission processing circuit according to a fifth embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The utility model provides a signal transmission processing circuit.
Referring to fig. 1, in the present embodiment, the signal transmission processing circuit includes a processing unit 10 and a plurality of connection units 20 for electrically connecting a test motherboard; the connection unit 20 has a first signal interface 21 for outputting a test result of the test motherboard; the processing unit 10 is provided with a plurality of second signal interfaces 11 and a communication interface 12 for communicating with the upper computer, the second signal interfaces 11 are in one-to-one correspondence with the connecting units 20, and the second signal interfaces 11 are electrically connected with the first signal interfaces 21 of the corresponding connecting units 20; the processing unit 10 is configured to output the test results received by the respective second signal interfaces 11 from the communication interface 12.
When the signal transmission circuit of this embodiment is applied to a scenario where multiple test boards are tested simultaneously, each connection unit 20 is electrically connected to one test board, each test board outputs the test result of the test board on a chip (or other devices) to the processing unit 10 through the first signal interface 21 of the connection unit 20, and after receiving the test result output by each test board through the corresponding connection unit 20, the processing unit 10 outputs each test result from the communication interface 12 in a unified manner, so as to feed back the test result to an upper computer (e.g., a server, an industrial personal computer, etc.). Therefore, by adopting the technical scheme of the signal transmission circuit of the embodiment, the test results of a plurality of test mainboards can be fed back to the upper computer through one communication interface 12, and only one transmission line is needed. Meanwhile, the number of the circuits is greatly reduced, so that the circuit cost is reduced.
In some embodiments, the connection unit 20 may employ a multi-PIN connector, such as a 15PIN connector. Of course, in other embodiments, the connection unit 20 may be other connection devices or connection circuits.
Referring to fig. 2, in some embodiments, the signal transmission processing circuit further includes a serial port to network port unit 30, where the communication interface 12 (which is a serial port) is electrically connected to a serial port end of the serial port to network port unit 30, and the network port end of the serial port to network port unit 30 is used to connect to an upper computer.
The signal transmission processing circuit of the embodiment further adopts the serial port to network port unit 30 to convert the multiple groups of test results output by the communication interface 12 into network port communication signals to be output from the network port end for transmission to the upper computer; the network port end is connected with the upper computer through a network cable, so that the signal can be transmitted for a longer distance.
Of course, in other embodiments, the serial port to network port unit 30 may be a part of the processing unit 10, for example, the processing unit 10 may be a single chip microcomputer with a serial port to network port function.
Referring to fig. 3, in some embodiments, the signal transmission processing circuit further includes a plurality of level shift units 40, where the level shift units 40 are in one-to-one correspondence with the connection units 20, and the first signal interfaces 21 of the connection units 20 are electrically connected to the second signal interfaces 11 through the corresponding level shift units 40.
Since most of test result signals output by the test motherboard generally do not exceed 1.8V level signals, and when the processing unit 10 adopts a hardware module such as a single chip microcomputer, the level signals are generally 3.3V level signals, the level conversion unit 40 is added between the first signal interface 21 of the connection unit 20 and the second signal interface 11 of the processing unit 10, and the level conversion unit 40 converts the signals output by the first signal interface 211.8V level signals into 3.3V level signals and outputs the 3.3V level signals to the second signal interface 11. The level shift unit 40 may employ an SN74LVC2G07 chip. Of course, the level conversion unit 40 may also convert level signals of other sizes according to the different selection of the test motherboard and the different selection of the processing unit 10, so as to convert the level signal output by the first signal interface 21 into a level signal that can be identified by the processing unit 10.
Of course, in other embodiments, the level conversion unit 40 may also be a part built in the processing unit 10, for example, the processing unit 10 may be a single chip microcomputer with a level conversion function for level signals received by the second signal interface 11.
Referring to fig. 4, in some embodiments, the connection unit 20 further has a power supply input terminal 22 and an enable terminal 23 for electrically connecting with a power source, and the processing unit 10 further includes a plurality of control signal terminals 13, where the control signal terminals 13 are in one-to-one correspondence with the connection units 20, and the control signal terminals 13 are electrically connected with the enable terminals 23 of the corresponding connection units 20.
The enabling terminal 23 may be used to control power-up and power-down of the test boards, so that the processing unit 10 may control power-up and power-down of each test board by sending level signals with different potentials to the enabling terminal 23 through the control signal terminal 13, for example, when the control signal terminal 13 sends a first potential signal (e.g., a high level signal) to the enabling terminal 23, the enabling terminal 23 powers up the test board, and when the control signal terminal 13 sends a second potential signal (e.g., a low level signal) to the enabling terminal 23, the enabling terminal 23 powers down. The processing unit 10 may make the control signal terminal 13 output a corresponding level signal according to the received instruction (the instruction may be an instruction transmitted by the upper computer through the communication interface 12, or may be an instruction sent by other control devices to the processing unit 10), so as to control the test start and shutdown of the test motherboard. The test motherboard may be automatically tested after power-on, and the test result is transmitted to the singlechip through the first signal interface 21 of the connection unit 20 after the test is completed.
Referring to fig. 5, in some embodiments, the signal transmission processing circuit further includes a plurality of detection units 50 electrically connected to the processing unit 10, where the detection units 50 are in one-to-one correspondence with the connection units 20, and the detection units 50 are electrically connected to the power supply input terminals 22 of the corresponding connection units 20; the detecting unit 50 is configured to detect a power supply condition of the power supply input terminal 22, and feed back the power supply condition to the processing unit 10. The power supply input terminal 22 of the detecting unit 50 is configured to be connected to a power source (e.g. a 5V power source), and the power supply condition of the power supply input terminal 22 detected by the detecting unit 50 may include: one or more of current, voltage, power consumption of the power supply input 22.
In this embodiment, the plurality of detection units 50 are provided to detect the power supply condition of each test motherboard and feed back the power supply condition to the processing unit 10, so that the processing unit 10 can also feed back the power supply condition of the test motherboard to the upper computer along with the test result through the communication interface 12, or feed back the power supply condition of each test motherboard in the test process through the communication interface 12 in real time, so that the upper computer can know in time that the power supply condition of each test motherboard is abnormal or unstable when the power supply condition of the test motherboard occurs, and then can timely perform power supply adjustment and repair on the test motherboard with abnormal or unstable power supply, thereby ensuring the accuracy and reliability of the test result of the test motherboard.
In some embodiments, the detection unit 50 may employ INA219 current detection chips.
In some embodiments, the signal transmission processing circuit further includes an IIC bus 60 electrically connected to the processing unit 10, and the power supply detected by each detecting unit 50 is fed back to the processing unit 10 through the IIC bus 60, i.e. each detecting unit 50 is electrically connected to the IIC bus 60, and outputs are transmitted to the processing unit 10 through the IIC bus 60. In this embodiment, by electrically connecting each detection unit 50 by using one IIC bus 60, the power supply condition data signal fed back by each detection unit 50 is received, and power supply detection is implemented by using the least wire harness, so that simplification of the circuit is further ensured.
It should be noted that, the embodiments of the signal transmission circuit of the present application may be combined arbitrarily on the premise that there is no contradiction between the embodiments. In addition, all the units in the above embodiments of the signal transmission processing circuit of the present application may be disposed on the same circuit board, as a whole circuit board structure, or each unit may be separately disposed in a plurality of circuit boards.
The utility model further provides a test system, which comprises a plurality of test mainboards and the signal transmission processing circuit, wherein the specific structure of the signal transmission processing circuit refers to the embodiment, and the test system adopts all the technical schemes of all the embodiments of the signal transmission processing circuit, so that the test system at least has all the beneficial effects brought by the technical schemes of the embodiments, and the detailed description is omitted. The test main board is correspondingly connected with the connecting units one by one; optionally, the connection unit adopts a 15PIN connector, and the corresponding test main board is plugged with the 15PIN connector through a 15PIN terminal.
In some embodiments, the test system further comprises a host computer, and the communication interface is connected with the host computer. The user can send instructions to the processing unit through the upper computer, so that the processing unit controls the starting and closing of the test main boards, and the user can clearly line the test conditions of all the test main boards through the test result signals sent by the processing unit and the power supply condition data of the test main boards and realize the simultaneous test and monitoring of a plurality of test main boards.
The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.
Claims (8)
1. A signal transmission processing circuit is characterized by comprising a processing unit and a plurality of connecting units for electrically connecting a test main board;
The connecting unit is provided with a first signal interface and is used for outputting a test result of the test main board;
The processing unit is provided with a plurality of second signal interfaces and a communication interface for communicating with the upper computer, the second signal interfaces are in one-to-one correspondence with the connecting units, and the second signal interfaces are electrically connected with the first signal interfaces of the corresponding connecting units;
the processing unit is used for outputting the test results received by each second signal interface from the communication interface.
2. The signal transmission processing circuit according to claim 1, further comprising a plurality of level shift units, wherein the level shift units are in one-to-one correspondence with the connection units, and wherein the first signal interfaces of the connection units are electrically connected to the second signal interfaces via the corresponding level shift units.
3. The signal transmission processing circuit of claim 1, further comprising a serial port-to-network port unit, wherein the communication interface is electrically connected to a serial port end of the serial port-to-network port unit, and a network port end of the serial port-to-network port unit is connected to the host computer.
4. A signal transmission processing circuit according to any one of claims 1 to 3, wherein the connection unit further has a power supply input terminal and an enable terminal for electrically connecting with a power supply, the processing unit further comprising a plurality of control signal terminals, the control signal terminals being in one-to-one correspondence with the connection units, the control signal terminals being electrically connected with the enable terminals of the corresponding connection units.
5. The signal transmission processing circuit according to claim 4, further comprising a plurality of detection units electrically connected to the processing units, wherein the detection units are in one-to-one correspondence with the connection units, each detection unit is electrically connected to a power supply input end of the corresponding connection unit, and the detection unit is configured to detect a power supply condition of the power supply input end and feed back to the processing unit.
6. The signal transmission processing circuit of claim 5, further comprising an IIC bus electrically connected to the processing unit, wherein the power detected by each of the detection units is fed back to the processing unit via the IIC bus.
7. A test system comprising a plurality of test boards and the signal transmission processing circuit according to any one of claims 1 to 6, the test boards being connected to the connection units in one-to-one correspondence.
8. The test system of claim 7, further comprising a host computer, wherein the communication interface is coupled to the host computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321097718.8U CN220913285U (en) | 2023-05-08 | 2023-05-08 | Signal transmission processing circuit and test system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321097718.8U CN220913285U (en) | 2023-05-08 | 2023-05-08 | Signal transmission processing circuit and test system |
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| Publication Number | Publication Date |
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| CN220913285U true CN220913285U (en) | 2024-05-07 |
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| CN202321097718.8U Active CN220913285U (en) | 2023-05-08 | 2023-05-08 | Signal transmission processing circuit and test system |
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| CN (1) | CN220913285U (en) |
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- 2023-05-08 CN CN202321097718.8U patent/CN220913285U/en active Active
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