JP2015184935A - I2c bus arbitration system and arbitration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an I2C bus arbitration system in which a FW of a BMC issues a command with an Arbitration winning data format on a Slave address setting device and acquires priority, therefore a selector switch does not have to be used and BIOS does not have to be modified, and cost is not increased significantly.SOLUTION: The I2C bus arbitration system comprising the BMC, CPU, and I2C bus, comprises: an address setting part which is coupled to the I2C bus and sets a predetermined address; and a control part disposed on the BMC and controls the I2C bus. The control part controls the address setting part and makes the address setting part output a predetermined command.

Description

  The present invention relates to an arbitration system that enables order control of an I2C (Inter-Integrated Circuit) bus, and more particularly, to an arbitration system that always obtains the priority of an I2C bus.

  In addition to the CPU, the server is equipped with a controller called BMC (Base Management Controller), which initializes and monitors the status of each module such as the memory, chip, and fan that make up the server. Realized.

  The FW (firmware) of the BMC operating on the BMC and the basic input / output system (BIOS) operating on the CPU use an I2C bus which is a standard specification in order to access each module. The I2C bus performs communication using two signal lines of serial data (SDA) and serial clock (SCL). This bus is shared between the BIOS and BMC FW, but the right to use the bus is arbitrated by the protocol of the I2C bus.

  This arbitration method is a method in which the access that has started first is prioritized. However, when access is started at the same timing, a priority is given to a device that has continuously issued Low by SDA. With this arbitration method, arbitration can be performed in command units.

  Although the I2C bus has an arbitration function in units of commands, it is impossible to control the order of commands in a single unit. For example, assuming online installation of a memory riser board, first, the BMCFW performs initialization processing of the installed board, and tries to start the BIOS processing after completion of the initialization processing. However, since the arbitration of the I2C bus is an arbitration in units of commands, there is a possibility that the process may be started from the BIOS before the BMCFW initialization is completed.

  In order to avoid such a situation, order control is performed to block the BIOS path until the BMCFW processing is completed via a selector switch between the path from the I2C BMCFW and the path from the BIOS. There was a thing. In addition, there is a method in which the BIOS is modified and the BIOS information collection is waited until a message indicating that the BMCFW processing has been completed is received from the communication path between the BIOS and the BMCFW.

  However, the use of a selector switch or remodeling the BIOS has led to an increase in the cost of the device, which has been a problem.

  As a technique related to the above, Patent Document 1 is provided with a memory and a master for storing attribute information for the purpose of performing arbitration with an easy configuration, and a plurality of requests for access to the master's memory are received. And an arbitration control unit that is configured by hardware, arbitrates an access request received by each channel, permits access to the memory of one selected access request, and determines the access request. .

Japanese Patent No. 5261993

  However, Patent Document 1 has a problem that a sequence control unit, a channel arbitration control unit, a memory access control unit, a memory, and the like are necessary.

  The object of the present invention is to provide an I2C bus arbitration system that does not lead to a significant increase in cost without using a selector switch or modifying the BIOS.

  In the present invention, in order to solve the above problem, in an arbitration system of an I2C bus including a BMC, a CPU, and an I2C bus, an address setting unit that is connected to the I2C bus and sets a predetermined address is provided in the BMC. And a control unit that controls the I2C bus, and the control unit controls the address setting unit to output a predetermined command.

  In the present invention, in order to solve the above problem, in the arbitration method of the I2C bus including the BMC, the CPU, and the I2C bus, a step of connecting to the I2C bus and setting a predetermined address is provided in the BMC. A step of controlling the I2C bus, and a step of controlling the I2C bus and outputting a predetermined command.

  According to the present invention, it is possible to provide an I2C bus arbitration system that does not lead to a significant increase in cost without using a selector switch or modifying the BIOS.

It is a block diagram which shows the structure of the arbitration system of I2C bus in embodiment of this invention. It is a figure which shows the example of the data format in embodiment of this invention. It is a flowchart which shows operation | movement of BMCFW in embodiment of this invention. It is a figure explaining the condition which acquires the priority of an I2C bus | bath using the arbitration winning format in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The configuration of the I2C bus arbitration system in this embodiment will be described with reference to FIG.

  FIG. 1 is a block diagram illustrating a configuration of an I2C bus arbitration system according to the present embodiment.

  In FIG. 1, the server device 1 is assumed to be a device including modules necessary as a general computer, such as a CPU, a memory, a chip set, a disk, and an expansion card. In FIG. 1, a module centered on the I2C bus 2 is shown.

  The server device 1 is equipped with a BMC 3 for strengthening the management function, and the CPU 4 and the BMC 3 and a module constituting the server, in this case, a memory riser board 6 are connected by an I2C bus 2 as an example. Further, the memory riser board 6 and the BMC 3 are connected by a presence dedicated signal line 8 for notifying the BMC 3 of the presence when the memory riser board 6 is maintained online. A plurality of DIMMs (Dual Inline Memory Modules) 7 are mounted on the memory riser board 6. The CPU 4 is equipped with a BIOS 10, and the BMC 3 is equipped with a BMCFW 9 as a control unit.

  Further, the youngest slave address setting device 5 for acquiring priority is connected to the I2C bus as an address setting unit. In the youngest slave address setting device 5, an arbitration winning data format is created by an instruction from the BMCFW 9. In this embodiment, the youngest slave address setting device 5 for acquiring priority is arranged outside the BMC. However, the device 5 is not necessarily independent from the BMC 3 and is mounted as a part of the BMC 3. You can also.

  The operation of the I2C bus arbitration system in this embodiment will be described with reference to FIGS. 2, 3, and 4. FIG. 2 shows an example of the data format of this embodiment. FIG. 3 is a flowchart showing the operation of the BMCFW in this embodiment. FIG. 4 is an example of a signal waveform of data according to the present embodiment.

  First, the normal I2C bus data format 100 will be described with reference to FIG. 2. In the normal data format, both the first “S”, that is, the slave address 101 after the start condition (communication start) and the next slave address 102 are described. Set the address of the device to be accessed.

  When I2C bus arbitration is performed between these data formats, the slave address 101 is younger (more 0s are counted from the beginning of the bit sequence) because priority is obtained by issuing a longer 0 by SDA from the arbitration rules. ) Gets I2C bus priority.

  Therefore, in this embodiment, a command is output to the I2C bus 2 in the arbitration winning data format 110. In the slave address 111 after the Start Condition, a number smaller than the address of the device existing in the device targeted by the arbitration system, that is, the server device 1 is designated. As a result, priority can always be obtained. The address of the device to be accessed is set in the slave address 112. In order to set the above young number in the slave address 111, the youngest number slave address setting device 5 for obtaining priority is prepared, and a number younger than the address of the device existing in the server apparatus 1 is assigned.

  Further, the BMC FW 9 obstructs communication such as the BIOS 10 with the Arbitration winning data format command, but in order to monitor and obstruct the Start Condition, it is necessary to know the implementation of each module before the BIOS. The BMC 3 and each DIMM 7 are connected by the presence dedicated signal line 8, and the presence arrives at the BMC within a time within one clock of the I2C bus 2.

  On the other hand, since the BIOS 10 detects the presence of a newly installed module by polling via the I2C bus 2, the BMCFW 9 always knows the presence of the newly installed module earlier than the BIOS 10. This relationship is established at the first time, but since the BMCFW 9 performs other processing from the next time, there is a possibility that the command from the BIOS 10 will arrive at the device for which the BMCFW 9 is being initialized.

  Therefore, taking the case where the memory riser board 6 is mounted as an example, the sequence control operation by the BMCFW 9 will be described with reference to FIG.

  When the memory riser board 6 is mounted (S201), the presence of the memory riser board is notified to the BMC 3 via the presence dedicated signal line 8 (S202).

When the BMCFW 9 detects the presence of a new device (S202), it observes the SDA on the I2C bus 2, and when a start condition from another device including the BIOS 10 is generated (S203) (communication start in I2C), the arbitration winning format The interference command is transmitted to the I2C bus 2 (S204), and the command transmission of other devices is suppressed.
That is, the interference command is continuously transmitted until another device is not communicating on the I2C bus 2. Here, the interference command is a command for suppressing command transmission of another device.

  If the other device is not communicating, a command for processing the BMCFW 9 is transmitted in the arbitration winning format in order not to be disturbed by the other device (S205).

  When the initialization process of the memory riser board 6 by the BMC FW 9 is completed (S206), transmission of a command that interferes with communication from other devices (S204) is stopped (S207), and the presence notification waiting state due to the implementation of a new device is stopped. Return to (S208).

  Next, a situation where the priority of the I2C bus is acquired using the arbitration winning format will be described with reference to FIG.

  Assuming that the youngest address of the normal device in the apparatus is 0010000, it is necessary to set a younger address than the priority acquisition device address, and 0001111 is set.

  When BMCFW 9 obstructs access to a device having the youngest address of the BIOS with a command using the arbitration winning format, when BMCFW 9 finds a start condition in SDA, it issues a command in the arbitration winning format.

In the example of FIG. 4, the data format issued by the BIOS is “slave address” immediately after the start condition is 0010000, and the arbitration winning format issued by the BMCFW 9 is “slave address” is 0001111. BMCFW 9 tries to issue 0 while trying to issue 1.
At this time, the BMCFW 9 can acquire the priority according to the arbitration rule of the I2C bus in which the one that continues to output 0 gets the priority.

  As described above, when the BMCFW finds the Start Condition in the SDA, the BMCFW instructs the device for setting the lowest slave address, issues a command in the Arbitration winning data format, and acquires the priority.

As described above, according to the present embodiment, the FW of the BMC is a slave address setting device and issues a command in the arbitration winning data format to obtain the priority. It is possible to provide an I2C bus arbitration system that does not lead to a large cost increase without modification.
That is, since the slave address 101 should be changed to the lowest address 111 of the priority acquisition device, the cost is not greatly increased.

  The present invention is not limited to the above-described embodiment, and can be implemented with various changes and modifications without departing from the gist of the present invention.

  The present invention can be used for a server that is controlled by a BMC using an I2C bus.

1 Server device 2 I2C bus 3 BMC
4 CPU
5 Youngest number slave address setting device 6 Memory riser board 7 DIMM
8 Presence dedicated signal line 9 BMCFW
10 BIOS
101 slave address
111 Youngest address of priority acquisition device

Claims (10)

In an I2C bus arbitration system comprising a BMC, a CPU, and an I2C bus,
An address setting unit connected to the I2C bus for setting a predetermined address;
A controller provided in the BMC for controlling the I2C bus;
Have
The I2C bus arbitration system, wherein the control unit controls the address setting unit to output a predetermined command.   The arbitration system for an I2C bus according to claim 1, wherein the predetermined command is output to the I2C bus.   3. The I2C bus arbitration system according to claim 1, wherein the predetermined command is processed with the highest priority in the I2C bus.   The control unit according to any one of claims 1 to 3, wherein when the I2C bus detects a communication start signal, the control unit controls the address setting unit to output the predetermined command. I2C bus arbitration system.   5. The I2C bus arbitration according to claim 1, wherein, when an external signal is detected, the control unit controls the address setting unit to output the predetermined command. 6. system.   6. The arbitration system for an I2C bus according to claim 1, wherein the predetermined command designates an address that is younger than an address of a device existing in the arbitration target apparatus.   7. The arbitration system for an I2C bus according to claim 6, further comprising a presence dedicated signal line that connects a device that exists in an arbitration target device and the control unit.   8. The I2C according to claim 1, wherein the control unit continues to transmit an interference command until a device other than the BMC existing in the arbitration target device is not communicating. 9. Bus arbitration system.   9. The arbitration system for an I2C bus according to claim 1, wherein the disturbing command specifies an address that is younger than an address of a device existing in the arbitration target apparatus. In an I2C bus arbitration method comprising a BMC, a CPU, and an I2C bus,
Connected to the I2C bus and setting a predetermined address;
Provided in the BMC and controlling the I2C bus;
Have
A method of arbitrating an I2C bus, comprising the step of controlling the I2C bus and outputting a predetermined command.

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