JP6416488B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of executing DMA transfer via a bus.

  DMA (Direct Memory Access) is a technique for transferring data between components via a bus without using a processor in a computer system. In such data transfer by DMA (hereinafter referred to as “DMA transfer”), when a data transfer request is generated in the processor, the processor gives a data transfer instruction to the DMA controller, and the DMA controller receives the data transfer instruction. Based on this, data transfer processing is performed independently of the processing of the processor. When the transfer process is completed, the DMA controller interrupts the CPU to notify the completion of the transfer process. Generally, a processor or a DMA controller controls a bus or a bus IP to access a memory or the like, and is therefore referred to as a “bus master” or “initiator”. Called.

  For example, the following Patent Document 1 is a data transfer device that performs data transfer via a bus, and DMA-transfers the data to a device controller that writes data to a target device and the device controller via the bus, Disclosed is a data transfer device including an initiator core 11 that outputs a transfer completion notification request signal to the device controller. When the device controller receives the transfer completion notification request signal, the device controller outputs a transfer completion notification signal with all writing of the data to the target device.

JP 2009-277004 A

  When a processor or a DMA controller that operates as a bus master accesses a memory such as an SRAM via the bus IP, for example, a conflict of the bus IP may occur. That is, processor accesses (eg, read / write) typically have a higher priority than those of the DMA controller, and DMA controller accesses that occur during processor access are executed after the processor access is completed. Is done. In order to guarantee data consistency, when write access control to the memory by the DMA controller occurs, the processor needs to be in a wait state until the write access control ends and an interrupt is generated. When the DMA controller receives a notification of the end of data transfer to the memory from the bus IP, the DMA controller interrupts the processor, and the processor resumes execution upon receiving the interrupt.

  However, it may take several clocks from the time when the DMA controller performs the write access control of the data to the memory until the notification of the end of the data transfer is received from the bus IP. Actually, latency occurs with respect to write access control.

  Further, even when the DMA controller does not compete with the processor and it is known that the access is completed within a predetermined time, the DMA controller is based on the data transfer completion notification from the bus IP. Similarly, an undesirable latency occurred as well.

  Therefore, an object of the present invention is to provide a semiconductor device capable of improving the latency in DMA transfer.

  More specifically, the present invention improves the latency by sending a notification of the end of data transfer early in write access control by DMA transfer between the DMA controller and the memory connected via the bus IP. An object of the present invention is to provide a semiconductor device that can be realized.

  The present invention for solving the above-described problems is configured to include the following invention specific items or technical features.

  The present invention according to an aspect includes at least one processor operating as a bus master and at least one memory operating as a bus slave, connected to be able to transfer data according to a predetermined bus protocol based on a request / response via a bus IP. And a DMA controller that operates as the bus master. The semiconductor device is connected to the at least one processor and the DMA controller and configured to behave the same as the bus IP, and is connected to the dummy bus IP and behaves the same as the memory. A dummy memory configured as described above, the DMA controller, and a bus control circuit provided between the bus IP and the dummy bus IP. The dummy bus IP sends a preceding response based on the request issued by the DMA controller to the bus control circuit. The bus control circuit sends a response to the request to the DMA controller based on the preceding response sent from the dummy bus IP.

  In particular, the dummy bus IP sends the preceding response to the bus control circuit based on a write request issued by the bus master, and the bus control circuit based on the preceding response sent from the dummy bus IP, A write response to the write request can be sent to the DMA controller.

  Thereby, in the semiconductor device, when a write access is issued from the DMA controller to the memory, a pseudo write response can be returned to the DMA controller without waiting for a write response from the memory. become able to. Therefore, the DMA controller can immediately terminate the write access to the memory, and the latency is improved.

  The DMA controller may interrupt the processor when receiving the write response to the write request.

  The dummy bus IP may send the preceding response to the bus control circuit at the same timing as when the bus IP issues the request to the memory based on a request issued by the bus master.

  The dummy bus IP may be configured to ignore a data body according to a request issued by the bus master. Accordingly, the dummy memory is configured not to have a memory cell that stores a data body according to the request issued by the bus master, while issuing a response to the request to the dummy bus IP. Can be configured.

  The semiconductor device may further include a first timing adjustment circuit provided between the at least one processor and the DMA controller and the dummy bus IP.

  When the bus control circuit receives a true write response to the request issued by the memory via the bus IP after sending the write response based on the preceding response to the DMA controller, Control may be performed so that the true write response is not sent to the DMA controller.

  Further, when the bus control circuit determines that there is another request issued by the bus master that precedes the write request when the preceding response sent from the dummy bus IP is received, Instead of a write response to the write request based on the preceding response, a true write response to the write request issued by the memory received via the bus IP may be sent to the DMA controller.

  Furthermore, the bus control circuit may send the true write response to the DMA controller after sending a response to the other request to the bus master.

  The bus control circuit also includes a buffer for temporarily storing a request issued by the bus master, a response issued by the memory and received via the bus IP, and a correspondence between the request stored in the buffer. According to the relationship, a response control unit may be provided that controls to send a predetermined response to the request issued by the bus master to the bus master.

  The bus control circuit may further include a second timing adjustment circuit that adjusts a timing for storing a request issued by the bus master in the buffer.

  Further, the semiconductor device monitors at least one bus monitor that monitors the number of write requests issued by the at least one processor and the number of write responses issued by the dummy memory received via the dummy bus IP. A circuit may further be provided. When the bus monitoring circuit determines that there is no write request currently being processed from the at least one processor to the memory by the bus monitoring circuit, at the time when one write request is issued by the DMA controller. A write response to the one write request can be sent to the DMA controller.

  In the case where a plurality of bus monitoring circuits are provided in the semiconductor device, each of the plurality of bus monitoring circuits monitors the number of write requests issued by a corresponding one of the plurality of processors. obtain.

  The semiconductor device may include a plurality of the memories and a plurality of dummy memories corresponding to the plurality of memories. The dummy bus IP can send the preceding response to the bus control circuit based on a write access to each of the plurality of dummy memories issued by the bus master.

  Further, the present invention according to another aspect can be grasped as a method invention.

  In this specification and the like, the means does not simply mean a physical means, but includes a case where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

  According to the present invention, a semiconductor device capable of improving the latency in DMA transfer is realized.

  More specifically, according to the present invention, when a write request is issued from the DMA controller to the memory, a pseudo write response is returned to the DMA controller without waiting for the write response from the memory. Therefore, the DMA controller can immediately terminate the write access to the memory, and hence the latency in the semiconductor device can be improved.

  Further, according to the present invention, the dummy bus IP and the dummy memory introduced for improving the latency do not need to reproduce all the circuit configurations of the original bus IP and the memory, and therefore, while avoiding an increase in circuit scale, A semiconductor device capable of improving the latency is realized.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a block diagram explaining an example of schematic structure of the semiconductor device concerning one embodiment of the present invention. It is a block diagram which shows an example of schematic structure of bus | bath IP of the semiconductor device which concerns on one Embodiment of this invention. It is a block diagram which shows an example of schematic structure of the dummy bus IP of the semiconductor device which concerns on one Embodiment of this invention. 6 is a timing chart for explaining an example of a schematic operation of the semiconductor device according to the embodiment of the present invention. It is a timing chart for demonstrating other examples of schematic operation | movement of the semiconductor device which concerns on one Embodiment of this invention. 1 is a block diagram illustrating an example of a schematic configuration of a bus control circuit of a semiconductor device according to an embodiment of the present invention. 4 is a flowchart for explaining response processing in a bus control circuit of a semiconductor device according to an embodiment of the present invention. 4 is a flowchart for explaining response processing in a bus control circuit of a semiconductor device according to an embodiment of the present invention; 4 is a flowchart for explaining response processing in a bus control circuit of a semiconductor device according to an embodiment of the present invention; It is a block diagram which shows the other example of schematic structure of the bus control circuit of the semiconductor device which concerns on one Embodiment of this invention. 5 is a timing chart for explaining an example of the operation of the bus control circuit of the semiconductor device according to the embodiment of the present invention. 6 is a timing chart for explaining another example of the operation of the bus control circuit of the semiconductor device according to the embodiment of the present invention. It is a block diagram which shows an example of schematic structure of the semiconductor device which concerns on one Embodiment of this invention. It is a block diagram which shows the other example of schematic structure of the bus control circuit of the semiconductor device which concerns on one Embodiment of this invention. It is a block diagram which shows an example of schematic structure of the semiconductor device which concerns on one Embodiment of this invention. It is a block diagram which shows an example of schematic structure of the semiconductor device which concerns on one Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude various modifications and technical applications that are not explicitly described below. The present invention can be implemented with various modifications (for example, by combining the embodiments) without departing from the spirit of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match actual dimensions and ratios. In some cases, the dimensional relationships and ratios may be different between the drawings.

  The present invention is a semiconductor device including a processor, a memory, and a DMA controller (DMAC), which are connected so as to be able to transfer data according to a bus protocol based on a request / response via a bus IP. The semiconductor device includes a dummy bus IP configured to behave the same as the bus IP, a dummy memory connected to the dummy bus IP and configured to behave the same as the memory, the DMAC, and the bus And a bus control circuit provided between the IP and the dummy bus IP. The dummy bus IP sends a preceding response based on the write request issued by the DMAC to the bus control circuit, and the bus control circuit sends a write response to the write request to the DMA controller based on the preceding response. Send it out.

[First Embodiment]
FIG. 1 is a block diagram illustrating an example of a schematic configuration of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the semiconductor device 100 includes, for example, a processor 110, a memory 120, a bus IP 130, and a DMA controller (hereinafter referred to as “DMAC”) 140. That is, a so-called bus is formed between the processor 110, the memory 120, and the DMAC 140. In the present embodiment, the semiconductor device 100 further includes, for example, a dummy bus IP150, a dummy memory 160, a timing adjustment circuit 170, and a bus control circuit 180. That is, a dummy block is formed by the dummy path IP, the dummy memory, and the timing adjustment circuit.

  The processor 110 is a component that executes a predetermined process by interpreting an instruction code described as a program. Here, the term “processor” is treated as synonymous with a CPU, MPU, coprocessor, microcontroller, or the like, and may mean a multi-core processor. Although not shown, the processor 110 includes, for example, an arithmetic circuit, a decoder, various registers, and a program counter. The processor 110 may also include a cache memory. The processor 110 is connected to the memory 120 via the bus IP130, for example. For example, the processor 110 issues a predetermined request (for example, a write request or a read request) in order to access the memory 120 as a bus slave as a bus master. The request is uniquely identified in the semiconductor device 100 by, for example, a unique access ID.

  The memory 120 is a component configured to include, for example, a volatile memory and / or a rewritable nonvolatile memory. Examples of volatile memory include DRAM and SRAM, and examples of rewritable nonvolatile memory include flash memory, but are not limited thereto. Although only one memory 120 is shown in the figure, a plurality of memories 120 may be provided.

  The bus IP 130 is an interface circuit for realizing data transfer (bus communication) between a bus master and a bus slave according to a predetermined bus protocol. In the bus protocol, for example, access of request and response is defined. The request is a data unit sent from the bus master to the bus slave, and the request includes, for example, a read command and a write command. The response is a data unit sent from the bus slave to the bus master, and the request includes, for example, read data and a write end message. In this embodiment, each of the processor 110 and the DMAC 140 operates as a bus master, and the memory 120 operates as a bus slave. Accordingly, in this example, the bus IP 130 is configured to include two initiator agents (IA) 131 for communicating with the bus master and one target agent (TA) 132 for communicating with the memory 120.

  FIG. 2 is a block diagram showing an example of a schematic configuration of the bus IP of the semiconductor device according to the embodiment of the present invention. In the figure, a schematic configuration of a bus IP 130 including two initiator agents 131A and 131B and one target agent 132 is shown. Also, as shown in the figure, different paths are formed in the bus IP 130 so as to separately manage bus protocol requests and responses.

  Each of the initiator agents 131A and 131B includes a protocol conversion unit 1311, various buffers 1312a to 1312d, and an address decoder 1313. The protocol conversion unit 1311 sequentially converts data received from the outside into internal data according to a predetermined bus protocol, and sends the internal data to the corresponding buffer 1312a or 1312b, while the internal data received from the corresponding buffer 1312c or 1312d. Are converted into external data according to a predetermined bus protocol. The request buffer 1312a is a FIFO buffer circuit that stores a request as a data unit, and the write data buffer 1312b is a FIFO buffer circuit that stores write data according to the write request. The request transmitted from the request buffer 1312a is input to the address decoder 1313. The response buffer 1312c is a FIFO buffer circuit that stores a response received from the target agent 132, and the read data buffer 1312d is a FIFO buffer circuit that stores read data received from the target agent 132. The address decoder 1313 identifies an access destination bus slave and its address based on the address indicated by the request received from the request buffer 1312a.

  In addition, the protocol conversion unit 1311 can assign a unique access ID to the bus master for the received requests so that the requests received from the bus master can be distinguished from each other. The access ID is carried over to the response to the request, and thereby the bus IP 130 can recognize which request corresponds to the response received from the bus slave.

  The target agent 132 includes a protocol conversion unit 1321 and various buffers 1322a to 1322d. The target agent 132 is different from the initiator agent 131 in that it does not include an address recorder, but the others are the same and will not be described.

  Returning to FIG. 1, the DMAC 140 is a component for directly transferring data between designated components. For example, the DMAC 140 issues a request (for example, a write request or a read request) in order to access the memory 120 that is a bus slave as a bus master. For example, in the DMAC 140, when a processor 110 sets a data transfer instruction including an internal register (not shown) including a transfer source address, a transfer destination address, and a parameter indicating the length of data to be transferred. The data transfer is executed according to the instruction. The DMAC 140, which is a bus master that has received a data transfer command from the processor 110, interrupts the processor 110 when it receives a data transfer end notification from the bus slave.

  The dummy bus IP150 is a dummy circuit configured to exhibit the same behavior as the bus IP130. In other words, the dummy bus IP150 may have the same circuit configuration as that of the bus IP130, but can be realized by a minimum circuit configuration necessary for reproducing the function related to the request / response. Therefore, since the dummy bus IP150 is mounted with only the minimum necessary circuits, the circuit scale is very small and simple compared to the bus IP130. The dummy bus IP 150 sends a preceding response (preceding response state signal) PR to the bus control circuit 180 via the preceding response signal line L at a timing when write access to the memory 120 becomes possible. The preceding response PR is a response that is effective when the DMAC 140 performs a write access. For example, the dummy bus IP150 determines which bus master (for example, either the processor 110 or the DMAC 140) has performed a write access based on a master ID that appears on the bus, for example, and determines that it is a write access from the DMAC 140. To the preceding response PR.

  The dummy memory 160 is a dummy circuit configured to exhibit the same behavior as the memory 120. The dummy memory 160 can also be configured by a minimum circuit necessary for reproducing a function of returning a response to a request from the dummy bus IP150. That is, the dummy memory does not have a memory cell for storing individual data segments and a configuration for accessing the memory cell. Therefore, the circuit scale is very small and simple compared to the memory 120.

  FIG. 3 is a block diagram showing an example of a schematic configuration of the dummy bus IP of the semiconductor device according to the embodiment of the present invention.

  As described above, the dummy bus IP150 is a circuit configured to reproduce the request / response function of the bus IP130 and includes the initiator agents 151A and 151B and the target agent 152.

  More specifically, the dummy bus IP150 includes a protocol conversion unit 1511, a request buffer 1512a and a response buffer 1512c, and an address decoder 1513. That is, in the dummy bus IP150, since the data body according to the request and response can be ignored, the buffer for storing them can be omitted, and it is not necessary to specify the address in the access destination bus slave, so the address is specified. The circuit for this can be omitted. Therefore, the protocol conversion unit 1511 and the address decoder 1513 can also be configured by omitting circuits relating to the data body and the address. As a result, since the dummy bus IP150 is also mounted with only the minimum necessary circuits, the circuit scale is very small and simple compared to the bus IP130.

  Returning to FIG. 1, the timing adjustment circuit 170 is a circuit for guaranteeing a problem of timing convergence in design (timing closure) due to branching of the bus wiring between the bus master and the bus slave. It is configured to include. Although not shown, the timing adjustment circuit 170 includes a control circuit that complies with the bus protocol. For example, access between the processor 110 and the dummy bus IP150 is performed through the FF1, and access between the DMAC 140 and the dummy bus IP150 is performed through the FF2. Note that the timing adjustment circuit 170 may be omitted when it is not necessary to consider the timing convergence problem.

  The bus control circuit 180 is a circuit that performs control based on a response sent from the bus slave side. Specifically, the bus control circuit 180 temporarily stores the request issued by the bus master in a buffer, and also stores the content of the response issued by the memory 120 and received via the bus IP 130 and the buffer. By managing so that the correspondence with the contents of the request is maintained, control is performed so that an appropriate response to the request is transmitted to the bus master. In addition, the bus control circuit 180 uniquely manages each access (that is, request / response) by a plurality of bus masters by, for example, a master ID.

  In this example, the bus control circuit 180 is connected to the dummy memory 160 via the response signal line L so that the response from the dummy memory 160 is directly received. In mounting, since the circuit scales of the dummy bus IP150 and the dummy memory 160 are small, the wiring length of the response signal line L is also shortened. Therefore, it is not necessary to consider timing convergence in this respect.

  FIG. 4 is a timing chart for explaining an example of a schematic operation of the semiconductor device according to the embodiment of the present invention.

  In the semiconductor device 100, when the DMAC 140 issues a write request for write access to the memory 120, the write access is transmitted to the initiator agent 131B of the bus IP 130 and the initiator agent 151B of the dummy bus IP 150. Since the bus IP 130 and the dummy bus IP 150 behave in the same manner, the write access appears in the respective target agents 132 and 152 at the same timing. Therefore, the bus control circuit 180 immediately returns a write response to the write request to the DMAC 140 at the timing when the write access appears in the target agent 152 of the dummy bus IP150.

  That is, as shown in the figure, for example, it is assumed that the DMAC 140 issues a write request at the nth clock. It is assumed that the write request appears in the target agents 132 and 152 at the (n + 4) th clock due to the latency of the bus IP 130 (and the dummy bus IP 150). Therefore, the memory 120 returns a write response (write end status) to the write request at the next clock timing (n + 5th clock), and this is three clocks later (n + 8th clock) via the bus IP130. Will appear.

  In this embodiment, the preceding response PR is issued to the bus control circuit 180 at the timing when the write request appears in the target agent 152. As will be described later, the bus control circuit 180 receives the preceding response PR and sends a write response to the write request to the DMAC 140 under a predetermined condition. Requests and responses usually correspond one-to-one unless there is a burst access by a single request. Therefore, when the bus control circuit 180 sends a write response according to the preceding response, even if a true write response is received from the memory 120 via the bus IP 130, the bus control circuit 180 ignores the request and the response. I try to keep consistency between them.

  As shown in FIG. 5, even when the bus control circuit 180 receives a preceding response PR for a write request, if another request preceding the write request already exists, the bus control circuit 180 The circuit 180 does not issue a write response based on the preceding response PR, sends a response to the other request to the bus master, and then sends a write response to the write request sent from the memory 120 to the bus master.

  As described above, when a write access is issued from the DMAC 140 to the memory 120, the semiconductor device 100 returns a pseudo write response to the DMAC 140 without waiting for a write response from the memory 120. Can immediately terminate the write access to the memory 120, thus improving the latency.

  Next, details of the bus control circuit 180 will be described. FIG. 6 is a block diagram showing an example of a schematic configuration of the bus control circuit of the semiconductor device according to the embodiment of the present invention. As shown in the figure, the bus control circuit 180 includes, for example, a buffer 181, an OR gate 182, and a response control circuit 183.

  The buffer 181 is a FIFO buffer circuit, and temporarily stores a request sent from the bus master (that is, the DMAC 140). The number of requests stored in the buffer 181 is counted by a counter (not shown). The buffer 181 operates so that requests are sequentially fetched from the FIFO fetch block 181a by the response control circuit 183 every time a response is received from the bus slave side via the OR gate 182.

  The response control circuit 183 includes a counter 183a that counts two values related to the preceding response received from the bus slave side, and performs processing according to the response received from the bus slave side according to each count value by the counter 183a. The counter 183a, for example, the number of times that a write response is returned to the bus master with respect to the preceding response PR received from the bus slave side (hereinafter referred to as “response returning number”), and the number of preceding responses PR received from the bus slave side. In response to this, the number of write responses not yet returned to the bus master (hereinafter referred to as “response remaining number”) is counted.

  Specifically, the response control circuit 183 refers to the buffer 181 when receiving the preceding response PR via the preceding response signal line L. When the request to be extracted is a write request, the response control circuit 183 receives the request from the buffer 181. One is taken out and a response to the write request is sent to the bus master regardless of the response from the bus IP 130, and the counter value of the counter 183a is updated accordingly. Thereafter, when the response control circuit 183 receives a true response to the write request from the bus IP130, if the count value of the remaining response number is not 0, the response control circuit 183 decrements it and ignores the response sent from the bus IP130. (That is, do not transfer to the bus master). That is, in one example, even if the response control circuit 183 receives a response from the bus IP 130, the response control circuit 183 ignores the number of times the preceding response PR is received and the write response is returned to the bus master. On the other hand, if the count value of the remaining response number is 0, the response control circuit 183 passes the response sent from the bus IP 130 as it is to the bus master.

  7A to 7C are flowcharts for explaining response processing in the bus control circuit of the semiconductor device according to the embodiment of the present invention. In addition to the response processing, the bus control circuit 180 stores a request in the buffer 181 every time it receives a request from the bus master (that is, the DMAC 140).

  As shown in the figure, the bus control circuit 180 monitors whether or not there is a response from the bus slave side (S701). When receiving a response from the bus slave side (Yes in S701), the bus control circuit 180 determines whether or not the response is the preceding response PR (S702), and the remaining number of responses related to the preceding response PR is not 0 ( It is determined whether or not (≠ 0) (S703 and S704). That is, when the bus control circuit 180 determines that the response is not the preceding response PR (No in S702) and the remaining number of responses is 0 (No in S703), the bus control circuit 180 performs processing related to the normal response (S705). The process related to the normal response will be described with reference to FIG. 7B.

  The bus control circuit 180 determines that the response is not the preceding response PR (No in S702) and the remaining number of responses is not 0 (Yes in S703), or the response is the preceding response PR (Yes in S702). If it is determined that the remaining number of responses is 0 (No in S704), processing related to the preceding response is performed (S706). That is, if the response is the preceding response PR or the remaining number of responses related to the preceding response PR is not 0, the bus control circuit 180 performs processing related to the preceding response PR instead of processing related to the normal response. Processing related to the preceding response will be described with reference to FIG. 7C.

  Furthermore, if the response is the preceding response PR (Yes in S702) and the bus control circuit 180 determines that the number of responses to the preceding response PR is not 0 (Yes in S704), the bus control circuit 180 performs processing related to the preceding response (S707). ), A process related to a normal response is performed (S708).

  Referring to FIG. 7B, in the process related to the normal response, the bus control circuit 180 refers to the buffer 181 and determines whether or not the request stored in the FIFO fetch block 181a is a write request (S7051). If the bus control circuit 180 determines that the data in the FIFO fetch block 181a is not a write response (No in S7051), the bus control circuit 180 fetches and discards the request (for example, a read request) stored in the FIFO fetch block 181a ( S7052). Subsequently, the bus control circuit 180 sends a response (for example, a read response) received from the bus slave side to the bus master (S7053), and ends the process related to the normal response. As a result, the bus control circuit 180 returns to monitoring the response from the bus slave side.

  On the other hand, if the bus control circuit 180 determines that the data in the FIFO fetch block 181a is a write response (Yes in S7051), then whether or not the response return number related to the preceding response PR is zero. Is determined (S7054). If the bus control circuit 180 determines that the response return number is not 0 (Yes in S7054), the bus control circuit 180 decrements the counter value by 1 (S7055), and ends the processing related to the normal response. As a result, the bus control circuit 180 returns to monitoring the response from the bus slave side.

  Next, referring to FIG. 7C, in the process related to the preceding response, the bus control circuit 180 first increments the remaining response number related to the preceding response by one (S7061). Subsequently, the bus control circuit 180 refers to the buffer 181 and determines whether or not the request stored in the FIFO fetch block 181a is a write request (S7062). When the bus control circuit 180 determines that the request stored in the FIFO fetch block 181a is not a write request (No in S7062), the bus control circuit 180 ends the process related to the preceding response.

  On the other hand, when the bus control circuit 180 determines that the request stored in the FIFO fetch block 181a is a write request (Yes in S7062), the bus control circuit 180 fetches the write request stored in the FIFO fetch block 181a. (S7063), the extracted write request is sent to the bus master (S7064). Subsequently, the bus control circuit 180 increments the response return number by 1 (S7065), further decrements the remaining response number by 1 (S7066), and ends the processing related to the preceding response. As a result, the bus control circuit 180 returns to monitoring the response from the bus slave side.

  When the bus control circuit 180 determines that the response is the preceding response PR (Yes in S702) and the remaining number of responses is not 0 (Yes in S704), the bus control circuit 180 performs the above-described processing related to the preceding response (S707), and Then, the process related to the normal response described above is performed (S708).

  That is, this processing is executed when the bus control circuit 180 receives the preceding response PR and also receives a response from the bus IP 130. For example, it can be assumed that the bus control circuit 180 receives a preceding response PR and a response completely independent of the preceding response PR and a case where the bus control circuit 180 receives a preceding response PR and a corresponding true write response.

  In the former case, the bus control circuit 180 returns a write response if the predetermined condition is met in the process related to the preceding response (S707), and does not return a response if the condition is not met. In the process related to the next normal response, the bus control circuit 180 returns a response if the response return number is zero. In the latter case, in the process related to the preceding response (S707), the bus control circuit 180 returns a write response if it matches a predetermined condition, and does not return a response if it does not match. In the process related to the next normal response, the bus control circuit 180 returns the write response in the process related to the preceding response (S707), so that the response return number becomes 0 or more, and therefore does not return a response. That is, the bus control circuit 180 returns no response when the predetermined condition is not met in the process related to the preceding response, and returns a response in the process related to the next normal response.

  FIG. 8 is a block diagram showing another example of the schematic configuration of the bus control circuit of the semiconductor device according to the embodiment of the present invention. The bus control circuit 180 shown in the figure further includes a timing adjustment circuit 184. The timing adjustment circuit 184 is a circuit for assuring a timing convergence problem in design due to the provision of the bus control circuit 180. In other words, the bus control circuit 180 itself has only to have a function of returning a predetermined response to the bus master side based on the preceding response via the response signal line L, and usually the timing convergence problem needs to be considered. It is not considered. However, when considering the problem of timing convergence, for example, a timing adjustment circuit 184 may be disposed in front of the buffer 181 as shown in FIG. The timing adjustment circuit 184 includes a flip-flop, for example.

  Next, an example of the operation of the bus control circuit 180 will be described. 9 to 10 are timing charts for explaining an example of the operation of the bus control circuit of the semiconductor device according to the embodiment of the present invention.

  As shown in FIG. 9, requests sent from the bus master (that is, the DMAC 140) to the bus control circuit 180 according to the clock CLK are sequentially stored in the buffer 181. At this time, the number of requests stored in the buffer 181 is counted. The figure shows that a write request is sent at the nth clock, followed by a read request and a read request, and a write request is sent two clocks later (n + 5th clock). A request to be fetched next is set in the FIFO fetch block 181a.

  Here, it is assumed that the bus control circuit 180 requires 8 clocks from receiving a request from the bus master to receiving a true response corresponding to the request from the bus slave (that is, the memory 120). Further, it is assumed that the dummy bus IP150 can send a preceding response PR to the bus control circuit 180 after 5 clocks with respect to the write request.

  Therefore, when receiving the preceding response PR at the (n + 5) th clock, the bus control circuit 180 sends a write response to the bus master at the next clock timing (n + 6th clock). At this time, the counter value by the counter 183a is “1”. Therefore, as is apparent from the figure, in this example, the bus control circuit 180 can return the response to the bus master three clocks ahead.

  For example, after receiving the first write request, the bus control circuit 180 receives a true response corresponding to the n + 8th clock. However, since the bus control circuit 180 sends a response to the first write request to the bus master based on the preceding response PR, the bus control circuit 180 ignores the true response, and therefore the counter value by the counter 183a is “ 0 ”. The bus control circuit 180 sends the received read request to the bus master as it is at the next clock timing.

  If the bus control circuit 180 receives the preceding response PR at the (n + 10) th clock, the read response and the write response compete at the next clock timing. In this example, the bus control circuit 180 The read response is sent first.

  As another example, assume that the bus control circuit 180 receives a read request and a write request in the order shown in FIG. In response to the write request received at the (n + 4) th clock, when the bus control circuit 180 receives the preceding response PR at the (n + 9) th clock, it does not send the write response at the next clock timing but stores it in the buffer 181 first. After the read request is taken out, a write response is sent out. That is, the bus control circuit 180 receives a write request for the write request received at the (n + 13) th clock at the (n + 13) th clock, and sends it to the bus master.

[Second Embodiment]
In the present embodiment, a bus master other than the DMAC 140 (that is, the processor 110) is based on the number of write requests to the memory 120 and the number of write responses (write end status) issued by the dummy memory received via the dummy bus IP150. ) To determine whether there is a write request currently being processed for the memory 120. If there is no write request currently being processed, the write request is immediately issued when the write request from the DMAC 140 is issued. A semiconductor device capable of returning a write response to a request is disclosed.

  FIG. 11 is a block diagram showing an example of a schematic configuration of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the semiconductor device 1100 further includes a bus monitoring circuit 1110 that monitors a write request input to the bus IP130. In the semiconductor device 1100, a bus control circuit 1120 is provided instead of the bus control circuit 180. Hereinafter, description of the same components as those of the semiconductor device 100 illustrated in FIG. 1 will be omitted.

  When a write access to the memory 120 is input from the processor 110, the bus monitoring circuit 1110 increments the count value by one. When a write response to the write access is input from the dummy bus IP150, the bus monitoring circuit 1110 increases the count value by one. It includes a counter 1111 that decrements. The counter 1111 sets the value of the ongoing signal to “H” when the count value becomes 0, and sends the value of the ongoing signal to “L” when the count value is other than 0.

  FIG. 12 is a block diagram showing an example of a schematic configuration of a bus control circuit of a semiconductor device according to an embodiment of the present invention.

  As shown in the figure, the bus control circuit 1120 of this embodiment further includes a preceding response control circuit 1121. The preceding response control circuit 1121 receives a request from the bus master and an oning signal and a preceding response PR sent from the bus monitoring circuit 1110.

  When the request from the bus master is a write request, the preceding response control circuit 1121 performs transmission control of the preceding response received from the dummy bus IP 150 for the write request. The preceding response control circuit 1121 has a counter (not shown), and counts the number of times the preceding response PR is transmitted by the counter.

  That is, when the request from the bus master is a write request, the preceding response control circuit 1121 first determines whether or not the value of the ongoing signal is “H”. When the preceding response control circuit 1121 determines that the value of the ongoing signal is “H”, it next determines whether or not the count value is 0, and determines that the count value is 0. The received preceding response PR is sent to the OR gate 182 and the response control circuit 183. The response control circuit 183 that has received the preceding response PR performs the above-described processing. On the other hand, even if the preceding response control circuit 1121 determines that the value of the ongoing signal is “H”, if it determines that the count value is not 0, it decrements the count value of the counter by one, No processing is performed for the preceding response PR. As a result, the preceding response control circuit 1121 can pass the preceding response only when there is no write access currently being processed.

[Third Embodiment]
The present embodiment is a modification of the second embodiment, and discloses a semiconductor device adapted when there are two or more bus masters in addition to the DAMC 140 that can access the memory 120 operating as a bus slave.

  FIG. 13 is a block diagram showing an example of a schematic configuration of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the semiconductor device 1300 of this embodiment includes processors 110A and 110B and a DMAC 140 as a bus master. Further, with the addition of the processor 110B, a timing adjustment circuit 170 'including three flip-flops and two bus monitoring circuits 1110A and 1110B are provided. The configuration of the bus monitoring circuits 1110A and 1110B is the same as that shown in the second embodiment.

  The bus control circuit 1120 'has also been modified to accommodate these changes. That is, the bus control circuit 1120 ′ is controlled so as to send the preceding response PR only when the values of the ongoing signal sent by the bus monitoring circuits 1110 A and 1110 B are both “H”.

  Thus, even when there are two or more bus masters that can access the memory 120 as the bus slave, in addition to the DAMC 140, an appropriate preceding response can be obtained by monitoring the write access from each bus master to the memory 120. A write response based on PR can be issued.

[Fourth Embodiment]
The present embodiment is a modification of the second embodiment, and discloses a semiconductor device adapted to a case where a plurality of memories 120 are present.

  FIG. 14 is a block diagram illustrating an example of a schematic configuration of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the semiconductor device 1400 of this embodiment is configured to be accessible via a bus IP 130 to a plurality of memories 120A and 120B that operate as bus slaves. Accordingly, the semiconductor device 1400 includes a dummy bus IP150 and a plurality of dummy memories 160A and 160B so as to correspond to such a configuration.

  The bus control circuit 1120 ′ monitors a preceding response issued by one of the target agents 152 </ b> A and 152 </ b> B of the dummy bus IP <b> 150. The bus monitoring circuit 1110 'is configured to manage the number of issued write accesses and the number of write responses (write end status) for the write accesses, for each access destination of the bus master.

  As described above, even when the semiconductor device 100 includes a plurality of memories 120, the latency of access to each of the memories 120 can be improved.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations and functions described are provided as examples only, and some of the steps, operations and functions may be omitted without departing from the spirit of the invention and may be combined with one another. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment are added to other embodiments while appropriately improving the other features, or other Specific features in the embodiments can be replaced, and such forms are also included in the gist of the present invention.

  The present invention can be widely used in the field of semiconductor devices having a bus.

100, 1100, 1300, 1400 ... Semiconductor device 110 ... Processor 120 ... Memory 130 ... Bus IP
131 ... Initiator agent 1311 ... Protocol converter 1312a-1312d ... Buffer 1313 ... Address decoder 132 ... Target agent 1321 ... Protocol converter 1322a-1312d ... Buffer 140 ... DMA controller (DMAC)
150 ... Dummy bus IP
DESCRIPTION OF SYMBOLS 151 ... Initiator agent 1511 ... Protocol conversion part 1512a, 1512c ... Buffer 1313 ... Address decoder 152 ... Target agent 1521 ... Protocol conversion part 1522a, 1522c ... Buffer 160 ... Dummy memory 170 ... Timing adjustment circuit 180 ... Bus control circuit 181 ... Buffer 182 ... OR gate 183 ... Response control circuit 1110, 1110 '... Bus monitoring circuit 1111 ... Counter 1120, 1120' ... Bus control circuit 1121 ... Preceding response control circuit

Claims (14)

At least one processor operating as a bus master, at least one memory operating as a bus slave, and a DMA operating as the bus master, connected so as to be able to transfer data according to a predetermined bus protocol based on a request / response via the bus IP A semiconductor device including a controller,
A dummy bus IP connected to the at least one processor and the DMA controller and configured to behave the same as the bus IP;
A dummy memory connected to the dummy bus IP and configured to behave the same as the memory;
The DMA controller, and a bus control circuit provided between the bus IP and the dummy bus IP,
When the request issued by the DMA controller is a write request, the dummy bus IP sends a preceding response to the bus control circuit before the timing at which the memory sends a write response,
The bus control circuit sends a write response to the write request to the DMA controller based on the preceding response sent from the dummy bus IP.
Semiconductor device. The DMA controller, when receiving the write response to the write request, an interrupt to the processor, the semiconductor device according to claim 1, wherein.   The dummy bus IP sends the preceding response to the bus control circuit at the same timing as when the bus IP issues the write request to the memory based on the write request issued by the bus master. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the dummy bus IP is configured to ignore a data body according to the write request issued by the bus master. The dummy memory is configured not to have a storage cell that stores a data body according to the write request issued by the bus master, and configured to issue a response to the write request to the dummy bus IP. The semiconductor device according to claim 4 .   The semiconductor device according to claim 1, further comprising a first timing adjustment circuit provided between the at least one processor and the DMA controller and the dummy bus IP. When the bus control circuit receives the true write response to the write request issued by the memory via the bus IP after sending the write response based on the preceding response to the DMA controller, The semiconductor device according to claim 1 , wherein control is performed so that a true write response is not sent to the DMA controller. When the bus control circuit determines that there is another request issued by the bus master that precedes the write request when the preceding response sent from the dummy bus IP is received, 8. The semiconductor according to claim 7 , wherein the true write response to the write request issued by the memory, received via the bus IP, is sent to the DMA controller instead of a write response to the write request based on apparatus. 9. The semiconductor device according to claim 8 , wherein the bus control circuit sends the true write response to the DMA controller after sending a response to the other request to the bus master. The bus control circuit
A buffer for temporarily storing the request issued by the bus master;
When the request to be extracted from the buffer is the write request, the bus master performs the correspondence between the response issued by the memory and received via the bus IP and the write request to be extracted from the buffer. A response control unit that controls to send a predetermined response to the issued write request to the bus master;
The semiconductor device according to claim 1, comprising: The semiconductor device according to claim 10 , wherein the bus control circuit further includes a second timing adjustment circuit that adjusts a timing for storing a request issued by the bus master in the buffer. At least one processor operating as a bus master, at least one memory operating as a bus slave, and a DMA operating as the bus master, connected so as to be able to transfer data according to a predetermined bus protocol based on a request / response via the bus IP A semiconductor device including a controller,
A dummy bus IP connected to the at least one processor and the DMA controller and configured to behave the same as the bus IP;
A dummy memory connected to the dummy bus IP and configured to behave the same as the memory;
A bus control circuit provided between the DMA controller and the bus IP and the dummy bus IP;
At least one bus monitoring circuit for monitoring the number of write requests issued by the at least one processor and the number of write responses issued by the dummy memory received via the dummy bus IP;
When the request issued by the DMA controller is a write request, the dummy bus IP sends a preceding response to the bus control circuit before the timing at which the memory sends the write response.
The bus control circuit is issued by the DMA controller based on the preceding response when the bus monitoring circuit determines that there is no write request currently being processed from the at least one processor to the memory. A semiconductor device that sends a write response to the write request to the DMA controller. The semiconductor device according to claim 12 , wherein each of the plurality of bus monitoring circuits monitors the number of write requests issued by a corresponding one of the plurality of processors. A plurality of the memories, and a plurality of dummy memories corresponding to each of the plurality of memories,
The dummy bus IP sends the preceding response to the bus control circuit based on a write access to each of the plurality of dummy memories issued by the bus master,
The semiconductor device according to claim 13 .