JP6430710B2 - Data transfer control device and data transfer control method - Google Patents

Description

  The present invention relates to a data transfer control device and a data transfer control method.

  In the information society, the existence of a computer system is indispensable, and the computer system is required to have higher performance. In order to improve the performance of a computer system, the processing load of a CPU (Central Processor Unit) and the efficient use of a bus are important factors.

  As a technique for transferring data between components in a computer system for the purpose of reducing the processing load on the CPU, a DMA (Direct Memory Access) transfer technique for transferring data in place of the CPU is conventionally known. In such DMA transfer, when a data transfer request occurs in the CPU, the CPU gives a data transfer command to the DMA controller, and the DMA controller, based on the data transfer command, independently of the processing of the CPU, Data transfer processing is performed, and when the transfer processing ends, a response indicating the end of transfer is returned to the CPU. In general, when one device or component controls a bus to access another device or component, the one device is called a bus master device, and the other device is called a bus slave device.

  Thus, in DMA transfer, CPU processing occurs at the start and end of data transfer. Attempts have been made to reduce the number of accesses to the CPU in order to further reduce the processing load on the CPU in the DMA transfer.

  For example, Patent Document 1 below transmits a notification signal including identification information of a peripheral device and the content of the event when a predetermined event occurs in each peripheral device and a DMA controller that controls DMA transfer on a computer system. One or more peripheral devices that become DMA transfer sources or transfer destinations and request execution of DMA transfer, and for registering the contents of events to be monitored in the peripheral devices that should be permitted DMA transfer When the notification signal is received from the event register and each peripheral device, and the identification information and event content of the peripheral device included in the notification signal and the event register match, the DMA controller is activated and specified by the identification information And an event monitoring unit that executes DMA transfer related to the peripheral device to be executed. It discloses a DMA transfer system characterized Rukoto.

Japanese Patent No. 4530971

  The conventional DMA transfer system as disclosed in Patent Document 1 requires the contents of a register held by the activation processing device, and has a problem that the activation processing device uses a bus when transferring the contents. Was.

  Further, in the DMA transfer system, since the activation processing device is connected to the bus master device and the bus slave device by a dedicated signal line, it is necessary to newly design the circuits of the bus master device and the bus slave device itself.

  Therefore, an object of the present invention is to provide a data transfer control device that reduces the data transfer processing load of the bus master device and the bus usage rate.

  It is another object of the present invention to provide a data transfer control device and a data transfer control method that do not require a new design of a bus master device, a bus slave device, and a bus circuit.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect is a data transfer control device connected to a bus. The data control device includes a snoop unit that monitors a write request sent from the bus master device via the bus, and a controller that controls whether to output the write request to a bus slave device. The snoop unit stores data according to the first write request and stores data according to the first write request when the target area indicated by the first write request matches at least one retransfer target area. If the target area indicated by the second write request matches the at least one retransfer target area, the data according to the first write request is output to the controller. When the controller receives data according to the first write request from the snoop unit, the controller outputs data according to the first write request to the bus slave device instead of data according to the second write request. To control.

  The snoop unit includes an address table storing an address indicating the at least one retransmission target area, an address of a target area indicated by the write request, and the at least one retransmission target area stored in the address table. And a comparator that determines whether or not the address indicating the address matches.

  Furthermore, the snoop unit may further include a data storage unit that holds data associated with the at least one retransmission target area.

  In addition, the controller controls the bus slave device from the predetermined device to the bus slave device while controlling to output the data according to the first write request output from the snoop unit to the bus slave device. When there is an access request, a response to the predetermined device can be performed instead of the bus slave device.

  According to another aspect of the present invention, there is provided a bus, a bus master device connected to the bus, a data transfer control device connected to the bus, and a bus connected to the bus via the data transfer control device. A computer system including a slave device. The data transfer control device includes a snoop unit that monitors a write request sent from the bus master device, and a controller that controls whether to output the write request to the bus slave device. The snoop unit stores data according to the first write request and stores data according to the first write request when the target area indicated by the first write request matches at least one retransfer target area. If the target area indicated by the second write request matches the at least one retransfer target area, the data according to the first write request is output to the controller. When the controller receives data according to the first write request from the snoop unit, the controller outputs data according to the first write request to the bus slave device instead of data according to the second write request. To control.

  The computer system may further include a DMA controller connected to the bus. The DMA controller may function as the bus slave device connected to the bus via the data transfer control device.

  Furthermore, the present invention according to another aspect is a data transfer control method in a computer system. The data transfer control method includes monitoring a write request sent from a bus master device via a bus, and controlling whether to output the write request to a bus slave device. The monitoring includes determining whether the target area indicated by the first write request matches at least one retransfer target area, and determining that the target area matches the at least one retransfer target area. When determining, storing the data according to the first write request in a predetermined storage area, and the second write when the data according to the first write request is stored in the predetermined storage area Outputting data according to the first write request stored in the predetermined storage area to the controller when a target area indicated by the request matches the at least one retransmission target area. In addition, the control is performed when the data according to the first write request stored in the predetermined storage area is received, instead of the data according to the second write request. Controlling to output data to the bus slave device.

  According to the present invention, since data retransfer processing is performed without going through the bus master device, the burden of data retransfer processing in the bus master device is reduced, and the bus usage rate associated with data retransfer is reduced. It will be.

  Also, according to the present invention, the data transfer control device can eliminate the need to newly design a bus master device, a bus slave device, and a bus circuit.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a figure which shows an example of schematic structure of the computer system which concerns on one Embodiment of this invention. It is a figure which shows schematic structure of the data transfer control apparatus which concerns on one Embodiment of this invention. It is a figure which shows the structure of the snoop part in the data transfer control apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating the address table and the object data storage part of the data transfer control apparatus which concern on one Embodiment of this invention. It is a state transition diagram for demonstrating operation | movement of the controller in the data transfer control apparatus which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the controller in the data transfer control apparatus which concerns on one Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the controller in the data transfer control apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating an example of the data transfer process in the computer system which concerns on one Embodiment of this invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an example of a schematic configuration of a computer system according to an embodiment of the present invention. As shown in the figure, the computer system 1 according to the present embodiment includes, for example, a bus 10, a processor 20, a storage device 30, a DMA controller 40, a peripheral device 50, and a data transfer control device 70. Consists of.

  The bus 10 is a transmission path including various signal lines for transmitting data between components such as the processor 20 in the computer system 1. In this example, the bus 10 includes an address line ADD for transmitting component address information, a data line DATA for transmitting data to the component, and a control line CNT for transmitting control information for the component. (See FIG. 2). The bus 10 may be, for example, a serial system or a parallel system. In the present disclosure, the bus 10 is described as being an internal bus in the computer system 1. However, the present invention is not limited to this, and for example, an external bus or an extension for connecting the computer system 1 to an external device. It may be a bus.

  The processor 20 is, for example, a CPU or a microprocessor, and is a component that controls the entire computer system 1. That is, the processor 20 typically implements a desired function in the computer system 1 by controlling other components in accordance with a program loaded in the storage device 30. The processor 20 typically functions as a bus master device that controls the bus 10, and thus includes a bus master 61 that controls the bus slave device via the bus 10 and the data transfer control device 70. In the present embodiment, the bus master 61 is connected to the bus 10.

  The storage device 30 is typically a primary storage device composed of a volatile memory (such as a RAM), a rewritable nonvolatile memory (such as a flash memory), or a combination thereof, and is used for the processor 20. Data to be stored. The storage device 30 typically functions as a bus slave device, and thus includes a bus slave 62 controlled by the bus master device via the bus 10 and the data transfer control device 70. In the present embodiment, the bus slave 62 is connected to the bus 10 via the data transfer control device 70.

  The DMA controller 40 is a component that directly controls data transfer between components such as the storage device 30 and the peripheral device 50 under the control of the processor 20. The DMA controller 40 typically functions as a bus master device that controls the bus 10 and can function as a bus slave device such as the processor 20 that is a bus master device. Therefore, the DMA controller 40 includes a bus master 61 and a bus slave 62. Is done.

  The peripheral device 50 is, for example, a communication device, an input / output device, a secondary storage device, an external I / O interface, or the like. The peripheral device 50 of this example functions as a bus master device that controls the bus 10 and can function as a bus slave device such as the processor 20 that is a bus master device. Therefore, the peripheral device 50 includes a bus master 61 and a bus slave 62. Yes. Note that when the peripheral device 50 functions only as a bus master device, the bus slave 62 may not be provided. When the peripheral device 50 functions only as a bus slave device, the bus master 61 may not be provided.

  The data transfer control device 70 is a component for more efficiently controlling data transmission from the bus master device to the bus slave device. In the present embodiment, the data transfer control device 70 is provided between the bus 10 and the bus slave 62 of each bus slave device. The data transfer control device 70 determines whether the target area of data to be written, which is instructed by the bus master device, coincides with a specific area in the bus slave 62 of the bus slave device (hereinafter referred to as “retransfer target area”). If it is determined that the target area matches the retransfer target area, the data is retained. The retransfer target area is, for example, an area in which data (including programs) that is frequently used in the computer system is stored. For example, when there is a retransfer request for the same data from the bus slave 62 of the bus slave device, the data transfer control device 70 outputs the held data to the bus slave 62 instead of the bus master device, Realize retransmission.

  While the data transfer control device 70 executes data retransfer, the bus slave device is occupied by the data retransfer process. In this state, when the data transfer control device 70 receives a new control instruction from the bus master device, the data transfer control device 70 replaces the bus slave device occupied by the data retransfer process with, for example, A response indicating that the bus slave device is busy is output to the bus master device.

  In the computer system 1 of this example, the number of data transfer control devices 70 corresponding to the bus slave devices is provided. However, the present invention is not limited to this, and is provided only for the necessary bus slave devices. You can do it. In this example, the retransfer request is typically output from the bus slave 62, but is not limited thereto.

  FIG. 2 is a diagram showing a schematic configuration of a data transfer control device according to an embodiment of the present invention. As shown in the figure, the data transfer control device 70 includes, for example, a snoop unit 71, a controller 72, and selection circuits 73 and 74. In this example, the data transfer device 70 that bears between the processor 20 and the storage device 30 will be described, but the same applies to the control between other bus slave devices and other bus master devices.

  The snoop unit 71 monitors the request signal REQ0 transmitted from the bus master 61 via the bus 10, stores the content of the request signal REQ0 under a predetermined condition, and outputs the stored content to the controller 72. To do. Specifically, the snoop unit 71 determines whether or not the target area indicated by the request signal REQ0 transmitted from the bus master 61 via the bus 10 matches the retransfer target area. When it is determined that it matches the target area, the target data according to the request signal REQ0 is stored. Further, the snoop unit 71 generates a retransfer signal RETRANS based on the address information indicating the retransfer target area and the stored target data, and outputs the generated retransfer signal RETRANS to the controller 72. The retransfer signal RETRANS includes, for example, target data to be retransmitted, a target address, a command, and the like.

  The controller 72 controls signal output to the bus master 61 and the bus slave 62 based on signal inputs received from the bus master 61 and the bus slave 62. Specifically, the controller 72 has a setting indicating whether or not to perform retransfer. When the re-transfer is set to be valid, the controller 72 executes re-transfer of the target data to the bus slave 62. As the re-transfer process, the controller 72 outputs the re-transfer signal RETRANS output from the snoop unit 71 to the selection circuit 73 as the request signal REQ 1 based on the re-transfer request signal REQ_RETRANS output from the bus slave 62. At the same time, the potential of the selection signal SEL 1 is set to the potential “that is, H” of the power supply line and the signal is output to the selection circuit 73. The re-transfer setting in the controller 72 may be determined in advance as a predetermined setting, or may be dynamically switched between valid / invalid by the controller 72.

  When the controller 72 receives the request signal REQ0 output from the bus master 61 via the bus 10 while executing the retransfer of the data, the bus slave 62 is busy with respect to the bus master 61. In order to notify this, the output response signal RES1 is generated and output to the selection circuit 74, while the potential of the selection signal SEL2 is set to “H” and the signal is output to the selection circuit 74. In cases other than those described above, the controller 72 sets the potentials of the selection signals SEL1 and SEL2 to the potential of the ground line, that is, “L”, and outputs the signals to the selection circuits 73 and 74.

  The selection circuit 73 includes, for example, a multiplexer, and based on a selection signal SEL1 output from the controller 72, a request signal REQ1 output from the controller 72 and a request output from the bus master 61 via the bus 10 One of the signals REQ0 is selected, and the signal is output to the bus slave 62 as the request signal REQ. Specifically, when the potential of the selection signal SEL1 is “H”, the selection circuit 73 selects the request signal REQ1, and outputs the request signal REQ to the bus slave 62, while the selection signal SEL1 When the potential is “L”, the request signal REQ0 is selected and the signal is output to the bus slave 62 as the request signal REQ.

  The selection circuit 74 includes, for example, a multiplexer, and based on a selection signal SEL2 output from the controller 72, a response signal RES1 output from the controller 72 and a response signal RES0 output from the bus slave 62 One of them is selected, and the response signal RES is output to the bus master 61 via the bus 10 as a response signal RES. Specifically, when the potential of the selection signal SEL2 is “H”, the selection circuit 74 selects the response signal RES1, and outputs the signal to the bus master 61 via the bus 10 as the response signal RES. When the potential of the selection signal SEL2 is “L”, the response signal RES0 is selected and the signal is output to the bus master 61 via the bus 10 as the response signal RES.

  FIG. 3 is a diagram showing a configuration of the snoop unit in the data transfer control device according to the embodiment of the present invention. As shown in the figure, the snoop unit 71 of this embodiment includes, for example, an address table 710, a comparator 711, a data storage control unit 712, and a data storage unit 713. In the figure, the request signal REQ0 is a general term for signals of a request address signal REQ0_ADD indicating a control target, a request data signal REQ0_DATA indicating target data, and a request control signal REQ0_CNT indicating control contents. In the figure, a retransfer signal RETRANS is a general term for signals of a retransfer address signal RETRANS_ADD indicating a control target and a retransfer data signal RETRANS_DATA indicating target data.

  The address table 710 is a table that holds a head address indicating a retransfer target area. The address table 710 also outputs a retransfer address signal RETRANS_ADD based on the address indicating the area to the comparator 711, the data storage unit 713, and the controller 72. The contents of the address table 710 will be described with reference to FIG.

  The comparator 711 compares the target area indicated by the request address signal REQ0_ADD output from the bus master 61 via the bus 10 with the target area indicated by the retransfer address signal RETRANS_ADD, and determines whether these target areas match. Judging. When the comparator 711 determines that the target regions match, the comparator 711 outputs a match signal MATCH to the data storage control unit 712.

  The data storage control unit 712 generates the enable signal ENA based on the coincidence signal MATCH output from the comparator 711, the request control signal REQ0_CNT and the request data signal REQ0_DATA output from the bus master 61 via the bus 10. The enable signal ENA is output to the data storage unit 713. Specifically, the data storage control unit 712 determines whether or not the content indicated by the request control signal REQ0_CNT is a write request to the bus slave 62, and whether or not the match signal MATCH is output from the comparator 711. Further, it is determined whether the target data indicated by the request data signal REQ0_DATA has valid contents corresponding to the write request. The data storage control unit 712 determines that the content indicated by the request control signal REQ0_CNT is a write request to the bus slave 62, determines that the match signal MATCH is output from the comparator 711, and outputs the request data signal When it is determined that the target data indicated by REQ0_DATA has valid contents corresponding to the write request, an enable signal ENA is generated and the signal is output to the data storage unit 713.

  The data storage unit 713 has a predetermined storage area, and stores target data corresponding to an address indicating the retransfer target area in the predetermined storage area. In addition, the data storage unit 713 indicates the state of the stored target data corresponding to the address indicated by the retransfer address signal RETRANS_ADD output from the address table 710 based on the enable signal ENA output from the data storage control unit 712. The data is updated to the state of the target data indicated by the request signal REQ0_DATA output from the bus master 61 via the bus 10. Specifically, the data storage unit 713 corresponds to the address indicated by the retransfer address signal RETRANS_ADD output from the address table 710 while the potential of the enable signal ENA output from the data storage control unit 712 is “H”, for example. The state of the stored target data is updated to the target data indicated by the request signal REQ0_DATA output from the bus master 61 via the bus 10. Further, the data storage unit 713 outputs the updated target data to the controller 72 as the retransfer data signal RETRANS_DATA.

  FIG. 4 is a diagram for explaining an address table and a target data storage unit of the data transfer control device according to the embodiment of the present invention. As shown in the figure, the address table 710 is typically configured to include a retransfer target area start address column 7101 and a data address column 7102. The retransfer target area start address column 7101 holds the start address of a storage area in which frequently used data or the like is stored in the computer system. The data address column 7102 holds the start address of the corresponding area in the data storage unit 713 storing the data entity such as the program so that the retransfer target area and the data entity stored therein are associated with each other. To do.

  FIG. 5 is a state transition diagram for explaining the operation of the controller in the data transfer control device according to the embodiment of the present invention. Referring to the figure, first, in the standby state (S501), when the re-transfer is set to be valid, the controller 72 re-transfers based on the re-transfer request signal REQ_RETRANS output from the bus slave 62. It is determined whether or not is requested.

  When the controller 72 determines that the retransfer to the bus slave 62 is valid and the retransfer is requested from the bus slave 62, the controller 72 receives the request signal REQ0 output from the bus master 61 via the bus 10, and the bus 72 Based on the state of the response signal RES0 output from the slave 62, it is further determined whether or not the bus master 61 is accessing the bus slave 62. When the controller 72 determines that the bus master 61 is not accessing the bus slave 62, the controller 72 transits from the standby state (S501) to the retransfer execution state (S503). On the other hand, when the controller 72 determines that the bus master 61 is accessing the bus slave 62, the controller 72 transits from the standby state (S501) to the bus access execution state (S502). Details of the operation of the controller 72 when maintaining the standby state (S501) in the standby state (S501) will be described later.

  In the bus access execution state (S502), the controller 72 determines the bus master 61 for the bus slave 62 based on the request signal REQ0 output from the bus master 61 via the bus 10 and the response signal RES0 output from the bus slave 62. It is determined whether or not the access has been completed. When the controller 72 determines that the access of the bus master 61 to the bus slave 62 is not completed, the controller 72 maintains the bus access execution state (S502). On the other hand, when the controller 72 determines that the access of the bus master 61 to the bus slave 62 is completed, the controller 72 transits from the bus access execution state (S502) to the retransfer execution state (S503). Details of the operation of the controller 72 when maintaining the bus access execution state (S502) in the bus access execution state (S502) will be described later.

  In the retransfer execution state (S503), the controller 72 determines whether or not the retransfer to the bus slave 62 is completed based on the response signal RES0 output from the bus slave 62. When the controller 72 determines that the retransfer to the bus slave 62 has not ended, the controller 72 maintains the retransfer execution state (S503). On the other hand, when the controller 72 determines that the retransfer to the bus slave 62 has been completed, the controller 72 transitions to the standby state (S501). Details of the operation of the controller 72 when maintaining the retransfer execution state (S503) in the retransfer execution state (S503) will be described later.

  FIG. 6 is a flowchart for explaining the operation of the controller in the data transfer control device according to the embodiment of the present invention. Specifically, FIG. 6 is a flowchart for explaining the operation of the controller when maintaining the standby state and the bus access execution state of the data transfer control device according to the embodiment of the present invention.

  Referring to the figure, in the standby state and the bus access execution state, first, the controller 72 sets the logic of the selection signal SEL to “L” and outputs the signal to the selection circuits 73 and 74 (S601).

  Next, the controller 72 confirms the state of the request signal REQ0 output from the bus master 61, and determines whether the access destination (that is, the target area) of the bus master 61 is the retransfer target area of the bus slave 62. (S602). When the controller 72 determines that the access destination of the bus master 61 is not the retransfer target area (No in S602), the controller 72 outputs the request signal REQ0 output from the bus master 61 to the bus slave 62 via the selection circuit 73 (S604). .

  On the other hand, when the controller 72 determines that the access destination of the bus master 61 is the retransfer target area (Yes in S602), the controller 72 retransmits the target data output from the snoop unit 71 to the bus slave 62 and the target data. The retransfer signal RETARNS indicating the address of the transfer target area is received (S603), and then the request signal REQ0 output from the bus master 61 is output to the bus slave 62 (S604).

  Then, the controller 72 outputs the response signal RES0 output from the bus slave 62 to the bus master 61 via the selection circuit 74 (S605).

  Accordingly, the controller 72 can transmit the control instruction output from the bus master 61 to the bus slave 62 and transmit the response output from the bus slave 62 to the bus master 61. Further, when the controller 72 determines whether or not the target area indicated by the control instruction output by the bus master 61 is a retransfer target area, and determines that the target area is a retransfer area, the controller 72 By receiving the address indicating the retransfer area and the target data indicated by the control instruction, it is possible to prepare for a retransfer request.

  FIG. 7 is a flowchart for explaining the operation of the controller in the data transfer control device according to the embodiment of the present invention. Specifically, in the retransfer execution state of the data transfer control device according to one embodiment of the present invention, it is a flowchart for explaining the operation of the controller when maintaining this state.

  With reference to the figure, in the retransfer execution state, the controller 72 first sets the logic of the selection signal SEL to “H” and outputs the signal to the selection circuits 73 and 74 (S701). Next, the controller 72 outputs the retransfer signal RETRANS output from the snoop unit 71 via the selection circuit 73 as the request signal REQ1 to the bus slave 62 (S702).

  The controller 72 confirms the state of the request signal REQ0 output from the bus master 61, and determines whether or not the bus master 61 is accessing the bus slave 62 (S703). If the controller 72 determines that the bus master 61 is not accessing the bus slave 62 (No in S703), the controller 72 outputs the response signal RES0 output from the bus slave 62 to the bus master 61 (S706). Complete control. On the other hand, when the controller 72 determines that the bus master 61 is accessing the bus slave 62 (Yes in S703), the response signal RES0 output from the bus slave 62 is replaced with a response signal via the selection circuit 74. RES1 is output to the bus master 61 (S704). Subsequently, the controller 72 confirms the state of the request signal REQ0 output from the bus master 61, and determines whether or not the access of the bus master 61 to the bus slave 62 is completed (S705).

  When the controller 72 determines that the access of the bus master 61 to the bus slave 62 is not completed (No in S705), the controller 72 returns to the process of step S704. On the other hand, when the controller 72 determines that the access of the bus master 61 to the bus slave 62 has ended (Yes in S705), the controller 72 completes the retransfer control.

  In this way, the controller 72 retransmits data to the bus slave 62 by outputting the target data indicated by the retransfer signal RETRANS output from the snoop unit 71 to the retransfer area of the bus slave 62 as the request signal REQ1. And a response output from the bus slave 62 that has finished the re-transfer process can be transmitted to the bus master 61. Further, the controller 72 determines whether or not there is an access to the bus slave 62 of the bus master 61 during execution of the retransfer, and when determining that there is the access, the controller 72 replaces the bus slave 62. A response can be output to the bus master 61.

  In the computer system 1 configured as described above, the data transfer control device 70 determines whether or not the target area of the target data instructed by the bus master device is a retransfer target area in the bus slave 62 of the bus slave device. If it is determined that the target area is the retransfer target area, the data transfer control device 70 stores the target data for the retransfer target area. When receiving a retransfer request, the data transfer control device 70 outputs the stored target data to the bus slave 62 of the bus slave device instead of the bus master device.

  Therefore, according to the present embodiment, the data transfer control device 70 in the computer system 1 does not newly design the circuits of the bus 10, the bus master device, and the bus slave device, and the data transfer processing load of the bus master device and the bus 10 Reduction of usage rate can be realized. Further, the data transfer control device 70 can perform the retransfer process without affecting the usage rate of the bus 10 in the computer system 1.

  FIG. 8 is a diagram for explaining an example of data transfer processing in the computer system according to the embodiment of the present invention. That is, in the figure, the data when the processor 20 is a bus master device, the DMA controller 40 is a bus slave device for the processor 20, the DMA controller 40 is a bus master device, and the storage device 30 is a bus slave device for the DMA controller 40. The transfer process is described. Note that the configurations and operations of the peripheral device 50 and the data transfer control device 70 are the same as those in the above-described embodiment, and thus description thereof is omitted.

  The processor 20 generates a request signal REQ2 as a control instruction for the storage device 30 and outputs the request signal REQ2 to the data transfer control device 70. Further, the processor 20 receives the response signal RES2 indicating the end of the processing of the DMA controller 40 output from the data transfer control device 70. In this example, the processor 20 outputs a control instruction to the storage device 30, but is not limited to this, and may output a control instruction to the peripheral device 50, for example.

  Based on the request signal REQ3 output from the bus master 61 of the DMA controller 40, the storage device 30 holds the write target data indicated by the signal in the target area of the storage device 30 indicated by the signal. Further, as a response to the DMA controller 40, the storage device 30 generates a response signal RES3 and outputs the signal to the bus master 61 of the DMA controller 40.

  Based on the request signal REQ output from the data transfer control device 70, the bus slave 62 of the DMA controller 40 holds the write target data indicated by the signal in the target area of the bus slave 62 indicated by the signal, and the processor A signal indicating that a control instruction has been received from 20 is transmitted to the bus master 61 of the DMA controller 40 via the signal line W_SIG. In addition, the bus slave 62 of the DMA controller 40 receives a signal indicating the end of processing related to the control instruction from the bus master 61 of the DMA controller 40 via the signal line W_SIG. Based on the signal, the bus slave 62 of the DMA controller 40 resets the contents held in the bus slave 62 and generates a response signal RES0 as a response to the processor 20. The bus slave 62 outputs a response signal RES0 to the data transfer control device 70, generates a retransfer request signal REQ_RETRANS, outputs the signal to the data transfer control device 70, and retransfers data to the retransfer target area. Request.

  The bus master 61 of the DMA controller 40 holds in the bus slave 62 of the DMA controller 40 based on a signal indicating that a control instruction is received from the processor 20 transmitted from the bus slave 62 of the DMA controller 40 via the signal line W_SIG. The request data REQ3 indicating a control instruction for the storage device 30 is generated with reference to the received data, and the request signal REQ3 is output to the storage device 30. Further, the bus master 61 of the DMA controller 40 sends a signal indicating that the processing related to the control instruction received from the processor 20 is completed based on the response signal RES3 output from the storage device 30 via the signal line W_SIG. To the bus slave 62. In this example, the bus master 61 of the DMA controller 40 outputs a control instruction to the storage device 30, but the present invention is not limited to this. For example, the bus master 61 of the DMA controller 40 may output a control instruction to the peripheral device 50. good.

  According to the present embodiment, the data transfer control device 70 determines whether the target area of the target data instructed by the processor 20 is a retransfer target area in the bus slave 62 of the DMA controller 40, and the target area is When determining that the area is the retransfer target area, the data transfer control device 70 stores the target data for the retransfer target area. When the data transfer control device 70 receives a retransfer request from the bus slave 62 of the DMA controller 40, the data transfer control device 70 outputs the stored target data to the bus slave 62 of the DMA controller 40 instead of the processor 20. Therefore, according to this modification, the data transfer control device 70 in the computer system 1A does not newly design the circuits of the bus 10, the processor 20, and the DMA controller 40, and the data transfer processing load of the processor 20 and the bus 10 Reduction of usage rate can be realized. Further, the data transfer control device 70 can perform retransfer processing without affecting the usage rate of the bus 10 in the computer system 1A. Furthermore, according to the present embodiment, the data transfer control device 70 holds the contents of the bus slave 62 of the DMA controller 40 that is reset when the processing of the DMA controller 40 ends, and the processor 20 when the processing of the DMA controller 40 ends. Instead, the data transfer processing load of the processor 20 can be reduced by retransferring the held contents to the bus slave 62 of the DMA controller 40.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, a specific feature (technical matter) in one embodiment is appropriately improved and added to another embodiment or the other implementation. Specific features in the form can be substituted, and such form is also included in the gist of the present invention.

  The present invention can be widely used in the field of computer systems that perform data transfer via a bus.

DESCRIPTION OF SYMBOLS 1 ... Computer system 10 ... Bus 20 ... Processor 30 ... Storage device 40 ... DMA controller 50 ... Peripheral device 61 ... Bus master 62 ... Bus slave 70 ... Data transfer control device 71 ... Snoop part 72 ... Controller 73, 74 ... Selection circuit 710 ... Address table 711 ... Comparator 712 ... Data storage control unit 713 ... Data storage unit 7101 ... Re-transfer target area start address column 7102 ... Data address column

Claims (7)

A data transfer control device connected to a bus,
A snoop unit for monitoring a write request sent from the bus master device via the bus;
A controller for controlling whether to output the write request to a bus slave device,
The snoop part is
A data storage unit that stores data in accordance with the write request when the target area indicated by the write request matches at least one retransmission target area;
When the snoop unit stores the data according to the write request in the data storage unit, the data according to the stored write request based on the re-transfer request received from the bus slave device by the controller To the controller, and the controller controls the bus slave device to output data in accordance with the write request output from the snoop unit on behalf of the bus master device.
Data transfer control device. The snoop part is
An address table storing an address indicating the at least one retransmission target area;
A comparator that determines whether an address of the target area indicated by the write request matches an address indicating the at least one retransmission target area stored in the address table;
The data transfer control device according to claim 1.   The data transfer control device according to claim 2, wherein the snoop unit stores data associated with the at least one retransmission target area in the data storage unit.   While the controller performs control to output data according to the write request output from the snoop unit to the bus slave device, there is a predetermined access request from the predetermined device to the bus slave device. The data transfer control device according to claim 1, wherein a response to the predetermined device is made instead of the bus slave device. With bus,
A bus master device connected to the bus;
A data transfer control device connected to the bus;
A bus slave device connected to the bus via the data transfer control device, and a computer system comprising:
The data transfer control device includes:
A snoop unit for monitoring a write request sent from the bus master device;
A controller for controlling whether to output the write request to the bus slave device,
The snoop part is
When the target area indicated by the write request matches at least one re-transfer target area, the data according to the write request is stored,
When the snoop unit stores data according to the write request, based on the re-transfer request received from the bus slave device by the controller, outputs the data according to the stored write request to the controller The controller controls to output data according to the write request output from the snoop unit to the bus slave device instead of the bus master device.
Computer system. A DMA controller connected to the bus;
The DMA controller functions as the bus slave device connected to the bus via the data transfer control device;
The computer system according to claim 5. A data transfer control method in a computer system, executed by a data transfer control device,
Monitoring the write request sent from the bus master device via the bus by the snoop unit of the data transfer control device;
Controlling whether the controller of the data transfer control device outputs the write request to a bus slave device,
The monitoring is
Determining whether the target area indicated by the write request matches at least one area to be retransmitted;
Storing the data according to the write request in a predetermined storage area when it is determined that the target area matches the at least one retransmission target area;
In the case where the data according to the request write attempts before Kisho in the predetermined storage area is stored, based on the retransmission request received from said bus slave device, according to the predetermined the write request stored in the storage area data Output to the controller,
The control is performed such that when data according to the write request stored in the predetermined storage area is received, data according to the write request is output to the bus slave device instead of the bus master device. Including,
Data transfer control method.