JP2018128845A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of reducing a process load of a first processor when the first processor and multiple second processors transmit and receive data mutually between each other via a dual port memory.SOLUTION: A multiprocessor system includes: a first board 1 on which a first dual port memory 51 connected between a first CPU 11 and a backboard 6 and a first bus controller 31 connected to the backboard-6 side of the first dual port memory 51 are mounted; second dual port memories 52_1 to 52_n connected between second CPUs 12_1 to 12_n and the backboard 6; and a second bus controller connected to the backboard-6 sides of the second dual port memories 52_1 to 52_n. The first bus controller 31 and second bus controllers 32_1 to 32_n are mutually connected with each other via the backboard 6.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a multiprocessor system.

  For example, in a multiprocessor system for industrial equipment such as a digital relay, as shown in FIG. 8, a first CPU (Central Processing Unit: processor) 10, a second CPU 30, and a bidirectional connection between the first CPU 10 and the second CPU 30 are provided. There is known a system in which a dual port memory 50 having a port is provided, and the first CPU 10 and the second CPU 30 exchange data one-on-one via the dual port memory 50 (see Patent Document 1).

  In addition, as shown in FIG. 9, a plurality of second boards 200_1 to 200 each mounting a first board 100 on which a first CPU 10 that performs overall control and a plurality of second CPUs 20_1 to 20_n that individually control each element function are mounted. 200_n and a first board 100 and a backboard 6P to which a plurality of second boards 200_1 to 200_n are mounted, respectively, the first CPU 10 and the plurality of second CPUs 20_1 to 20_n via the backboard bus 60P of the backboard 6P. There is known a method for exchanging data with the. In such a system, for example, the first CPU 10 and the plurality of second CPUs 20_1 to 20_n are connected to each other via dual port memories provided respectively on the second boards 200_1 to 200_n corresponding to the second CPUs 20_1 to 20_n. To exchange data.

JP 2004-64892 A

  In the system as shown in FIG. 9, for example, when the same command data is notified from the first CPU 10 to all the second CPUs 20_1 to 20_n, the first CPU 10 corresponds to each of the second CPUs 20_1 to 20_n via the backboard bus 60P. It was necessary to individually write the same command data to each of the dual port memories. For example, when the second CPU 20_n uses the data of the second CPU 20_1, the first CPU 10 reads the data of the second CPU 20_1 from the dual port memory of the second board 200_1, and the first CPU 10 reads the data of the second CPU 20_1 to the dual port memory of the second board 200_n. I had to write data. As described above, there is a problem that the processing load on the first CPU 10 is large in a multiprocessor system that exchanges data in a one-to-many manner.

  In view of the above problems, the present invention provides a multi-processor capable of reducing the processing load on the first processor when data is exchanged between each of the first processor and the plurality of second processors via the dual port memory. An object is to provide a processor system.

  In order to achieve the above object, a multiprocessor system according to an aspect of the present invention includes a first board on which a first processor is mounted, a plurality of second boards each having a second processor, a first board, and a plurality of boards. The second board is provided with a backboard for connecting the first board and each of the plurality of second boards, and the first board is provided between the first processor and the backboard. A first dual-port memory to be connected; a first bus controller connected to the backboard side of the first dual-port memory and controlling access on the backboard side of the first dual-port memory; Each of the boards includes a second dual port memory connected between the corresponding second processor and the backboard, and a corresponding second dual port. A second bus controller connected to the backboard side of the second memory and controlling the access on the backboard side of the corresponding second dual-port memory, and between the first bus controller and the plurality of second bus controllers And connected by a backboard.

  According to the present invention, there is provided a multiprocessor system capable of reducing the processing load on the first processor when data is exchanged between each of the first processor and the plurality of second processors via the dual port memory. it can.

1 is a block diagram illustrating a basic configuration of a multiprocessor system according to an embodiment of the present invention. It is a block diagram explaining the structure of the multiprocessor system which concerns on embodiment of this invention. It is a figure explaining an example of the area division of each storage area of the 1st dual port memory and the 2nd dual port memory. It is a figure explaining an example of the address signal which a 1st access controller outputs. 6 is a timing chart for explaining the operation of each access controller when the first access controller outputs the address value of the data write area dedicated to the first CPU. 10 is a timing chart for explaining the operation of each access controller when the first access controller outputs the address value of one data writing area dedicated to the second CPU. It is a timing chart explaining an example of the signal which general CPU transmits / receives between DPRAM. It is a block diagram explaining an example of the conventional multiprocessor system. It is a block diagram explaining an example of the conventional multiprocessor system.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant description is omitted. However, the embodiment described below exemplifies a system or apparatus for embodying the technical idea of the present invention, and the technical idea of the present invention is a system or apparatus exemplified in the following embodiment. It is not something specific. The technical idea of the present invention can be variously modified within the technical scope described in the claims.

(Multiprocessor system)
As shown in FIG. 1, a multiprocessor system according to an embodiment of the present invention includes a first board 1 on which a first CPU 11, a first dual port memory 51, and a first bus controller 31 are mounted, and second CPUs 12_1, 12_2,. , 12_n, second dual port memories 52_1, 52_2,..., 52_n and a plurality of second boards 2_1, 2_2,..., 2_n (n: 2) on which the second bus controllers 32_1, 32_2,. And a backboard bus 60 for connecting the first board 1 and the plurality of second boards 2_1 to 2_n by mounting the first board 1 and the plurality of second boards 2_1 to 2_n. And a backboard 6.

  The first CPU 11 is a processor that performs overall control of the multiprocessor system according to the embodiment of the present invention by controlling each of the plurality of second boards 2_1 to 2_n. The first dual port memory 51 is connected between the first CPU 11 and the backboard 6. One port of the first dual port memory 51 is connected to the first CPU 11, and the other port is connected to the backboard 6. The first bus controller 31 is connected to a port on the backboard 6 side of the first dual port memory 51 and controls access on the backboard side of the first dual port memory 51.

  Each of the second CPUs 12_1 to 12_n is, for example, a processor that individually controls each element of the industrial device in a multiprocessor system that controls the industrial device. Each of the second dual port memories 52_1 to 52_n is connected between the second CPUs 12_1 to 12_n and the backboard 6. Ports on one side of the second dual port memories 52_1 to 52_n are connected to the second CPUs 12_1 to 12_n, and ports on the other side are connected to the backboard 6, respectively. Each of the second bus controllers 32_1 to 32_n is connected to a port on the backboard 6 side of each of the second dual port memories 52_1 to 52_n, and controls access on the backboard side of each of the second dual port memories 52_1 to 52_n.

  Between each of the first bus controller 31 and the second bus controllers 32_1 to 32_n, the first board 1 and the plurality of second boards 2_1 to 2_n are mounted on the backboard bus 60, so Connection is made via the board bus 60.

  Hereinafter, with reference to the block diagram shown in FIG. 2, the first board 1, the second board 2 — i (i is an integer from 1 to n) that is one of the plurality of second boards 2 _ 1 to 2 _n, Details of the back board 6 on which the second board 2_i is mounted will be described.

  As shown in FIG. 2, the first bus controller 31 includes a first CPU number setting unit 311 that sets a number for identifying the first CPU 11 for the first board 1, and a backboard 6 side of the first dual port memory 51. A first access controller 312 for controlling access. The number for identifying the first CPU 11 is determined by, for example, manual setting using a jumper switch or the like, or setting values stored as parameters in other storage devices as initialization processing, and is held by the first access controller 312. The

  Similarly, the second bus controller 32_i (i is an integer of 1 to n), which is one of the plurality of second bus controllers 32_1 to 32_n, corresponds to the second CPU 12_i (mounted on the same second board 2_i). A second CPU number setting unit 321_i that sets an identification number for the second board 2_i and a second access controller 322_i that controls access on the backboard 6 side of the second dual-port memory 52_i. The number for identifying the second CPU 12_i is determined by, for example, manual setting using a jumper switch or the like, or setting values stored as parameters in other storage devices as initialization processing, and is determined by the corresponding second access controller 322_i. Retained.

  The first dual port memory 51 includes a first input / output port (first processor side port) 511 connected to the first CPU 11, and a second input / output port (first input port) connected to the first bus controller 31 and the backboard bus 60. 1 backboard side port) 512 and a storage unit 513 for storing data.

  Similarly, the second dual port memory 52_i includes a first input / output port (second processor side port) 521_i connected to the second CPU 12_i, and a second input / output connected to the second bus controller 32_i and the backboard bus 60. A port (second backboard side port) 522 — i and a storage unit 523 — i for storing data.

  Between the first input / output port 511 of the first dual port memory 51 and the first CPU 11, a chip select signal line L1 for the chip select signal L_CS1, a data read signal line L2 for the data read signal L_RD1, and a data write It is connected to a data write signal line L3 for signal L_WR1. In addition, the first CPU 11 and the first input / output port 511 are connected by an address bus B1 for the address signal L_Addr1 and a data bus B2 for the data signal L_Data1.

  Similarly, a chip select signal line L1i for a chip select signal L_CS2i and a data read signal line L2i for a data read signal L_RD2i are provided between the first input / output port 521_i and the second CPU 12_i of the second dual port memory 52_i. A data write signal line L3i for data write signal L_WR2i is provided. In addition, the second CPU 12_i and the first input / output port 521_i are connected by an address bus B1i for the address signal L_Addr2i and a data bus B2i for the data signal L_Data2i.

  Between the second input / output port 512 of the first dual port memory 51 and the first access controller 312, a chip select signal line L4 for the chip select signal R_CS1, a data read signal line L5 for the data read signal R_RD1, Connection is made by data write signal line L6 for data write signal R_WR1. In addition, the second input / output port 512 and the first access controller 312 are connected by an address bus B3 for the address signal R_Addr1 and a data bus B4 for the data signal R_Data1.

  Similarly, a chip select signal line L4i for the chip select signal R_CS2i and a data read signal line for the data read signal R_RD2i are between the second input / output port 522_i and the second access controller 322_i of the second dual port memory 52_i. L5i is connected to data write signal line L6i for data write signal R_WR2i. In addition, the second input / output port 522_i and the second access controller 322_i are connected by an address bus B3i for the address signal R_Addr1 and a data bus B4i for the data signal R_Data2i.

  The backboard bus 60 includes a control signal bus 61 for the access control signal OPREQ, a backboard address bus 62 for the address signal R_Addr1, and a backboard data bus 63 for the data signal R_Data1 / 2i. The control signal bus 61 is connected to the first access controller 312 via the control signal line L7 for the access control signal OPREQ, and is connected to the second access controller 322_i via the control signal line L7i for the access control signal OPREQ. The backboard address bus 62 is connected to the address buses B3 and B3i, respectively. Backboard data bus 63 is connected to data buses B4 and B4i, respectively.

  As shown in FIG. 3, each storage area of the storage unit 513 and the storage units 523_1 to 523_n includes a data write area 501 dedicated to the first CPU 11 and a plurality of data write areas dedicated to the plurality of second processors 12_1 to 12_n. 502_1 to 502_n. As common to the storage unit 513 and the storage units 523_1 to 523_n, the data write area 501 has a range of address values from A1 to less than A2_1, the data write area 502_1 has a range of address values of less than A2_1 to A2_2,. The data write area 502_n has an address value set in a range from A2_n to less than A3.

(Operation of the first access controller 312)
As shown in FIG. 4, the first access controller 312 defined by the first CPU number setting unit 311 to be an access controller mounted on the first board 1 having the first CPU 11 includes the storage unit 513 and the storage unit 523_1. An address signal R_Addr1 including each address value of a plurality of data write areas 501 and 502_1 to 502_n dedicated to the first CPU 11 and the plurality of second CPUs 12 in each storage area of ˜523_n in a predetermined cycle is generated.

  The address signal R_Addr1 is output to the first dual port memory 51 and the backboard address bus 62 via the address bus B3. For example, in one cycle P, the address signal R_Addr1 is derived from each address value in the address range of the data write area 501 dedicated to the first CPU 11 (the address value is a range from A1 to less than A2_1), and the data write area dedicated to the second CPU 12_n. It is generated so as to be sequentially output up to an address range of 502_n (a range of address values from A2_n to less than A3). Each address range of the data write areas 501, 502_1 to 502_n includes each address value sequentially while being incremented from the start address to the end address.

  The first access controller 312 generates an access control signal OPREQ for controlling access to any of the first dual port memory 51 and the plurality of second dual port memories 52_1 to 52_n in conjunction with the address signal R_Addr1. The first access controller 312 outputs the access control signal OPREQ to the control signal bus 61 via the control signal line L7. The first access controller 312 generates an address signal R_Addr1 and an access control signal OPREQ, thereby generating a signal indicating that one of the first CPU 11 and the plurality of second CPUs 12_1 to 12_n is to read a dedicated data write area.

  For example, as shown in FIG. 5, the first access controller 312 has an address value of the output address signal R_Addr1 corresponding to the data write area 501 dedicated to the first CPU 11 (mounted on the same first board 1). When the address value is A1, the data read signal R_RD1 is asserted and negated in conjunction with the assertion (valid state) and negation (invalid state) of the access control signal OPREQ. The data signal R_Data1 including the data in the storage unit 513 corresponding to A1 is output to the backboard data bus 63.

  Specifically, after the address value A1 of the address signal R_Addr1 output by the first access controller 312 at time t1 is stabilized, the first access controller 312 asserts the access control signal OPREQ at time t2. The access control signal OPREQ is input to the multiple second boards 2_1 to 2_n via the control signal bus 61, respectively. The first access controller 312 negates the access control signal OPREQ at time t6 before time t8 when the output address signal R_Addr1 changes next.

  When the address value of the address signal R_Addr1 to be output is the address value A1 of the data write area 501 dedicated to the first CPU 11, the first access controller 312 receives the data read signal R_RD1 in response to the assertion of the access control signal OPREQ at time t3. Is asserted. The first access controller 312 negates the data read signal R_RD1 at time t7 in response to the negation of the access control signal OPREQ at time t6. As a result, the first access controller 312 outputs a signal indicating that the first dual port memory 51 reads the data write area dedicated to the first CPU 11.

  In response to the assertion of the data read signal R_RD1, the first dual-port memory 51 reads data corresponding to the address value of the address signal R_Addr1 from the storage unit 513, and outputs it to the backboard data bus 63 as the data signal R_Data1. The data signal R_Data1 is input to the plurality of second boards 2_1 to 2_n via the backboard data bus 63 of the backboard 6.

  On the other hand, as shown in FIG. 6, the first access controller 312 outputs the address value A2_i of the data write area 502_i dedicated to the second CPU 12_i whose address value of the output address signal R_Addr1 is one of the plurality of second CPUs 12_1 to 12_n. (That is, not the address value A1 of the data write area 501 dedicated to the first CPU 11 corresponding to the first access controller 312), the data write signal R_WR1 is asserted in conjunction with the assertion and negation of the access control signal OPREQ. And negate. As a result, the first access controller 312 causes the first dual port memory 51 to copy the data signal R_Data2i input via the backboard data bus 63 to the data write area 502_i dedicated to the second CPU 12_i in the storage unit 513. .

  Specifically, after the address value of the address signal R_Addr1 output by the first access controller 312 is stabilized at time t1, the first access controller 312 asserts the access control signal OPREQ at time t2. The access control signal OPREQ is input to the multiple second boards 2_1 to 2_n via the control signal bus 61, respectively. The first access controller 312 negates the access control signal OPREQ at time t6 before time t8 when the output address signal R_Addr1 changes next.

  When the address value of the output address signal R_Addr1 is the address value A2_i of the data write area 502_i dedicated to the second CPU 12_i, which is one of the plurality of second CPUs 12_1 to 12_n (that is, dedicated to the first CPU 11). From the time t4 to the time t5 when the value of the data signal R_Data2i output from the second dual-port memory 52_i is stabilized after the access control signal OPREQ is asserted at the time t3. In the meantime, the data write signal R_WR1 is asserted and negated. The first access controller 312 causes the first dual port memory 51 to copy the data signal R_Data2i input via the backboard data bus 63 to the data write area 502_i dedicated to the second CPU 12_i in the storage unit 513.

  The timings from time t3 to time t5 are, for example, the timing at which the access control signal OPREQ is asserted and the clock timing of the clock oscillator mounted on each of the first board 1 and the second boards 2_1 to 2_n. The interval between them is shorter than the interval at which the address signal R_Addr1 changes (the time from time t1 to time t8).

(Operations of the second access controllers 322_1 to 322_n)
Hereinafter, regarding the operation of the second access controllers 322_1 to 322_n, the second board 2_i (i is an integer of 1 to n) which is one of the plurality of second boards 2_1 to 2_n and the plurality of boards excluding the second board 2_i. A description will be given by appropriately using i and k defined as the second board 2_k (k is an integer of 1 to n, k ≠ i) which is one of the second boards 2_1 to 2_n.

  As shown in FIG. 5, the second access controller 322_i has an address value of the address signal R_Addr1 input from the backboard address bus 62 that is the address value A1 of the data write area 501 dedicated to the first CPU 11 (that is, The data write signal R_WR2i is asserted and negated in conjunction with the assertion and negation of the access control signal OPREQ when the address value A2_i of the corresponding data write area 502_i dedicated to the second CPU 12_i is not. Accordingly, the second access controller 322_i transfers the data value of the data signal R_Data2i input from the backboard data bus 63 to the corresponding second dual-port memory 52_i, and the data writing area 501 dedicated to the first CPU 11 of the storage unit 523_i. To make a copy.

  Specifically, the second access controller 322_i has the case where the address value of the address signal R_Addr1 input from the backboard address bus 62 is the address value of the dedicated data write area of the first CPU 11 and the second CPUs 12_1 to 12_n. The chip select signal R_CS2i is asserted. When the address value of the input address signal R_Addr1 is the address value of the data writing area dedicated to the first CPU 11 (that is, not the corresponding data writing area dedicated to the second CPU 12_i), the second access controller 322_i After the access control signal OPREQ input via the bus 61 is asserted, the data write signal R_WR2i is between the time t4 and the time t5 when the data signal R_Data1 output from the first dual port memory 51 is stabilized. Is asserted and negated. Thereby, the data in the data writing area dedicated to the first CPU 11 in the first dual port memory 51 is copied to the data writing area dedicated to the first CPU 11 in the second dual port memory 52_i.

  As shown in FIG. 5, the operation of the other second access controller 322_k is the same as that of the second access controller 322_i. The timings from time t3 to time t5 are, for example, the timing at which the access control signal OPREQ is asserted and the clock timing of the clock oscillator mounted on each of the first board 1 and the second boards 2_1 to 2_n. The interval between them is shorter than the interval at which the address signal R_Addr1 changes (the time from time t1 to time t8).

  On the other hand, as shown in FIG. 6, in the second access controller 322_i, the address value of the address signal R_Addr1 input from the backboard address bus 62 is the address value A2_i of the corresponding data write area 502_i dedicated to the second CPU 12_i. In this case, the data read signal R_RD1 is asserted and negated in conjunction with the assertion and negation of the access control signal OPREQ. As a result, the second access controller 322_i causes the second dual port memory 52_i to output the data signal R_Data1 including the data in the storage unit 523_i corresponding to the address value A2_i to the backboard data bus 63.

  Specifically, the second access controller 322_i has the case where the address value of the address signal R_Addr1 input from the backboard address bus 62 is the address value of the dedicated data write area of the first CPU 11 and the second CPUs 12_1 to 12_n. The chip select signal R_CS2i is asserted. When the address value of the input address signal R_Addr1 is the address value A2_i of the data write area 502_i dedicated to the second CPU 12_i, the second access controller 322_i responds to the assertion of the access control signal OPREQ at time t3. R_RD2i is asserted, and at time t7, the data read signal R_RD2i is negated according to the negation of the access control signal OPREQ. Thereby, the second access controller 322_i outputs the data of the address value A2_i of the data writing area 502_i dedicated to the second CPU 12_i of the storage unit 523_i to the second dual port memory 52_i to the backboard data bus 63 as the data signal R_Data2i. To do.

  When the address value of the address signal R_Addr1 input from the backboard address bus 62 is the address value A2_i of the data writing area 502_i dedicated to the second CPU 12_i (that is, the corresponding data dedicated to the second CPU 12_k) From the time t4 to the time t5 when the data signal R_Data2i output from the second dual port memory 52_i becomes stable after the access control signal OPREQ input via the control signal bus 61 is asserted. In the meantime, the data write signal R_WR2k is asserted and negated. As a result, the data in the data writing area dedicated to the second CPU 12_i in the second dual port memory 52_i is copied to the data writing area dedicated to the first CPU 12_i in the second dual port memory 52_k.

(CPU operation)
Since the first CPU 11 and the plurality of second CPUs 12_1 to 12_n operate in the same manner and can adopt a general configuration, as shown in FIG. 7, the first CPU 11 and the plurality of second CPUs 12_1 to 12_n are any one of them. Address signal L_Addrx, chip select signal L_CSx, transmitted between CPUx and dual port memory (DPRAM) x which is one of first dual port memory 51 and second dual port memories 52_1 to 52_n corresponding to CPUx, The data read signal L_RDx, data write signal L_WRx, and data signal L_Datax will be described as an example.

  At time t1, CPUx outputs an address signal L_Addrx that designates the address of the storage area of DPRAMx, and asserts a chip select signal L_CSx. In response to the assertion of data read signal L_RDx at time t2, DPRAMx outputs the data stored at the designated address to CPUx as data signal L_Datax via the data bus. Further, at time t5, the CPU x outputs an address signal L_Addrx that designates the address of the DPRAMx storage area, and asserts the chip select signal L_CSx. In response to the assertion of the data write signal L_WRx at time t6, the DPRAMx stores the data signal L_Datax input from the CPUx via the data bus at a specified address.

  As described above, according to the multiprocessor system of the embodiment of the present invention, the first bus that controls the access on the backboard side of each of the first dual port memory 51 and the second dual port memories 52_1 to 52_n. Since the controller 31 and the second bus controllers 32_1 to 32_n are connected to each other by the back board 6, the first dual port memory 51 and the second bus controller 32_1 to 32_n are connected to the first bus controller 31 and the second bus controllers 32_1 to 32_n in a predetermined cycle. The storage areas of the two dual-port memories 52_1 to 52_n can be synchronized.

  For this reason, according to the multiprocessor system according to the embodiment of the present invention, for example, during the period P1 in FIG. 4, the first CPU 11 has a data write area dedicated to the first CPU 11 in the corresponding first dual port memory 51. The new data written in is copied to the data writing area dedicated to each first CPU 11 in the second dual port memories 52_1 to 52_n at the latest during the period of the next period P2. Therefore, the second CPUs 12_1 to 12_n can reliably read the same data as the new data written by the first CPU 11 from the second dual port memories 52_1 to 52_n from the start of the next period P3.

  Thus, according to the multiprocessor system according to the embodiment of the present invention, for example, when the first CPU 11 notifies the second CPUs 12_1 to 12_n of the same data, the second dual port memories respectively corresponding to the second CPUs 12_1 to 12_n. It is not necessary to individually control 52_1 to 52_n, and an operation of writing once in the data writing area dedicated to the first CPU 11 of the first dual port memory 51 may be performed. When the second CPU 12_k uses the data of the second CPU 12_i, the first CPU 11 reads the data of the second CPU 12_i from the second dual-port memory 52_i corresponding to the second CPU 12_i, and then the first CPU 11 corresponds to the second CPU 12_k. There is no need to write to the memory 52_i, and the second CPU 12_i may perform an operation of writing once in the data writing area dedicated to the second CPU 12_i of the second dual-port memory 52_i.

  As described above, according to the multiprocessor system according to the embodiment of the present invention, the processing load on the first CPU 11 when data is exchanged between the first CPU 11 and the plurality of second CPUs 12_1 to 12_n via the dual port memory. Can be reduced. Further, since the first board 1 and the plurality of second boards 2_1 to 2_n may have the same configuration, they are defined by being identified by the first CPU number setting unit 311 and the second CPU number setting units 321_1 to 321_n. Therefore, parts and circuit configurations can be shared, and manufacturing costs can be reduced.

(Other embodiments)
While embodiments of the present invention have been described as described above, it should not be understood that the description and drawings that form part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the embodiment already described, the data writing area 501 and the plurality of data writing areas 502_1 to 502_n are shown as continuous areas in FIG. 3, but the data writing area dedicated to the first CPU 11 and the plurality of second data writing areas 502_1 to 502_n are shown in FIG. As long as the same definition is shared by the first access controller 312 and the second access controllers 322_1 to 322_i as a plurality of dedicated data write areas for the processors 12_1 to 12_n, discontinuous addresses may be used.

  In addition, of course, the present invention includes various embodiments that are not described here, such as configurations in which the respective configurations described in the above embodiments are arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 1st board 2 2nd board 6 Back board 11 1st CPU (1st processor)
12_1-12_n 2nd CPU (2nd processor)
31 First bus controller 32_1 to 32_n Second bus controller 51 First dual port memory 52_1 to 52_n Second dual port memory 501 Data write area 502_1 to 502_n Data write area A1, A2_1 to A2_n, A3 Address value

Claims (5)

A first board carrying a first processor;
A plurality of second boards each carrying a second processor;
In a multiprocessor system comprising: a backboard for connecting each of the first board and the plurality of second boards by mounting the first board and the plurality of second boards;
The first board is connected to a first dual port memory connected between the first processor and the back board, and to the back board side of the first dual port memory. A first bus controller that controls access on the backboard side;
Each of the plurality of second boards is connected to a second dual port memory connected between the corresponding second processor and the back board, and to the back board side of the corresponding second dual port memory. A second bus controller for controlling access on the backboard side of the corresponding second dual port memory,
The multiprocessor system, wherein the first bus controller and the plurality of second bus controllers are connected to each other by the backboard. Each storage area of the first dual port memory and the plurality of second dual port memories has a plurality of dedicated data write areas for the first processor and the plurality of second processors,
The first bus controller and the plurality of second bus controllers respectively store data written in the data write area dedicated to the first processor by the first dual port memory in each of the plurality of second dual port memories. Copying to the data writing area dedicated to the first processor,
In the first bus controller and the plurality of second bus controllers, one second dual port memory writes data written in a corresponding data write area dedicated to the second processor to the first dual port. 2. The multiprocessor system according to claim 1, wherein each of the plurality of second dual-port memories excluding a memory and the one second processor is copied to a data write area dedicated to the one second processor. . When the first bus controller outputs a signal indicating that the data writing area dedicated to the first processor is read from the first dual port memory, the first bus controller is dedicated to the first processor. Output data of the data writing area to the backboard,
Each of the plurality of second bus controllers sends the data output by the first dual port memory to the corresponding second dual port memory, and the dedicated second processor is dedicated to the first processor of the second dual port memory. 3. The multiprocessor system according to claim 2, wherein the data is written in a data writing area. When the first bus controller outputs a signal indicating that the corresponding data write area dedicated to the second processor is read from one second dual port memory, the corresponding second The bus controller causes the one second dual port memory to output data in the data writing area dedicated to the one second processor to the backboard,
The first bus controller sends the data output from the one second dual port memory to the first dual port memory, and the data write area dedicated to the one second processor of the first dual port memory. To copy
Each of the plurality of second bus controllers sends the data output by the first dual port memory to the corresponding second dual port memory, and the dedicated second processor is dedicated to the first processor of the second dual port memory. 4. The multiprocessor system according to claim 2, wherein the multiprocessor system is copied to a data writing area.   The first bus controller has a plurality of data write dedicated to each of the first processor and the plurality of second processors, which are common to the storage areas of the first dual port memory and the plurality of second dual port memories. An address signal including each address value of the area in a predetermined cycle, and an access control signal for controlling access to either the first dual port memory or the plurality of second dual port memories by interlocking with the address signal. 5. The multiprocessor according to claim 3, wherein a signal indicating that the data writing area dedicated to any one of the first processor and the plurality of second processors is read is output. system.

Images