JP2016110458A - Programmable logic controller, basic unit, control method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve usability for refreshing a device memory in a programmable logic controller (PLC).SOLUTION: A PLC repeatedly executes a user program for every scan. A first update unit 75 refreshes data held by an expansion unit and data held by a basic unit in a refresh period of a scan time. A second update unit 76 refreshes data held by the expansion unit and data held by the basic unit in a fixed period of the scan time.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a programmable logic controller, a basic unit, a control method, and a program.

  In general, a programmable logic controller (PLC) includes a basic unit (also called a CPU unit) and an expansion unit (Patent Document 1). The basic unit and the expansion unit exchange data (so-called refresh communication) in a period called a refresh period that is synchronized with the timing at which a normal ladder program is executed.

  By the way, the basic unit and the extension unit can also synchronize control with each other by inter-unit synchronization processing. Specifically, internal processing of one or a plurality of expansion units and predetermined processing (such as ladder execution processing) in the basic unit can be executed in synchronization.

  Generally, in order to exchange data between the basic unit and the extension unit in the inter-unit synchronization process, the user must separately write a direct communication command word in the ladder program for inter-unit synchronization. An instruction word for direct communication is an instruction word for exchanging data between the basic unit and the expansion unit at the timing when the basic unit executes the instruction word. This direct communication command allows data to be exchanged without waiting for the timing of refresh communication that is repeatedly executed at each scan, thus providing advantages such as high-speed control of external devices using inter-unit synchronization processing. It is done.

Japanese Patent Laid-Open No. 2004-052672

  However, it is troublesome for the user to write direct communication command words one by one in the ladder program for synchronization between units, which is troublesome. For example, even when part or all of the description of a normal ladder program (so-called flat field ladder program) that is repeatedly executed at every scan, not inter-unit synchronization, is diverted to a ladder program for inter-unit synchronization, Separately, direct communication commands must be added, and eventually, a program change operation is required.

  Therefore, in the same way as the refresh communication repeatedly executed at each scan, a method of exchanging data subject to synchronization between units in batch in synchronization with the timing at which the ladder program for synchronization between units is executed ( So-called inter-unit synchronous refresh) can be considered. This inter-unit synchronous refresh is a different concept from the normal refresh that is executed every scan, so a dedicated device that is different from the device that is the target of normal refresh is used as the device that is subject to the inter-unit synchronous refresh. Be prepared.

  However, since there is a lot of data that should be shared between the basic unit and the expansion unit, if you try to execute the update process (refresh) so that all of the data matches between units during the inter-unit synchronous refresh period, Many dedicated devices mentioned above must be prepared. As a result, creating a ladder program for inter-unit synchronization using a dedicated device is a cumbersome operation for the user and takes time and effort. Similarly, as described above, when part or all of the description of the flat ladder program is diverted to the ladder program for inter-unit synchronization, a device that is subject to normal refresh is separately designated as the target of inter-unit synchronous refresh. In the end, this method also requires a program change operation.

  In addition, when the number of dedicated devices that are subject to inter-unit synchronous refresh is large, the inter-unit synchronous refresh period becomes long. As a result, the merits of inter-unit synchronization processing such as high-speed control of external devices will be offset. If a part of such data can be selected so that it can be executed in a period other than the inter-unit synchronous refresh period, an increase in the refresh period will be suppressed. Therefore, the present invention prepares a device that can select the update timing of data to be shared between the basic unit and the expansion unit, thereby preventing a decrease in the merit of the inter-unit synchronization processing while changing the program. The purpose is to reduce the workload and improve usability.

The present invention is, for example,
A programmable logic controller having a basic unit that repeatedly executes a user program for each scan, and an expansion unit connected to the basic unit,
The expansion unit is
An interface to which an external device is connected;
A storage unit in which a device value related to an input value from the external device via the interface or an output value to the external device via the interface is stored, and a device for sharing data with the basic unit is allocated;
An expansion unit timer that counts the clock and measures time,
With
The basic unit is
A basic unit timer that counts the clock and measures time,
Synchronization means for synchronizing the timer values of the extension unit timer and the basic unit timer;
First update means for matching the data held by the extension unit and the data held by the basic unit within a refresh period for each scan;
Based on the timer value of the basic unit timer synchronized with the timer value of the extension unit timer by the synchronization means, the data held by the extension unit within the period of processing executed at regular intervals during scanning and the basic Second update means for matching the data held by the unit;
With
The programmable unit characterized in that the device of the extension unit described in the user program can be set as an update target by the first update means and / or an update target by the second update means. Provide logic controller.

  According to the present invention, usability can be improved.

Diagram showing an example of a PLC system The figure which shows an example of the user program The figure which shows an example of a program creation assistance apparatus The figure which shows an example of PLC Diagram for explaining scan time Diagram showing the relationship between scan time and synchronization period Diagram showing basic unit functions Diagram showing the functions of the expansion unit The figure which shows the function of the program creation support device Flowchart showing processing including synchronization and refresh between units at scan time Flowchart showing synchronous refresh performed on expansion unit Diagram showing the temporal relationship between synchronous refresh and internal processing Diagram showing data transmission and reception between multiple buffer units and multiple expansion units Flowchart showing scan processing executed along the timing of synchronization between units Flowchart showing scan processing executed along the timing of synchronization between units The figure which shows an example of GUI for selecting either synchronous refresh or batch refresh

  An embodiment of the present invention is shown below. The individual embodiments described below will help to understand various concepts, such as the superordinate concept, intermediate concept and subordinate concept of the present invention. Further, the technical scope of the present invention is determined by the scope of the claims, and is not limited by the following individual embodiments.

  First, in order to allow a person skilled in the art to better understand a programmable logic controller (PLC, which may be simply referred to as a programmable controller), the configuration and operation of a general PLC will be described.

  FIG. 1 is a conceptual diagram showing a configuration example of a programmable logic controller system according to an embodiment of the present invention. As shown in FIG. 1, this system includes a program creation support apparatus 1 for editing a user program such as a ladder program, and a PLC (programmable) for comprehensively controlling various control apparatuses installed in a factory or the like. -Logic controller 2). The PLC 2 includes a basic unit 3 having a built-in CPU and one or more expansion units 4. One or a plurality of expansion units 4 can be attached to and detached from the basic unit 3. The basic unit 3 may be called a CPU unit.

  The basic unit 3 includes a display unit 5 and an operation unit 6. The display unit 5 can display the operation status of each expansion unit 4 attached to the basic unit 3, and the display content of the display unit 5 can be switched by operating the operation unit 6. The display unit 5 normally displays a current value (device value) of a device in the PLC 2 and error information generated in the PLC 2. The device is a name indicating an area on a memory provided for storing a device value, and may be called a device memory. The device value is information indicating an input state from the input device, an output state to the output device, and states of an internal relay (auxiliary relay), a timer, a counter, a data memory, and the like set on the user program.

  The extension unit 4 is prepared for extending the function of the PLC 2 and is attached to the basic unit 3 from the side. The first extension unit 4 is directly attached to the basic unit 3 from the side. The second and subsequent expansion units 4 are attached in series from the side with respect to the expansion units 4 that are already attached. For example, the right side surface of the basic unit 3 and the left side surface of the expansion unit 4 are connection surfaces. Similarly, since the shape and the like of the right side surface of the first extension unit 4 are substantially the same as the right side surface of the basic unit 3, the left side of the second extension unit 4 is placed on the right side surface of the first extension unit 4. The faces are connected. Such a connection method may be called a daisy chain method or a daisy chain method. Each connection surface is provided with a connector, and a bus for performing communication and power supply is also connected through the connector. In this way, when the basic unit 3 and the plurality of expansion units 4 are attached in series, each expansion unit 4 is connected to the basic unit 3 via the wiring (eg, bus) provided in each expansion unit 4. To be communicable with each other. Each expansion unit 4 is connected to a controlled device 16 (FIG. 4) corresponding to the function of the expansion unit 4, whereby each controlled device 16 is connected to the basic unit 3 via the expansion unit 4. . The controlled device 16 includes an input device such as a sensor and an output device such as an actuator.

  The program creation support device 1 is, for example, a portable so-called notebook type or tablet type personal computer, and includes a display unit 7 and an operation unit 8. A ladder program which is an example of a user program for controlling the PLC 2 is created using the program creation support apparatus 1, and the created ladder program is converted into a mnemonic code in the program creation support apparatus 1. Then, the program creation support apparatus 1 is connected to the basic unit 3 of the PLC 2 via a communication cable 9 such as a USB (Universal Serial Bus), and the ladder program converted into the mnemonic code is transferred from the program creation support apparatus 1 to the basic unit 3. The ladder program is converted into a machine code in the basic unit 3 and stored in a memory provided in the basic unit 3.

  Although not shown in FIG. 1, the operation unit 8 of the program creation support apparatus 1 may include a pointing device such as a mouse connected to the program creation support apparatus 1. The program creation support device 1 may be configured to be detachably connected to the basic unit 3 of the PLC 2 via a communication cable 9 other than the USB.

  FIG. 2 is a diagram illustrating an example of a ladder diagram 17 displayed on the display unit 7 of the program creation support apparatus 1 when creating a ladder program. As shown in FIG. 2, the ladder program for controlling the PLC 2 appropriately arranges virtual device symbols 19 in a plurality of cells 18 displayed in a matrix on the display unit 7 of the program creation support apparatus 1. It is created by constructing a ladder diagram 17 representing a visual relay circuit.

  In the ladder diagram 17, for example, cells 18 of 10 columns × N rows (N is an arbitrary natural number) are arranged. A visual relay circuit can be created by appropriately arranging the virtual device symbols 19 in time series in the cells 18 of each row from the left side to the right side shown in FIG. The created relay circuit may be a serial relay circuit represented by one row, or a parallel relay created by coupling relay circuits represented in parallel in a plurality of rows to each other. It may be a circuit.

  The relay circuit shown in FIG. 2 includes three virtual devices (hereinafter referred to as “input devices”) 19a, 19b, and 19c that are turned on / off based on an input signal from the input device, and the operation of the output device. And a symbol 19d of a virtual device (hereinafter referred to as an “output device”) that is turned on / off to control the device.

  The characters (“R0001”, “R0002”, and “R0003”) displayed above the symbols 19a, 19b, and 19c of each input device represent the device name (address name) 21 of the input device. The characters (“flag 1”, “flag 2”, and “flag 3”) displayed below the symbols 19a, 19b, and 19c of each input device represent a device comment 22 associated with the input device. Yes. A character (“origin return”) displayed above the symbol 19d of the output device is a label 23 composed of a character string representing the function of the output device.

  In the example shown in FIG. 2, two input device symbols 19a and 19b respectively corresponding to device names “R0001” and “R0002” are coupled in series to form an AND circuit. In addition, an OR circuit is configured by parallelly connecting the input device symbol 19c corresponding to the device name “R0003” to the AND circuit including the symbols 19a and 19b of these two input devices. Yes. That is, in this relay circuit, the output device corresponding to the symbol 19d is turned on only when both of the input devices corresponding to the two symbols 19a and 19b are turned on or when the input device corresponding to the symbol 19c is turned on. It has come to be.

  FIG. 3 is a block diagram for explaining the electrical configuration of the program creation support apparatus 1 of FIG. As shown in FIG. 3, the program creation support apparatus 1 includes a CPU 24, a display unit 7, an operation unit 8, a storage device 25, and a communication unit 26. The display unit 7, the operation unit 8, the storage device 25, and the communication unit 26 are electrically connected to the CPU 24, respectively. The storage device 25 includes at least a RAM, and includes a ladder program storage unit 25a and an editing software storage unit 25b.

  The user causes the CPU 24 to execute editing software stored in the editing software storage unit 25 b and edits the ladder program through the operation unit 8. Here, the ladder program editing includes creation and modification of the ladder program. The ladder program created using the editing software is stored in the ladder program storage unit 25a. Further, the user can read out the ladder program stored in the ladder program storage unit 25a as needed, and change the ladder program using editing software. The communication unit 26 is for connecting the program creation support apparatus 1 to the basic unit 3 through the communication cable 9 so as to be communicable.

  FIG. 4 is a block diagram for explaining the electrical configuration of the PLC 2. As shown in FIG. 4, the basic unit 3 includes a CPU 10, a display unit 5, an operation unit 6, a storage device 12, and a communication unit 14. The display unit 5, the operation unit 6, the storage device 12, and the communication unit 14 are each electrically connected to the CPU 10. The storage device 12 may include a RAM, a ROM, a memory card, and the like, and stores a ladder program and the like. In the storage device 12, the ladder program and user data input from the program creation support device 1 are overwritten and stored. The storage device 12 also stores a control program for the basic unit.

  FIG. 5 is a schematic diagram showing a scan time configuration in the basic unit 3 of the programmable controller according to the embodiment of the present invention. As shown in FIG. 5, one scan time T is composed of inter-unit communication 201 for executing input / output refresh, program execution 202, and END processing 204. In the inter-unit communication 201, the basic unit 3 transmits output data obtained by executing the ladder program from the storage device 12 in the basic unit 3 to an external device and the like, and also receives input data including received data as the basic unit. 3 is stored in the storage device 12. For example, the device value stored in the device of the basic unit 3 is reflected in the device of the expansion unit 4 by refresh. Similarly, the device value stored in the device of the expansion unit 4 is reflected in the device of the basic unit 3 by refresh. Note that a mechanism for updating device values between units at a timing other than refresh may be employed. However, the device of the basic unit 3 is rewritten as needed by the basic unit 3, and similarly, the device of the expansion unit 4 is rewritten as needed by the expansion unit 4. That is, the device of the basic unit 3 can be accessed at any time by a device inside the basic unit 3, and similarly, the device of the expansion unit 4 can be accessed at any time by a device inside the expansion unit 4. The basic unit 3 and the expansion unit 4 synchronize by updating the device values at the refresh timing basically. In the program execution 202, the basic unit 3 executes (calculates) the program using the updated input data. The basic unit 3 computes data by executing a program. The END processing means general processing related to peripheral services such as data communication with an external device such as a display (not shown) connected to the program creation support apparatus 1 or the basic unit 3, and system error checking. . The END process is sometimes called a peripheral process.

  As described above, the program creation support apparatus 1 creates a ladder program according to the user's operation, and transfers the created ladder program to the PLC 2. The PLC 2 executes the input / output refresh, the execution of the ladder program, and the END process as one cycle (one scan), and periodically and cyclically executes this cycle. Thus, various output devices (motors, etc.) are controlled based on timing signals from various input devices (sensors, etc.). Therefore, the PLC 2 moves completely different from a general-purpose personal computer (PC).

<Inter-unit synchronization>
Inter-unit synchronization is a process of synchronizing the control cycle of internal processing of the basic unit 3 and the control cycle of internal processing of the expansion unit 4. Each of the basic unit 3 and the expansion unit 4 has a timer, and determines the start timing of internal processing according to the timer value. Since the basic unit 3 and the expansion unit 4 have timers having the same cycle, the control cycles of both are synchronized. There are a method of synchronizing the control cycle of the expansion unit 4 with reference to the control cycle of the basic unit 3 and a method of synchronizing the control cycle of the basic unit 3 with reference to the control cycle of the expansion unit 4. In any case, the expansion unit 4 executes internal processing according to the control cycle of the expansion unit 4. That is, the start timing of the internal processing coincides with the start timing of the control cycle of the expansion unit 4. The synchronization process may be executed during a specific period within the scan time of the ladder program that is the user program, or may be executed by interrupting the ladder program. Here, for convenience of explanation, it is assumed that the synchronization between units is executed by interruption with a fixed period. An interrupt module for executing an interrupt may be provided in the basic unit 3. For example, as shown in FIG. 6A, if the scan time is 5 milliseconds, the synchronization period of the inter-unit synchronization may be set to 200 microseconds (us). In this case, 25 inter-unit synchronization is executed within one scan time. Note that the scan is controlled by the scan module, and in parallel with this, the inter-unit synchronization is executed by the synchronization module. Therefore, inter-unit synchronization is performed at a constant cycle in any of the refresh period (inter-unit communication 201), the ladder program execution period (program execution 202), and the END process execution period (END process 204). Executed.

  The internal processing described above is processing executed by an internal function. The expansion unit 4 includes an interface, and is connected to the controlled device 16 that is an external device via the interface. The expansion unit 4 performs an operation on data acquired from the external device to obtain an input device value and stores it in the input device. Further, the expansion unit 4 performs an operation on the device value of the output device to obtain an output value, and outputs it to an external device. Internal processing includes these arithmetic processes. The arithmetic process is a concept that includes not only a calculation process based on a mathematical expression but also a process of acquiring a value from a table.

<Batch refresh and synchronous refresh>
As shown in FIG. 5, the input / output refresh is executed only once at one scan time T (this will be referred to as batch refresh). However, some data may not be sufficient if only one refresh is performed in one scan time. Such data can be read / written by allocating to the buffer memory without allocating to the device and performing direct communication with the buffer memory. However, in this case, an instruction for executing direct communication must be described in the ladder program. For data that needs to be updated at a much shorter cycle (eg, 200 us) with respect to the scan time (eg, 5 ms), data update instructions must be described in a number of locations in the ladder program. There was a face to put on. In addition, there are problems as described in the column “Problems to be Solved by the Invention”.

  By the way, as described above, the inter-unit synchronization (inter-unit synchronization program) may be set to be repeatedly executed with a very short synchronization cycle. Therefore, as shown in FIG. 6B, if data is refreshed at the time of synchronization between units, data that requires real-time property can be maintained in a fresh state (this is called synchronous refresh). ). However, if synchronous refresh is executed for all devices that have been subject to batch refresh, the time taken for the ladder program in the flat field to be interrupted by the synchronous refresh accompanying the inter-unit synchronization becomes longer (in other words, Therefore, the amount of description of the inter-unit synchronization program executed with the synchronization refreshing is limited), which causes inconvenience when the basic unit 3 controls the expansion unit 4. This is because the basic unit 3 needs to generate an interrupt to the ladder program at the timing of inter-unit synchronization and execute synchronous refresh. It should be noted that the inter-unit refresh has a fixed period in any of the refresh period (inter-unit communication 201), the ladder program execution period (program execution 202), and the END process execution period (END process 204). It is executed by interruption. If a large number of expansion units 4 are connected to the basic unit 3, the number of devices to be refreshed increases in proportion to the number of connected units, so the interruption time also increases.

  Therefore, if it is possible to select whether a plurality of devices are to be collectively refreshed or synchronously refreshed, the time during which the ladder program is interrupted can be reduced. That is, if the update timing of data to be shared between the basic unit 3 and the expansion unit 4 can be selected, the user can select the update timing for each device so that it falls within the interruption time within the range shared by the user. This will improve usability. Note that some devices may be set not only as a batch refresh target but also as a synchronous refresh target.

  Note that a buffer memory that has been updated by direct communication in the ladder program, which is a user program, may also be subject to synchronous refresh. That is, it is not necessary to write a direct communication code in the ladder program for the buffer memory selected for synchronous refresh. That is, the buffer memory selected as the target of the synchronous refresh can be handled in the ladder program in the same manner as the device that is the target of the batch refresh. Usability will also improve in that it makes it easier to create ladder programs. Similarly, a device that has been updated by direct communication in the ladder program can be selected as a target for synchronous refresh.

<Functions of basic unit>
FIG. 7 is a block diagram illustrating an example of functions of the basic unit 3. The CPU 10 implements various functions by executing the control program 77. Note that some of the functions may be implemented by a logic circuit such as an ASIC.

  The basic unit control unit 70 is a function for comprehensively controlling each unit of the basic unit 3. For example, the basic unit control unit 70 executes scan management, interrupt management for inter-unit refresh, and the like. The basic unit control unit 70 is a function realized by the CPU 10 executing the control program 77. The program execution unit 71 is a function that mainly executes a ladder program 78 and the like. If the program execution unit 71 is implemented by an ASIC or the like, it is easy to realize high-speed control. The device control unit 72 is a function that controls reading and writing with respect to the device 80. For example, while the synchronous refresh is being executed, the device control unit 72 executes an exclusion / arbitration process (prohibition process) so that the contents of the device 80 are not rewritten or read by other means. . The device control unit 72 may prohibit interruption by means other than the second update unit 76 while the second update unit 76 is executing synchronous refresh. Note that an interrupt that has already occurred when synchronous refresh is started is not prohibited and is executed as it is.

  The inter-unit synchronization unit 73 executes the inter-unit synchronization program according to a predetermined synchronization cycle. The inter-unit synchronization program is a program that is executed by interrupting the flat ladder program, and is basically executed in a shorter cycle than the flat ladder program. The inter-unit synchronization unit 73 performs timer synchronization that synchronizes the timer value of the extension unit timer 119 (FIG. 8) and the timer value of the basic unit timer 88. The function of executing timer synchronization may be provided as a timer synchronization unit independently from the inter-unit synchronization unit 73. The same applies to the expansion unit 4. The period of timer synchronization is, for example, 1000 microseconds. Thereby, the control cycle of the extension unit 4 is synchronized with the control cycle of the basic unit 3. In general, when inter-unit synchronization is not executed, the control cycle of the basic unit 3 and the control cycle of the expansion unit 4 may gradually shift, and the basic unit 3 may not be able to control the expansion unit 4 with high accuracy. Therefore, by executing the inter-unit synchronization program, the control cycle of the basic unit 3 and the control cycle of the expansion unit 4 coincide with each other in phase level. The basic unit timer 88 is a timer or counter that counts clocks and measures time. The inter-unit synchronization unit 73 executes the inter-unit synchronization program according to the synchronization cycle with the timer value of the basic unit timer 88 as a reference. The inter-unit synchronization unit 73 transmits a synchronization signal for notifying the expansion unit 4 of the synchronization timing via the expansion bus connected to the communication unit 14. It is assumed that the communication unit 14 includes a communication function for performing communication using the expansion bus and a communication function for communicating with the program creation support apparatus 1.

  The update unit 74 is a function of updating the data stored in the device by the basic unit 3 and the data stored in the device by the expansion unit 4 so that they match each other. For example, data transferred from the basic unit 3 to the expansion unit 4 is stored in the output device. Data transferred from the expansion unit 4 to the basic unit 3 is stored in the input device. In general, a plurality of output devices are updated together by output refresh, and a plurality of input devices are updated together by input refresh. Input refresh and output refresh exist in both batch refresh and synchronous refresh. The first update unit 75 is a function for executing batch refresh. That is, the first update unit 75 matches the data held by the extension unit 4 with the data held by the basic unit 3 within the refresh period for each scan. The second update unit 76 has a function of executing synchronous refresh. In other words, the second update unit 76 uses the inter-unit synchronization unit 73 within the period of processing executed at regular intervals during scanning based on the timer value of the basic unit timer 88 synchronized with the timer value of the extension unit timer 119. The data held by 4 and the data held by the basic unit 3 are matched. Note that the second update unit 76 can interrupt and execute synchronous refresh during any period within the scan time.

  The device of the expansion unit 4 described in the ladder program 78 that is a user program can be set as at least one of the update target by the first update unit 75 and the update target by the second update unit 76. Composed. The basic unit control unit 70 may function as a selection unit that selects data / devices to be updated by the first update unit 75 and data / devices to be updated by the second update unit 76. That is, the basic unit control unit 70 may function as a selection unit that selects at least one of the first update unit 75 and the second update unit 76 as an update unit that updates a device. For example, the basic unit control unit 70 selects whether each device is to be subjected to batch refresh or synchronous refresh according to an instruction from the operation unit 6 and holds the selection result in the setting data 79. That is, the setting data 79 includes update target designation information that designates a device or buffer memory that is a target of synchronous refresh. It should be noted that devices and buffer memories that are targets of batch refresh may also be included in the setting data 79 as update target designation information. Note that such setting data 79 may be created in the program creation support apparatus 1 and transferred to the basic unit 3 together with the ladder program 78. Only the synchronous refresh target may be selectable, and the batch refresh target may be disabled. Further, only the batch refresh target may be selectable, and the synchronous refresh target may be disabled.

  A control program 77 is stored in the storage device 12. The control program 77 includes a scan program for executing a scan, an inter-unit synchronization program for executing inter-unit synchronization, an interrupt module for executing an interrupt, and the like. The inter-unit synchronization program is executed based on the timer value of the basic unit timer 88 synchronized with the timer value of the extension unit timer 119 (FIG. 8) by inter-unit synchronization processing. The storage device 12 also functions as a program storage unit. Scanning means that a user program and END processing are repeatedly executed within a scan time. The END processing includes batch refresh and peripheral processing. The scan time T is a time required for scanning, and there are cases where the scan time T is set to be constant and cases where the scan time T is variable.

  The scan control program and the synchronization program may also be described in a ladder language. A ladder program 78, which is a kind of user program, is written in a ladder language, and is a user program for controlling the internal functions of the basic unit 3 and the internal functions of the expansion unit 4. The setting data 79 includes parameters necessary for controlling the connection order and internal functions of the basic unit 3 and the expansion unit 4. The device 80 is a storage area that functions, for example, data assigned to the internal function of the expansion unit 4, and is sometimes called a device memory. Here, the device 80 is described as a set of a plurality of devices. The first device 81 is a device selected as a batch refresh target. The second device 82 is a device selected as a target for synchronous refresh. The number of first devices 81 is generally greater than the number of second devices 82, but this may be reversed. The third device 83 is an optional device memory allocated to the buffer memory UG of the expansion unit 4. For the third device 83, the first update unit 75 may perform batch refresh, or the second update unit 76 may perform synchronous refresh. Information indicating the allocation relationship between the third device 83 and the buffer memory UG and which refresh is applied is also held in the setting data 79. A plurality of third devices 83 may be provided. Depending on which refresh is applied, the update unit 74 treats the third device 83 as the first device 81 or the second device 82.

<Function of expansion unit>
FIG. 8 is a block diagram showing an example of the function of the expansion unit. The CPU 110 implements various functions by executing the system program 117 stored in the storage device 111. The extension unit control unit 113 has a function of controlling the controlled device 16 in accordance with an instruction from the basic unit 3 written in the first device 118 or the second device 120. The storage device 111 includes a ROM, a RAM, and the like, and a part of the memory in the storage device 111 may be a rewritable nonvolatile memory. The CPU 110 has an interface 123 for communicating with the controlled device 16. The inter-unit synchronization unit 114 synchronizes the control cycle of internal processing in the expansion unit 4 with the control cycle of the basic unit 3 in accordance with the synchronization signal transmitted from the basic unit 3 via the expansion bus and communication unit 112. The expansion unit timer 119 is a timer or counter that counts clocks and measures time. The inter-unit synchronization unit 114 may operate so that the timer value of the extension unit timer 119 matches the timer value of the basic unit timer 88. The inter-unit synchronization unit 114 may include a postponement unit 115 that delays (postpones) the start of internal processing executed by the expansion unit 4 in accordance with the delay time of the update processing in the second update unit 76. If the expansion unit 4 starts internal processing even though the update processing has not been completed, the latest device value is not reflected in the internal processing. Therefore, by delaying the start timing of the internal process until the update process is completed, the internal process can use the latest device value.

  In the storage device 111, storage areas such as a device for storing a device value and a buffer to be subjected to direct communication are secured. The first device 118 is a device that is collectively refreshed. As the device value of the first device 118, a device value that matches the first device 81 of the basic unit 3 is stored. The second device 120 is a device that is synchronously refreshed. As the device value of the second device 120, a device value that matches the second device 82 of the basic unit 3 is stored. The first device 81 and the second device 120 may be realized by a plurality of buffers. The first buffer 121 is a buffer for exchanging device values with the basic unit 3. The second buffer 122 is a buffer for the expansion unit control unit 113 to input and output device values. The buffer update unit 116 is an optional unit and is necessary when one device is realized by a plurality of buffers. When the second device 120 is an output device, the buffer update unit 116 stores the device value of the second device 82 of the basic unit 3 in the first buffer 121, and further stores the device value stored in the first buffer 121. 2 stored in the buffer 122. When the second device 120 is an input device, the buffer update unit 116 stores the device value as a result of the internal processing in the second buffer 122, and stores the device value stored in the second buffer 122 in the first buffer 121. The device value stored in the first buffer 121 is transferred to the second device 82 of the basic unit 3. As described above, the first buffer 121 is referred to during synchronous refresh, and the second buffer 121 is referred to by internal processing of the expansion unit 4. By adopting such a double buffer configuration, the device value of the second device 120 is determined and then used for refresh and internal processing. That is, it is difficult for the device value to be rewritten during the refresh or the device value is rewritten during the internal processing. The device value includes a set of a plurality of device values that need to be updated at the same timing (simultaneity), and a set of a plurality of device values in which the update order is determined (order). There is also a set of a plurality of device values required to have substantially the same transmission delay time between the basic unit 3 and the expansion unit 4 (constancy of transmission delay time). For example, the denominator is stored in the first device and the numerator is stored in the second device, and the control value may be determined by the denominator and the numerator. In such a control value, if the numerator is rewritten by synchronous refresh after the expansion unit control unit 113 acquires the denominator, the denominator-numerator pair is broken (so-called crying phenomenon), and the control value is abnormal. Become. Therefore, the double buffer configuration is effective for devices that require simultaneity, such as a denominator and numerator pair. The buffer update unit 116 performs buffer update from the first buffer 121 to the second buffer 122 or from the second buffer 122 to the first buffer 121 after a plurality of device values for which simultaneity is required are obtained. , It will be possible to suppress the crying of multiple device values. The double buffer configuration is also useful for ensuring the order and the constant transmission delay time. The buffer memory UG is a memory that is normally accessed by direct communication. In the present embodiment, one or more of the plurality of buffer memories UG can be allocated to the third device 83. Since the buffer memory UG allocated to the third device 83 is refreshed collectively or synchronously, it is not necessary to update by direct communication.

<Functions of the program creation support device>
FIG. 9 shows functions realized by the CPU 24 of the program creation support apparatus 1 executing the editing software 86. The editing software 86 is a program used by a user to edit a ladder program 78, setting data 79, and the like.

  The CPU 24 functions as various means by executing the editing software 86, but here, representative ones will be described. The ladder program creation unit 87 displays a user interface for creating and editing the ladder program 78 on the display unit 7, creates the ladder program 78 in accordance with instructions input from the operation unit 8, and writes the ladder program 78 in the storage device 25. The setting data creation unit 84 displays a user interface for creating the setting data 79 on the display unit 7, creates the setting data 79 in accordance with an instruction input from the operation unit 8, and writes it in the storage device 25. For example, the setting data creation unit 84 displays a list in which the devices of the plurality of expansion units 4 connected to the basic unit 3 are listed on the display unit 7 and is set as a target of batch refresh for each device or a target of synchronous refresh Select what will be. When the number of devices per one expansion unit 4 is small, the setting data creation unit 84 may select whether to perform batch refresh or synchronous refresh for each expansion unit 4 as a unit. Good. For example, the setting data creation unit 84 displays a list listing a plurality of extension units 4 connected to the basic unit 3 on the display unit 7, and sets each of the extension units 4 as a batch refresh target or a synchronous refresh target. Select what will be. As described above, the setting data 79 may include information indicating whether each device is subject to batch refresh or synchronous refresh. The project transfer unit 85 collects the ladder program 78 and setting data 79 as project data, and transfers them to the basic unit 3 via the communication unit 26. The communication unit 26 has a USB interface and a LAN interface for communicating with the basic unit 3.

<Flowchart>
FIG. 10 is a flowchart showing processing executed by the basic unit 3. When the basic unit 3 is switched from the maintenance mode (programming mode) to the run mode, the CPU 10 executes the processing according to this flowchart according to the control program 77. In this embodiment, the inter-unit synchronization process is executed in the run mode, but the inter-unit synchronization process may be executed in the maintenance mode.

  In S1, the CPU 10 (first updating unit 75) executes batch refresh. For example, the first updating unit 75 performs batch refresh on a device selected as a batch refresh target by the setting data 79 among a plurality of devices.

  In S2, the CPU 10 (program execution unit 71) starts a ladder program 78 which is a user program. Thereafter, the program execution unit 71 executes the ladder program 78 in parallel with the control program 77 until the ladder program 78 ends.

  In S3, the CPU 10 (inter-unit synchronization unit 73) determines whether an event that triggers inter-unit synchronization has occurred. This event is generated every predetermined period by an interrupt module (inter-unit synchronization unit 73 or basic unit control unit 70). For example, the inter-unit synchronization unit 73 may perform inter-unit synchronization each time the timer value of the basic unit timer 88 increases by a predetermined value. The inter-unit synchronization notification is also generated in the extension unit 4 through a signal line or the like. If an inter-unit synchronization event occurs, the process proceeds to S4. If no inter-unit synchronization event has occurred, the ladder program 78 is continued, and the process proceeds to S8.

  In S <b> 4, the CPU 10 (inter-unit synchronization unit 73, program execution unit 71) interrupts the ladder program by an interrupt for synchronous refresh that occurs at regular intervals based on the timer value of the basic unit timer 88. For example, the inter-unit synchronization unit 73 instructs the program execution unit 71 to interrupt the ladder program based on the timer value of the basic unit timer 88. As a result, the program execution unit 71 interrupts the ladder program. Note that the interrupt itself may be recognized as an interruption instruction.

  In S5, the CPU 10 (second update unit 76) executes synchronous refresh. The second update unit 76 performs batch refresh on the devices that are selected as the target of synchronous refresh by the setting data 79 among a plurality of devices.

  In S6, the CPU 10 (inter-unit synchronization unit 73) executes the inter-unit synchronization program. The inter-unit synchronization unit 73 of the basic unit 3 and the inter-unit synchronization unit 114 of the expansion unit 4 communicate through the expansion bus, and synchronize their control periods by matching the timer values with each other.

  In S7, the CPU 10 (inter-unit synchronization unit 73, program execution unit 71) resumes the ladder program 78. For example, the inter-unit synchronization unit 73 instructs the program execution unit 71 to resume the ladder program. As a result, the program execution unit 71 resumes the ladder program.

  In S8, the CPU 10 (basic unit controller 70) determines whether or not the ladder program 78 has ended. If the ladder program 78 has not ended, the process returns to S3. If the ladder program 78 is completed, the process proceeds to S9.

  In S9, the CPU 10 (basic unit controller 70) executes the END process described above. This completes one can time. Thereafter, the process returns to S1 to start the next scan. Thereafter, until the mode is switched from the run mode to the maintenance mode, the processing according to this flowchart is repeatedly executed according to the scan T as shown in FIG.

  Here, it has been described that the inter-unit synchronization is executed during the execution of the ladder program 78, but the inter-unit synchronization is executed in both the batch refresh (S1) and the END process (S9). That is, S1 and S9 include steps corresponding to S3 to S7. Here, it is assumed that the ladder program described in S4 and S7 can be read as batch refresh and END processing.

  FIG. 11 is a flowchart showing processing executed by the expansion unit 4. Here, the batch refresh is omitted. The CPU 110 executes the following processing according to the system program 117.

  In S11, the CPU 110 (inter-unit synchronization unit 114) waits for notification of inter-unit synchronization. When the notification of inter-unit synchronization is received through the expansion bus, the process proceeds to S12.

  In S12, the CPU 110 (inter-unit synchronization unit 114, buffer update unit 116) executes synchronous refresh. The buffer update unit 116 transfers the device value stored in the input device of the second device 120 to the basic unit 3 and stores the device value received from the basic unit 3 in the output device. When the double buffer configuration is adopted, the buffer update unit 116 updates the device value between the first buffer 121 and the second buffer. Regarding the output device, the device value received from the basic unit 3 is stored in the first buffer 121, and then copied from the first buffer 121 to the second buffer 122. Internal processing executed by the extension unit control unit 113 refers to the device value stored in the second buffer 122. Regarding the input device, the device value stored in the second buffer 122 is copied to the first buffer 121 by internal processing executed by the expansion unit control unit 113, and then transferred from the first buffer 121 to the basic unit 3.

  In S13, the CPU 110 (extension unit control unit 113) reads the device value from the input device of the first device 118 and the second device 120, and executes internal processing according to the device value. The expansion unit control unit 113 stores the execution result of the internal processing in the output device (in particular, the second buffer 122 of the output device) of the first device 118 and the second device 120.

  By executing synchronous refresh at the timing of inter-unit synchronization in this way, communication programs (programs for the basic unit to communicate with the expansion unit) that are premised on batch refresh can also be used for devices that are subject to synchronous refresh. Applicable. In the prior art, when the latest device value is required at any timing for devices that were not subject to batch refresh, the device value is updated by direct communication within the flat ladder program (main ladder program). There was a need to do. However, this was a cumbersome programming task for the user. On the other hand, according to the present embodiment, devices that are not subject to batch refresh are also updated by synchronous refresh, so a code for direct communication is not required, and a communication program that assumes batch refresh is provided. It can also be used for synchronous refresh.

<Application of synchronous refresh to buffer memory>
Note that the PLC 2 has a storage area called a buffer memory UG separately from the device. The device is a storage area to be refreshed, and the buffer memory UG (sometimes referred to simply as a buffer) is not to be refreshed and is accessed by direct communication. Such a buffer memory UG may also be selected as a target for synchronous refresh. As a result, the buffer memory UG that requires a more complicated code than the device can be handled by the same code as the device by synchronous refresh. In particular, values stored in a plurality of buffer memories UG (referred to as buffer values) include a set of a plurality of buffer values that need to be updated at the same time, (simultaneity), and an update order. There is a set of multiple fixed buffer values (ordering). For example, the denominator is stored in the first buffer memory, and the numerator is stored in the second device, and the control value may be determined by this denominator and numerator. In such a control value, if the numerator is rewritten by synchronous refresh after the expansion unit control unit 113 acquires the denominator, the denominator / numerator pair is broken (crying apart), and the control value becomes abnormal. Therefore, buffer values that require simultaneity, such as denominator and numerator pairs, are updated while maintaining simultaneity and order in synchronous refresh. In addition, the synchronous refresh may be applied to the buffer memory UG that requires constant transmission delay time by assigning the third device 83. This will ensure the uniformity of the transmission delay time. Note that the buffer memory UG may also employ a double buffer configuration. Note that the buffer memory UG and the third device 83 to be subjected to synchronous refresh are treated in the same manner as the second device throughout the specification. That is, the description regarding the second device is applied to the buffer memory UG and the third device 83 as they are. In addition, when the buffer memory UG and the third device 83 are selected as a target for batch refresh, the description regarding the first device is applied to the buffer memory UG and the third device 83 as they are.

<Selection of devices subject to synchronous refresh>
As described above, the inter-unit synchronization may be executed at a cycle shorter than the refresh timing (for example, 50 us to 5 ms). This is to reduce variations in the responsiveness of the basic unit 3 and the expansion unit 4 (in other words, the responsiveness of the basic unit to the external input device or the responsiveness of the external output device to the basic unit). It is. In order to execute the synchronous refresh at the timing of executing the inter-unit synchronization, the synchronous refresh must be completed within the synchronization cycle of the inter-unit synchronization. Thus, the number of devices subject to synchronous refresh will need to be limited to some extent. For example, if all devices that have been subject to batch refresh are selected as subjects for synchronous refresh, the inter-unit synchronization cycle cannot be shortened, and variations in responsiveness between the basic unit 3 and the expansion unit 4 are reduced. It will be difficult to do. Therefore, the synchronous refresh target is selected in advance in consideration of the length of the synchronization cycle of inter-unit synchronization. This selection is executed by the program creation support apparatus 1 or through the operation unit 6 of the basic unit 3. Further, the synchronous refresh is realized by an interrupt program, and the synchronous refresh is executed for the selected device. This realizes stable inter-unit synchronization and synchronous refresh even if the scan time fluctuates, for example. In this case, the inter-unit synchronization can be executed anywhere within the scan time. For example, the inter-unit synchronization unit 73 and the second update unit 76 may perform inter-unit synchronization and synchronous refresh not only during the ladder program execution period but also during the batch refresh period. Inter-unit synchronization and synchronous refresh will be executed at regular intervals, and variations in responsiveness between the basic unit 3 and the expansion unit 4 will be reduced.

  The setting data creation unit 84 of the program creation support apparatus 1 selects a device or buffer memory UG that is a target of synchronous refresh, but may select an expansion unit 4 that is a target of synchronization between units in the first place. As a result, even when the number of extension units 4 that are subject to inter-unit synchronization is large and the amount of data that is subject to inter-unit synchronous refresh is large, the unit synchronization is realized while the unit synchronization is performed. (For example, 200 μs) can be shortened. As illustrated in FIG. 16, the setting data creation unit 84 displays a list 90 that lists a plurality of extension units 4 connected to the basic unit 3, and responds to an instruction input from the operation unit 8. It may be selected whether or not each of the plurality of expansion units 4 is to be subject to inter-unit synchronization. For example, a positioning unit (motion unit) that needs to reduce variations in responsiveness between the basic unit 3 and the extension unit 4 may be selected as a target for inter-unit synchronization. Since the LAN communication unit or the like is not required to be so real-time, it does not have to be selected as a target for inter-unit synchronization. Note that the setting data creation unit 84 may forcibly select the extension unit 4 that does not support inter-unit synchronization and exclude the unit from being subject to inter-unit synchronization, and may not give the user room for selection. For example, the setting data creation unit 84 may gray out such an extension unit and disable selection by the operation unit 8.

  For the extension unit selected as the target for inter-unit synchronization, the setting data creation unit 84 further determines whether refresh of a specific device such as an occupied device is subject to batch refresh or subject to synchronous refresh. A GUI for selection may be displayed on the display unit 7. The occupied device is a device allocated in advance for each expansion unit. For example, with respect to the expansion unit 4 having a large amount of communication with the basic unit 3, it is easy to divert the program code for batch refresh for synchronous refresh by making the occupied device the subject of synchronous refresh. . Note that the setting data creation unit 84 may intentionally select the occupied device of the extension unit 4 that needs to shorten the synchronization cycle between units as a target for synchronous refresh. Such a device does not perform synchronous refresh at the timing of inter-unit synchronization, so that the synchronization cycle can be shortened.

<Suppression of crying of multiple device values>
As described above, in order to correctly transmit the ratio determined by the numerator and the denominator, the numerator and the denominator must satisfy the simultaneity requirement and be refreshed between units. Although the double buffer configuration has already been described as a method for realizing this, other exclusive arbitration methods may be used.

  As described above, the internal processing of the expansion unit 4 refers to the values of a plurality of output devices. The internal processing of the expansion unit 4 stores a plurality of processing results in the input device value. Some output device values require simultaneity. Similarly, some input device values may require simultaneity.

  Therefore, as shown in FIG. 12, the extension unit 4 starts internal processing after waiting for the second update unit 76 of the basic unit 3 to complete the synchronous refresh for the device. That is, as shown in FIG. 12, the inter-unit synchronization unit 114 of the first expansion unit and the second expansion unit has a predetermined waiting time (called a refresh waiting time) when an interrupt for synchronous refresh occurs due to inter-unit synchronization. The expansion unit control unit 113 starts the internal processing after waiting for the elapse of time). During this waiting time, the second update unit 76 of the basic unit 3 executes synchronous refresh of the device and the buffer memory UG. As a result, during the period when the device value is synchronously refreshed, the internal processing of the expansion unit control unit 113 does not read or write the device value, and crying does not occur. As described above, the inter-unit synchronization unit 114 of the expansion unit 4 synchronizes the synchronous refresh and the internal processing, so that the access to the device by the synchronous refresh and the access to the device by the internal processing do not occur at the same time. Become. That is, the expansion unit control unit 113 is exclusively or arbitrated for access to the device during the waiting time. This exclusive / arbitration function may be built in the inter-unit synchronization unit 114 or may be built in the extension unit control unit 113. The exclusive / arbitration function (prohibition function) may include a timer or a counter that measures a predetermined waiting time from the start timing of the synchronization cycle.

  If synchronous refresh is not completed within a predetermined waiting time, or if no predetermined waiting time is provided in the first place, internal processing may be started before synchronous refresh is completed. In this case, the above-described double buffer configuration is effective. That is, synchronous refresh is performed on the first buffer 121, and access to the first buffer 121 by internal processing of the expansion unit 4 is exclusive or arbitrated. That is, an access that occurs after an access by synchronous refresh is kept waiting until the access by synchronous refresh is completed. Similarly, the internal processing of the expansion unit 4 accesses the second buffer 122, and access to the second buffer 122 by synchronous refresh is exclusive or arbitrated. That is, the access by the synchronous refresh that occurs after the access by the internal processing is waited until the access by the internal processing is completed. The device values of the first buffer 121 and the second buffer 122 are updated by the buffer update unit 116 at the inter-unit synchronization timing (synchronization cycle start timing). This suppresses crying of multiple device values. As described above, a double buffer configuration may also be adopted for the buffer memory UG.

<Device value propagation delay time>
It may be desirable to control the transmission delay time of the device value to a certain time. As described above, the inter-unit synchronization is executed in order to reduce variation in responsiveness between the basic unit 3 and the expansion unit 4. However, it may not be sufficient to synchronize the control cycle of the basic unit 3 and the control cycle of the expansion unit 4. That is, if the transmission delay time of the device value between the basic unit 3 and the expansion unit 4 becomes constant, the variation in responsiveness is further reduced. As described above, crying of a plurality of device values often occurs because the transmission delay times of these device values do not match. In particular, access to these device values by internal processing is likely to occur asynchronously.

  Thus, by synchronizing the execution timing of the synchronous refresh and the execution timing of the internal processing as described above, asynchronous access to the device is suppressed, and the variation in the transmission delay time is reduced. Note that the above-described double buffer configuration is also effective in reducing variations in transmission delay time. Since the access by the synchronous refresh for a certain device and the access by the internal processing of the extension unit 4 do not compete, the asynchronous access by the basic unit 3 and the internal processing does not occur. Therefore, the variation in the transmission delay time is reduced.

  FIG. 13 is a diagram for explaining the operation of the double buffer. Here, it is assumed that the basic unit 3 is connected with a first extension unit as an input unit and a second extension unit as an output unit. At the start of the synchronization cycle, X0 is stored as the device value in the first buffer 121 of the first extension unit, and X1 is stored in the second buffer 122. Similarly, Y0 is stored as a device value in the first buffer 121 of the second extension unit, and Y0 is also stored in the second buffer 122.

  When an interrupt for unit synchronization occurs, the buffer update unit 116 of the first expansion unit copies the device value of the second buffer 122 to the first buffer 121. Note that the second expansion unit, which is the output unit, does not have to execute copying between the buffers at this time. First, the second update unit 76 of the basic unit 3 executes the input refresh of the synchronous refresh. That is, the second update unit 76 reads the device value from the first buffer 121 of the first extension unit, and copies it to the second device assigned to the first extension unit.

  Next, the 2nd update part 76 performs output refresh among synchronous refreshes. That is, the second update unit 76 reads the device value from the first buffer 121 of the second extension unit and copies it to the second device 82 allocated to the second extension unit.

  When a predetermined time elapses from the timing at which the interrupt is generated, the inter-unit synchronization unit 73 of the basic unit 3 and the inter-unit synchronization unit 114 of the first extension unit and the second extension unit match each other's control periods at the phase level. When this synchronization processing is completed, or at the start of this synchronization processing, the extension unit control unit 113 of the first extension unit and the second extension unit starts internal processing. In FIG. 13, control is performed so that the internal processing is started at the start of the synchronization processing. The buffer update unit 116 of the second extension unit copies the device value of the first buffer 121 to the second buffer 122 at the start timing of internal processing.

  Thereafter, the extension unit control unit 113 of the first extension unit updates the device value of the second buffer 122 according to the result of the internal processing. The expansion unit control unit 113 of the second expansion unit refers to the device value in the second buffer 122 and executes internal processing according to the device value.

  It is also conceivable that input refresh is executed, then inter-unit synchronization (inter-unit synchronization program) and internal processing are executed, and finally output refresh is executed. In this case, if a device value is transmitted between the first extension unit and the second extension unit, two synchronization periods are required. That is, the device value is transmitted from the first extension unit to the basic unit 3 in the first synchronization cycle, and then the internal processing is executed, and the device value is transmitted from the basic unit 3 to the second extension unit. The second extension unit refers to the device value in the next synchronization cycle and executes internal processing. Therefore, two synchronization periods are required. On the other hand, as shown in FIG. 13, when the input refresh is executed, the output refresh is executed next, and the inter-unit synchronization and the internal processing are executed at the end, there is an advantage that only one synchronization cycle delay is required. That is, the device value is transmitted from the first extension unit to the basic unit 3 in the first synchronization cycle, and then the device value is transmitted from the basic unit 3 to the second extension unit, and the device value can be referred to by internal processing. It becomes. Therefore, the first extension unit and the second extension unit can transmit and receive device values within one synchronization period. However, the internal processing needs to be executed after a predetermined waiting time elapses from the timing when the interrupt occurs.

  As an example in which the first extension unit and the second extension unit need to communicate with each other, a PLC 2 including a positioning unit and an input unit that gives a trigger to the positioning unit can be considered. More specifically, when a workpiece (inspection object) is detected by the sensor of the input unit, a device value indicating the detection is transmitted to the basic unit 3 and further transmitted to the positioning unit. The positioning unit activates a motor or the like based on this device value and executes positioning.

  In order to reduce the delay in communication of device values between a plurality of extension units, it may be advantageous to execute inter-unit synchronization after executing input refresh and output refresh. In particular, in the communication of device values between expansion units that involve units that require high-speed operation such as positioning units, the order of such processing is suitable.

<Refresh bit device and word device>
Some devices and buffer memories store a 1-bit device value, and others store a one-word device value. In other words, there are a mixture of bit type and word type to be refreshed. Even in such a case, the order described above may be necessary. As a method of satisfying the order requirement, a flag is set when a device value to be transmitted is stored in the device. In the transmission path, the device value is transmitted first, and then the flag is transmitted. When the receiving side recognizes that the flag is set, it reads the device value from the device. As a result, the receiving side can read the device value with a small delay time. The flag can be realized by a bit type device. That is, it may be required to transfer the word data (word device value) to be transmitted stored in the word device first and transfer the device value of the bit device storing the flag later. This is because if the flag is transferred first, the old word device value may be read out.

  Interrupts with higher priority than inter-unit synchronization may occur during synchronous refresh execution. In this case, regarding the input device, the word device is updated first, and then the bit device is updated. Similarly, output devices are required to be ordered. In this case, the bit device is transferred first and the word device is transferred later. Note that the basic unit control unit 70 of the basic unit 3 and the expansion unit control unit 113 of the expansion unit 4 may prohibit interruption by other means during the period when the synchronous refresh is being executed.

  Note that a double buffer configuration may be applied to a device to be a flag. In this case, the update order of the bit device and the word device described above is reversed. Although the bit device and the word device have been described here, the present embodiment can be applied even when the word device is used as the bit device. That is, the present embodiment can be used to maintain the update order between word devices even when only word devices exist.

<Postponement of internal processing>
The inter-unit synchronization unit 114 of the extension unit 4 may include a postponement unit 115. If the internal processing is started even though the synchronous refresh has not been completed, the above-mentioned tearing problem may occur. Therefore, when the inter-unit synchronization unit 114 detects that the synchronous refresh has not been completed within a predetermined waiting time, the inter-unit synchronization unit 114 may postpone the generation timing of the internal processing. The postponement time may be determined dynamically or may be determined statically. In the former, when the inter-unit synchronization unit 114 detects the completion of the synchronous refresh, the internal process is started. In the latter, the inter-unit synchronization unit 114 waits for the elapse of a predetermined postponement time to start internal processing.

  Synchronous refresh delays may occur due to retries associated with flow control. In such a case, the postponing unit 115 is useful, but the double buffer configuration described above may be employed instead. By adopting the double buffer configuration, the problem of simultaneity, the problem of order, and the problem of variation in transmission delay time are alleviated.

<Synchronizing the batch refresh and scan time with the control cycle of the expansion unit>
In the above-described embodiment, the control cycle of the basic unit 3 and the control cycle of the expansion unit 4 are matched by inter-unit synchronization. However, the batch refresh and the scan time may be performed asynchronously. However, an interrupt is required to execute inter-unit synchronization. If the batch refresh and the scan time can be synchronized with the control cycle of the expansion unit 4, no interrupt will be required.

  FIG. 14 is a flowchart showing a process of synchronizing batch refresh and scan time with the control cycle of the extension unit. This process is executed by the CPU 10 of the basic unit 3.

  In S15, the CPU 10 (first updating unit 75) executes batch input refresh. The batch input refresh is the batch refresh described above for the input device. In S <b> 16, the CPU 10 (program execution unit 71) executes the ladder program 78. In S17, the CPU 10 (first updating unit 75) executes batch output refresh. The batch output refresh is the batch refresh described above for the output device. In S18, the CPU 10 (basic unit controller 70) executes an END process. The END processing is also called peripheral processing, and includes data acquisition from an external interface and data collection by logging processing. The END process is also executed in conjunction with the synchronization cycle. In S19, the CPU 10 (inter-unit synchronization unit 73) determines whether it is time to execute inter-unit synchronization. When the inter-unit synchronization timing arrives, the inter-unit synchronization unit 73 performs a synchronization process with the inter-unit synchronization unit 114 of the extension unit 4 designated as the target for inter-unit synchronization, and matches the control cycles with each other. Thereafter, the process returns to S15. In other words, due to the inter-unit synchronization, the control cycle of the basic unit 3 and the expansion unit 4 coincide, and the control cycle of the expansion unit 4 and the scan timing are also synchronized.

  Thus, since the scan of the ladder program 78 is executed with the synchronization between units as a trigger, the scan time is synchronized with the control cycle of the expansion unit 4. As can be seen from the flowchart shown in FIG. 14, the synchronization period and the scan time are substantially the same length.

  FIG. 15 is a flowchart showing another process for synchronizing the batch refresh and the scan time with the control cycle of the extension unit. This process is executed by the CPU 10 of the basic unit 3. Compared to FIG. 14, the point that synchronous refresh is also executed is particularly different.

  In S20, the CPU 10 (second update unit 76) executes synchronous refresh. In S21, the CPU 10 (first update unit 75) executes batch refresh. Batch refresh includes batch input refresh and batch output refresh. In S <b> 22, the CPU 10 (program execution unit 71) executes the ladder program 78. In S23, the CPU 10 (basic unit controller 70) executes an END process. In S24, the CPU 10 (inter-unit synchronization unit 73) determines whether it is time to execute inter-unit synchronization based on the timer value of the basic unit timer 88. When the inter-unit synchronization timing arrives, the inter-unit synchronization unit 73 performs a synchronization process with the inter-unit synchronization unit 114 of the extension unit 4 designated as the target for inter-unit synchronization, and matches the control cycles with each other. Thereafter, the process returns to S20. In this way, synchronous refresh and batch refresh may be executed in conjunction with inter-unit synchronization. This makes it possible to synchronize batch refresh and scan time with the control period of the expansion unit without using an interrupt program.

  The scan time has a fixed length and a variable length. When the user is instructed to execute the ladder program 78 in accordance with the fixed-length scan time, the setting data creation unit 84 of the program creation support apparatus 1 further synchronizes the scan time with inter-unit synchronization or synchronization. You may select according to a user's instruction | indication whether it does not make it. Which is selected is stored in the setting data 79. The CPU 10 of the basic unit 3 refers to the setting data 79 to recognize which one has been selected, and executes a scan according to the selected operation mode. In addition, when it is selected that the scan time is synchronized by inter-unit synchronization, the setting data creation unit 84 may set the synchronization period according to a user instruction. When it is not selected that the scan time is synchronized by inter-unit synchronization, the setting data creation unit 84 may set the scan time according to a user instruction.

<Synchronous refresh of buffer memory>
As already mentioned in some places, synchronous refresh may be applied not only to the device but also to the buffer memory UG. Generally, the device is updated by refresh, but the buffer memory UG is not updated. Therefore, conventionally, with respect to the buffer memory UG, it is necessary to describe an instruction for executing direct communication in the ladder program 78 as necessary. The basic unit 3 has a plurality of occupied devices, some of which are allocated to the expansion unit 4. Therefore, for the device of the basic unit 3 (the third device 83) that is not assigned to the device of the expansion unit 4, the buffer memory UG can be refreshed by assigning the buffer memory UG. As a result, the buffer memory UG is also subject to synchronous refresh.

  The setting data creation unit 84 of the program creation support apparatus 1 selects the third device 83 corresponding to the buffer memory UG in response to a user instruction. For example, the setting data creation unit 84 displays a list of devices on the display unit 7 in order to create setting data for each expansion unit. In this list, identification information of each device, for example, a device number (for example, DM31000) is listed. Further, a column for designating the corresponding buffer memory UG may be provided in a column next to each device. In this column, identification information (eg, UG2158) of the buffer memory UG is input from the operation unit 8. The setting data creation unit 84 selects whether the third device 83 corresponding to the buffer memory UG is to be subjected to batch refresh or synchronous refresh according to a user instruction. The setting data creation unit 84 also writes in the setting data 79 the refresh method selected by the user.

  As described above, since the buffer memory UG is associated with the third device 83, the second update unit 76 performs synchronous refresh as the second device according to the setting data 79. In addition, for the buffer memory UG selected as a target for batch refresh, the first update unit 75 performs batch refresh as the first device.

  For the buffer memory UG as well, by executing the above-described synchronous refresh, problems such as simultaneity, order, and constant transfer delay time are solved or alleviated.

  The timing at which the synchronous refresh of the occupied device and the synchronous refresh of the buffer memory UG are executed within the synchronization period will be described. For example, the second update unit 76 executes synchronous refresh for the input device, and then executes synchronous refresh for the input buffer memory. The second updating unit 76 executes synchronous refresh for the output buffer memory, and then executes synchronous refresh for the output device. In this way, the input system may be refreshed first, and then the output system may be refreshed. The occupied device may be refreshed first and then the buffer memory may be refreshed. The second update unit 76 executes synchronous refresh for the input device, and then executes synchronous refresh for the output device. Further, the second update unit 76 executes synchronous refresh for the output buffer memory, and then executes synchronous refresh for the input buffer memory. Finally, the inter-unit synchronization unit 73 performs inter-unit synchronization. As described above, the latter case may be more advantageous for communication between expansion units.

  By the way, when trying to update the buffer memory UG by direct communication, a problem of crying may occur. This can occur when the size of the buffer memory UG is limited to 32 bits or the like. Therefore, by applying the above-mentioned measures against crying such as a double buffer configuration to the buffer memory UG, the crying-off problem is alleviated.

<Summary>
As described with reference to FIG. 1 and the like, the PLC 2 includes the basic unit 3 that repeatedly executes the user program for each scan and the expansion unit 4 that is connected to the basic unit 3. As described with reference to FIG. 8 and the like, the expansion unit 4 is
A device for storing device values related to an input value from an external device via the interface 123 or an output value to the external device via the interface 123 and to share data with the basic unit 3 Are allocated to the storage device 111 and an expansion unit timer 119 that counts clocks to measure time. As described with reference to FIG. 7 and the like, the basic unit 3 includes the basic unit timer 88, the inter-unit synchronization unit 73, the first update unit 75, and the second update unit 76. The inter-unit synchronization unit 73 synchronizes the timer value of the extension unit timer 119 and the timer value of the basic unit timer 88. The first updating unit 75 matches the data held in the extension unit 4 with the data held in the basic unit 3 within the refresh period for each scan. The second updating unit 76 detects whether the expansion unit 4 is within the period of processing executed at regular intervals during scanning based on the timer value of the basic unit timer 88 synchronized with the timer value of the expansion unit timer 119 by the inter-unit synchronization unit 73. The data held and the data held by the basic unit 3 are matched. The device allocated to the extension unit 4 described in the ladder program 78 that is a user program can be set as an update target by the first update unit 75 and / or an update target by the second update unit 76. The This alleviates the user's programming burden and improves usability.

  In other words, in this embodiment, a device that can be set as a batch refresh target, a device that can be set as a synchronous refresh target, or a device that can be set as a batch refresh target or a synchronous refresh target is prepared. It will be done. As a result, even if the description of the flat field ladder program 78 is copied to the inter-unit synchronization program, the device described in the flat field ladder program 78 can be refreshed only by changing the setting to the target of the inter-unit synchronous refresh. Is executed. Therefore, the program change work is reduced. In addition, since it is possible for the user to freely set whether or not to include in the inter-unit synchronous refresh target, by removing some devices from the inter-unit synchronous refresh target (FIG. 16 shows a plurality of devices allocated to the expansion unit). In this example, the devices are collectively set as a target or excluded from the target.), And an increase in the inter-unit synchronous refresh period can be suppressed.

  As described above, the device may be set as an update target by the first update unit 75 or may be set as an update target by the second update unit 76. The basic unit control unit 70 and the setting data creation unit 84 may function as a selection unit that selects at least one of the first update unit 75 and the second update unit 76 as a unit for updating the device. This selection of the update unit corresponds to selection of whether to perform batch refresh or synchronous refresh, and may correspond to selection of update timing. Thus, by making it possible to select the update timing of data to be shared between the basic unit 3 and the extension unit 4, it is possible to improve usability. That is, synchronous refresh is executed not only in the batch refresh period but also in other periods such as a period in which the user program is being executed. As a result, it is difficult for the batch refresh period to become too long. For some devices, both synchronous refresh and batch refresh may be applied.

  The basic unit 3 further includes an inter-unit synchronization unit 73 that executes a synchronization process for synchronizing the control timing of the internal function of the basic unit 3 with the control timing of the expansion unit 4. The inter-unit synchronization unit 73 is realized by a timer or the like, for example. The second update unit 76 holds the data held by the extension unit 4 and the basic unit 3 at the timing when the inter-unit synchronization unit 73 executes the synchronization process within the period in which the user program is being executed. Synchronous refresh is performed to match the data. In this way, synchronous refresh is executed at the timing of inter-unit synchronization. Although it is possible to perform direct communication between the device and the buffer memory in the user program, this is poor in applicability of the program code (ladder diagram) and requires complicated programming. On the other hand, if synchronous refresh is executed at the timing of inter-unit synchronization, synchronous refresh of devices and buffer memories can be performed with a simple code similar to the program code for batch refresh. Thus, the burden on the user's programming will be reduced.

  As described with reference to FIGS. 6 and 10, the inter-unit synchronization unit 73 performs inter-unit synchronization when the inter-unit synchronization timing comes. As a result, the synchronization between the units is executed even during the execution period of the user program, so that the difference between the control timing of the basic unit 3 and the control timing of the expansion unit 4 can be reduced. In addition, synchronous refresh is performed accompanying the inter-unit synchronization during the execution period of the user program, and the device and buffer memory can be updated without waiting for the batch refresh period.

  As described with reference to FIG. 14 and FIG. 15, the basic unit 3 may execute a scan using the synchronization between units as a trigger. That is, the basic unit 3 may further include an inter-unit synchronization unit 73 that synchronizes the timing at which the first update unit 75 executes the update with respect to the control cycle applied to the extension unit 4. The inter-unit synchronization unit 73 synchronizes the control cycle applied to the extension unit 4 with respect to the control cycle of the basic unit 3. However, the inter-unit synchronization unit 73 may operate so as to synchronize the timing at which the first update unit 75 executes the update with respect to the control cycle applied to the extension unit 4. Internal processing of the expansion unit 4 is executed in synchronization with the control cycle of the expansion unit 4. The data stored in the device or buffer memory may be necessary for internal processing operations or may be the result of internal processing. If the data is refreshed according to the control cycle of the expansion unit 4, the data transmission delay time will be reduced.

  Each of the basic unit 3 and the expansion unit 4 has a device memory that is a memory for holding data. The device memory includes an input device memory for transmitting the data of the expansion unit 4 to the basic unit 3, and the data of the basic unit 3. Output device memory for transmitting to the expansion unit 4. The first update unit 75 and the second update unit 76 update the data in the input device memory by copying the data stored in the device memory of the expansion unit 4 to the device memory of the basic unit 3, and The data in the output device memory is updated by copying the data stored in the device memory to the device memory of the expansion unit 4. As a result, batch refresh and synchronous refresh are performed on the input device and output device. As described above, the refresh operations of the first update unit 75 and the second update unit 76 are very similar, so that the batch refresh code can be easily used as a synchronization refresh code.

  The input device memory stores data representing the state of the functions of the expansion unit 4. For example, if the controlled device 16 of the expansion unit 4 is a sensor or the like, a device value indicating a detection result (detection state) of the sensor is stored in the input device memory. The output device memory stores data controlled by the function of the expansion unit 4. For example, if the controlled device 16 of the expansion unit 4 is a motor or the like, a device value indicating the rotational speed of the motor or the like is stored in the output device memory.

  As described with reference to FIG. 6 and the like, the first update unit 75 updates the data held in the output device memory during the batch refresh period. Next, the first update unit 75 updates the data held in the input device memory. Then, the second update unit 76 may update the data within a period during which the user program is executed. Since the output device memory stores data and instructions that are referred to by internal processing, the output device memory may be refreshed first during the batch refresh period. Of course, the input device memory may be refreshed first.

  The second updating unit 76 provides data between the device memory that is provided in the basic unit 3 and holds data, and the buffer memory that is provided in the expansion unit 4 and holds data that is not subject to batch refresh. You may match. By associating the device with the buffer memory in this way, the buffer memory can be refreshed as if it were a device.

  The basic unit control unit 70 may include a storage device 12 that stores update target designation information (setting data 79) for designating data to be updated by the second update unit 76. The second update unit 76 refreshes the data specified by the setting data 79 synchronously within a period during which the user program is being executed. The first update unit 75 performs batch refresh of data not specified by the setting data 79 during the batch refresh period. Thus, the refresh timing applied to the device and the buffer memory may be held by the setting data 79.

  As described with respect to the setting data creation unit 84, the setting data 79 may be information created on a program creation support device that is connected to the basic unit 3 and creates a user program and transfers it to the basic unit 3. Good. The operation unit 8 of the program creation support apparatus 1 is easier to operate than the operation unit 6 of the basic unit 3. Further, the display unit 7 of the program creation support apparatus 1 has a larger amount of information that can be displayed than the display unit 5 of the basic unit 3. Therefore, it will be easy to select the refresh timing applied to the device and the buffer memory.

  While the second update unit 76 is updating data, the basic unit control unit 70 and the device control unit 72 serve as an exclusive / arbitration unit that excludes or arbitrates reading / writing of the data by means other than the second update unit 76. May function. As described above, if the data is changed during the execution of the synchronous refresh, a simultaneity problem may occur. Therefore, the problem of simultaneity can be solved by exclusive or arbitrating the reading and writing of data by other means.

  The device control unit 72 reads / writes the plurality of data by means other than the second update unit 76 during a period in which the plurality of data that are required to be linked to each other is updated by the second update unit 76. May be exclusive or arbitrated. This will solve the concurrency problem.

  In the device control unit 72, the second update unit 76 updates a plurality of data required to make the data transmission time (transmission delay time) between the basic unit 3 and the expansion unit 4 substantially constant. In a certain period, reading / writing of the plurality of data by means other than the second updating unit 76 may be exclusive or arbitrated. As a result, the variation in the propagation delay time for a plurality of device values will be reduced.

  The device control unit 72 excludes reading / writing of the plurality of data by means other than the second update unit 76 during a period in which the plurality of data each having an update order is updated by the second update unit 76 Or mediation may be performed. For example, the plurality of data may be bit type data and word type data. When copying the bit type data and the word type data of the basic unit 3 to the extension unit 4, the second updating unit 76 may copy the bit type data and then copy the word type data. In addition, when copying the bit type data and the word type data of the extension unit 4 to the basic unit 3, the second update unit 76 may copy the bit type data after copying the word type data. . This will solve the ordering problem described above. The present embodiment can also be applied to a case where a part of word type data is used as bit type data.

  The extension unit 4 may delay the start of internal processing executed by the extension unit 4 according to the delay time of the update process in the second update unit 76. If the number of devices and buffer memories to be subjected to synchronous refresh increases or if data retransmission due to flow control frequently occurs, the time for synchronous refresh becomes longer. As a result, the synchronous refresh cannot be completed even after a predetermined waiting time. If the internal processing is started even though the synchronous refresh has not been completed, the above-described simultaneity problem may occur. Therefore, in such a case, internal processing may be delayed to solve problems such as simultaneity.

  The device control unit 72 may prohibit the interrupt process while the second update unit 76 is updating data. If an interrupt occurs during synchronous refresh, problems such as simultaneity and variations in transmission delay time are likely to occur. Disabling interrupts during synchronous refresh will alleviate simultaneity problems and transmission delay time variations.

  The expansion unit 4 may hold data in the storage device 12 provided in the basic unit 3. Generally, since the device and the buffer memory are provided in both the basic unit 3 and the expansion unit 4, refreshing is necessary. However, the first device 118 and the second device 120 of the expansion unit 4 may be provided in the storage device 12 of the basic unit 3 and the refresh may be executed in the storage device 12. This means that it does not matter where the expansion unit 4 has device memory and buffer memory. As described above, even if the device memory and buffer memory of the basic unit 3 and the device memory and buffer memory of the expansion unit 4 are arranged in the same storage device, the above-described embodiments can be applied.

  Meanwhile, the storage device 12 of the basic unit 3 stores a user program (ladder program 78) and a synchronous program (part of the control program 77) that is executed in synchronization with the execution timing of the internal processing of the expansion unit 4. It may function as a program storage means. These are executed by the CPU 10 as program execution means. In particular, the ladder program 78 is executed by the program execution unit 71. The first device 81 and the second device 82 are an example of a first device memory allocated to internal processing of the expansion unit 4 in the user program.

  The basic unit 3 or the expansion unit 4 of the PLC 2 has a second device memory that is controlled so as to store the same data as the data stored in the first device memory. For example, the second device memory is secured in the storage device 12 and accessed by the expansion unit 4. Alternatively, the second device memory may be the first device 118 or the second device 120 secured in the storage device 111 of the expansion unit 4. The first update unit 75 and the second update unit 76 function as an update unit that executes an update process so that the data stored in the first device memory matches the data stored in the second device memory. However, the first update unit 75 and the second update unit 76 may be realized by the CPU 110 of the expansion unit 4. The inter-unit synchronization unit 114 of the expansion unit 4 may execute an interrupt to the basic unit 3 according to a synchronization period managed by itself or the expansion unit control unit 113, and perform synchronous refresh and inter-unit synchronization. Note that the setting data creation unit 84 of the program creation support device 1 and the operation unit 6 of the basic unit 3 set which of the batch refresh period and the synchronous refresh period to execute the update process. Functions as setting means. The setting data 79 may be stored in the storage device 12 and the storage device 111 accessible from the expansion unit 4 and read by the expansion unit control unit 113 and the inter-unit synchronization unit 114.

  The basic unit 3 includes an inter-unit synchronization unit 73 that synchronizes the control cycle of the basic unit 3 and the control cycle of the extension unit 4, and a predetermined period in the synchronization cycle in which the inter-unit synchronization unit 73 executes synchronization processing. Has a second updating unit 75 that updates so that the data held by the basic unit 3 matches the data held by the basic unit 3. The second update unit 75 may update a plurality of data that are required to be linked to each other or a plurality of data that are requested to be updated in accordance with a predetermined update order. This will alleviate simultaneity and ordering issues.

  Note that an expansion unit that handles data for which real-time performance is not required may be batch refreshed as in the past. On the other hand, an extension unit that requires real-time performance and high-speed operation such as a motion unit (positioning unit) may be subjected to synchronous refresh. In particular, when the synchronization period is shortened, synchronous refresh is executed many times in one scan time. Therefore, as the number of expansion units and devices to be subjected to synchronous refresh increases, the scan time becomes longer or the start of internal processing is delayed. Therefore, if the synchronization period is shorter than the scan time, it may be desirable to narrow down the target of synchronization refresh. This is because the user can select the data to be updated by the second update unit 76 and the data to be updated by the first update unit 75 from among the data of the second extension unit 4 so that the user can perform synchronous refresh. You may squeeze.

  The extension unit 4 may execute internal processing with reference to the data after the second update unit 76 completes the data update processing. This is because if the internal processing uses the data before the data update processing is completed, a simultaneity problem occurs. Note that the second update unit 76 may execute data update processing during a period when the expansion unit 4 is not executing internal processing. This will alleviate the simultaneity problem.

  The extension unit 4 may include a first buffer 121 that stores data updated by the second update unit 76 and a second buffer 122 that stores data referred to by internal processing of the extension unit 4. . In this case, the buffer updating unit 116 updates the data stored in the first buffer 121 and the data stored in the second buffer 122 so that the data stored in the second buffer 122 matches when the inter-unit synchronization process is executed. Functions as update means. The second update unit 76 executes the update process after the buffer update unit 116 completes the update process. For example, the second update unit 76 executes the synchronous refresh after a predetermined period has elapsed from the start timing of the synchronous cycle. The predetermined period is a period sufficient for the buffer update unit 116 to complete the update process, and is set in advance.

  The extension unit 4 may further include a postponing unit 115 that postpones the start timing of the internal processing when the synchronization processing by the inter-unit synchronization unit 114 is delayed. The delay of the synchronization process is often caused by an unexpected event such as an error in the transmission path. Therefore, it would be advantageous to delay the internal processing according to the delay time rather than always waiting for a certain period.

  As described with reference to FIGS. 14 and 15, the basic unit 3 may transition to a batch refresh period when the inter-unit synchronization unit 73 performs the synchronization process. This makes it possible to match the scan start timing with the synchronization period obtained by the inter-unit synchronization.

  As described above, the basic unit 3 has a device memory allocated to the internal processing of the expansion unit 4 in the user program. The basic unit 3 or the expansion unit 4 may have a buffer memory UG that is controlled to store the same data as the data stored in the device memory. When the buffer memory UG is arranged in the basic unit 3, the buffer memory UG is accessed from the expansion unit 4 and data is read / written. The first update unit 75 and the second update unit 76 perform update processing so that the data stored in the device memory matches the data stored in the buffer memory UG in synchronization with the control cycle of the expansion unit 4. May be executed. By assigning the buffer memory UG to the device in this way, batch refresh and synchronous refresh can be applied to the buffer memory UG as if it were a device.

  As described above, the present invention may be advantageous when a plurality of expansion units 4 transmit and receive device values via the basic unit 3. In this case, the basic unit 3 is allocated to internal processing of the first extension unit 4 in the user program and the inter-unit synchronization unit 73 that synchronizes at least the control period of the basic unit 3 and the control periods of the plurality of extension units 4. A first device memory for storing data to be transferred from the first extension unit 4 to the basic unit 3 and an internal process of the second extension unit 4 in the user program. 2 has a second device memory for storing data to be transferred to the expansion unit 4. In FIG. 7, only one each of the first device 81 and the second device 82 is shown, but there may be a plurality of them. Therefore, the first device memory and the second device memory correspond to a plurality of first devices 81 and a plurality of second devices 82.

  The first extension unit 4 may have a first buffer memory controlled to store the same data as the data stored in the first device memory. The second expansion unit 4 may have a second buffer memory that is controlled to store the same data as the data stored in the second device memory. FIG. 8 illustrates the first device 118 and the second device 120, but a buffer memory UG is provided in the storage device 111 separately from this. As shown in FIG. 13, the device value input from the first extension unit 4 may be transferred to the second extension unit 4 via the basic unit 3. In order to realize this, the first update unit 75 or the second update unit 76 is stored in the first buffer memory and the data stored in the first device memory in synchronization with the control cycle of the expansion unit 4. The update process is executed so that the stored data matches, and then the update process is executed so that the data stored in the second device memory matches the data stored in the second buffer memory. The first update unit 75 or the second update unit 76 may be provided on the extension unit 4 side. The first extension unit 4 starts internal processing after the second update unit 76 completes the synchronous refresh. Similarly, the second extension unit 4 starts internal processing after the second update unit 76 completes synchronous refresh. Thereby, transmission / reception of device values between a plurality of extension units can be realized with only a transmission delay time of one synchronization period.

Claims (29)

A programmable logic controller having a basic unit that repeatedly executes a user program for each scan, and an expansion unit connected to the basic unit,
The expansion unit is
An interface to which an external device is connected;
A storage unit in which a device value related to an input value from the external device via the interface or an output value to the external device via the interface is stored, and a device for sharing data with the basic unit is allocated;
An expansion unit timer that counts the clock and measures time,
With
The basic unit is
A basic unit timer that counts the clock and measures time,
Synchronization means for synchronizing the timer values of the extension unit timer and the basic unit timer;
First update means for matching the data held by the extension unit and the data held by the basic unit within a refresh period for each scan;
Based on the timer value of the basic unit timer synchronized with the timer value of the extension unit timer by the synchronization means, the data held by the extension unit within the period of processing executed at regular intervals during scanning and the basic Second update means for matching the data held by the unit;
With
The programmable unit characterized in that the device of the extension unit described in the user program can be set as an update target by the first update means and / or an update target by the second update means. Logic controller.   2. The programmable logic controller according to claim 1, wherein the device is set as one of an update target by the first update unit and an update target by the second update unit.   2. The programmable logic controller according to claim 1, further comprising selection means for selecting at least one of the first update means and the second update means as update means for updating the device. The basic unit includes a program storage unit that stores the user program and an inter-unit synchronization program executed based on a timer value of the basic unit timer synchronized by the synchronization unit,
The second update means matches the data held in the extension unit with the data held in the basic unit when the device is described in the inter-unit synchronization program. The programmable logic controller according to claim 1.   The second updating means matches the data held by the extension unit with the data held by the basic unit even during a period in which the user program is being executed during the scan. The programmable logic controller of claim 1 characterized by the above. The timer value of the extension unit timer is used as a start timing of internal processing of the extension unit,
The internal processing of the extension unit is processing for calculating the device value based on an input value from the external device or processing for calculating an output value from the device value to the external device. The programmable logic controller according to any one of 1 to 5.   2. The first update means performs update within a refresh period for each scan based on a timer value of the basic unit timer synchronized with a timer value of the extension unit timer by the synchronization means. Programmable logic controller described in 1. The basic unit and the extension unit each have a device that is a storage area for holding data,
The device includes an input device for transmitting data of the expansion unit to the basic unit, and an output device for transmitting data of the basic unit to the expansion unit;
The first update unit and the second update unit update a device value that is data of the input device by copying a device value that is data stored in the device of the expansion unit to the device of the basic unit. And updating a device value, which is data of the output device, by copying a device value, which is data stored in the device of the basic unit, to the device of the extension unit. 8. The programmable logic controller according to any one of 7 above. The input device stores data representing a function state of the extension unit;
The programmable logic controller according to claim 8, wherein the output device stores data for controlling a function of the extension unit.   In the refresh period, the first updating means updates the data held in the output device and the data held in the input device, and is scanned at regular intervals during scanning based on the timer value of the basic unit timer. The programmable according to claim 8 or 9, wherein the second updating means updates data held in the extension unit and data held in the basic unit during a period of processing to be executed. -Logic controller.   The second update unit matches data between a device provided in the basic unit and holding data and a buffer memory provided in the extension unit and holding data not to be refreshed The programmable logic controller according to any one of claims 1 to 7, wherein the programmable logic controller is provided. The selection means includes storage means for storing update target designation information for designating data to be updated by the second update means,
The second update means updates the data specified by the update target specification information,
4. The programmable logic controller according to claim 3, wherein the first update unit updates data that is not specified by the update target specification information during the refresh period. 5.   13. The update target designation information is information created on a program creation support device that is connected to the basic unit, creates the user program, and transfers the user program to the basic unit. Programmable logic controller.   2. The apparatus according to claim 1, further comprising an exclusion / arbitration unit that exclusively or arbitrates reading / writing of the data by means other than the second update unit while the second update unit is updating data. 14. The programmable logic controller according to any one of items 13.   The exclusion / arbitration means is configured to store the plurality of data by means other than the second update means during a period in which the plurality of data required to be linked to each other is updated by the second update means. The programmable logic controller according to claim 14, wherein reading and writing are exclusive or arbitrated.   The exclusion / arbitration means is configured to update the second update means during a period in which a plurality of data required to make the data transmission time between the basic unit and the extension unit constant is updated by the second update means. The programmable logic controller according to claim 14, wherein reading / writing of the plurality of data by means other than the second update means is exclusive or arbitrated.   The exclusion / arbitration means reads / writes the plurality of data by means other than the second update means in a period in which the plurality of data each having an update order is updated by the second update means. 15. The programmable logic controller of claim 14, wherein the programmable logic controller is exclusive or arbitrated. The plurality of data are bit type data and word type data,
The second updating means copies the bit type data and the word type data after copying the bit type data and the word type data of the basic unit to the extension unit. 18. The programmable logic controller according to claim 17, wherein when the bit type data and the word type data are copied to the basic unit, the bit type data is copied after the word type data is copied. .   The programmable logic controller according to any one of claims 14 to 18, wherein the exclusion / arbitration unit prohibits an interrupt process while the second update unit is updating data.   20. The extension unit according to claim 1, wherein the extension unit delays a start of an internal process executed by the extension unit according to a delay time of an update process in the second update unit. Programmable logic controller.   21. The programmable logic controller according to claim 1, wherein the extension unit holds the data in a storage device provided in the basic unit.   The extension unit performs internal processing with reference to the data after the second update unit completes the data update processing, according to any one of claims 1 to 21. Programmable logic controller.   The programmable logic circuit according to any one of claims 1 to 22, wherein the second update unit executes the data update process during a period when the extension unit is not executing an internal process. controller. The expansion unit is
A first buffer for storing the data updated by the second update means;
A second buffer for storing data referred to by internal processing of the extension unit;
Further comprising third update means for updating the data stored in the first buffer and the data stored in the second buffer so that the data stored in the second buffer coincide with each other when the synchronization means executes a synchronization process;
The programmable logic controller according to claim 1, wherein the second update unit executes the update process after the third update unit completes the update process. The expansion unit is
2. The programmable logic controller according to claim 1, further comprising means for delaying a start timing of internal processing of the expansion unit when the synchronization processing by the synchronization unit is delayed.   2. The programmable logic controller according to claim 1, wherein the basic unit transitions to the refresh period when the synchronization unit performs a synchronization process. 3. A basic unit that is connected to an expansion unit of a programmable logic controller and repeatedly executes a user program for each scan.
The expansion unit is
An interface to which an external device is connected;
A storage unit in which a device value related to an input value from the external device via the interface or an output value to the external device via the interface is stored, and a device for sharing data with the basic unit is allocated;
An expansion unit timer that counts the clock and measures time,
With
The basic unit is
A basic unit timer that counts the clock and measures time,
Synchronization means for synchronizing the timer values of the extension unit timer and the basic unit timer;
First update means for matching the data held by the extension unit and the data held by the basic unit within a refresh period for each scan;
Based on the timer value of the basic unit timer synchronized with the timer value of the extension unit timer by the synchronization means, the data held by the extension unit within the period of processing executed at regular intervals during scanning and the basic Second update means for matching the data held by the unit;
With
The basic unit is characterized in that the device of the extension unit described in the user program can be set as an update target by the first update means and / or an update target by the second update means. . A control method of a basic unit connected to an extension unit of a programmable logic controller and repeatedly executing a user program for each scan,
The expansion unit is
An interface to which an external device is connected;
A storage unit in which a device value related to an input value from the external device via the interface or an output value to the external device via the interface is stored, and a device for sharing data with the basic unit is allocated;
An expansion unit timer that counts the clock and measures time,
With
The control method is:
A basic unit timer that counts clocks and measures time; a synchronization step that synchronizes the timer values of the extension unit timer and the basic unit timer;
A first update step of matching the data held by the extension unit with the data held by the basic unit within a refresh period for each scan;
Based on the timer value of the basic unit timer synchronized with the timer value of the extension unit timer by the synchronization step, the data held by the extension unit within the period of processing executed at regular intervals during scanning and the basic A second update step for matching the data held by the unit;
Have
The basic unit characterized in that the device of the extension unit described in the user program can be set as an update target by the first update step and / or an update target by the second update step. Control method.   A program for causing a computer to execute each step of the control method according to claim 28.