CN108073238A - A kind of server architecture and operation method - Google Patents

A kind of server architecture and operation method Download PDF

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Publication number
CN108073238A
CN108073238A CN201610998053.6A CN201610998053A CN108073238A CN 108073238 A CN108073238 A CN 108073238A CN 201610998053 A CN201610998053 A CN 201610998053A CN 108073238 A CN108073238 A CN 108073238A
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bmc
bios
server architecture
code
storage
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CN108073238B (en
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张伟进
杨再松
王飞舟
石明
林俊
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SHENZHEN ZHONGDIAN CHANGCHENG INFORMATION SAFETY SYSTEM Co Ltd
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SHENZHEN ZHONGDIAN CHANGCHENG INFORMATION SAFETY SYSTEM Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

The present invention is suitable for server field, provides a kind of server architecture and operation method, and server architecture includes processor CPU, north bridge chips, South Bridge chip, and the server architecture further includes baseboard management controller BMC：The CPU or the South Bridge chip are connected by LPC low pin count mesh interfaces with the SPI controller Serial Peripheral Interface controllers of the BMC；The storage medium of the BMC is divided into two regions, first area storage BMC code, second area storage BIOS code.Advantageous effect of the present invention is following two aspect, on the one hand eliminates BIOS storage chips, reduces hardware cost, be conducive to the highly integrated of server architecture, on the other hand extend the pattern of BIOS code transmission, enhances the intelligence degree of server architecture.

Description

A kind of server architecture and operation method
Technical field
The invention belongs to server field more particularly to a kind of server architectures and operation method.
Background technology
Server, also referred to as servomechanism are to provide the equipment of the service of calculating.The composition of server architecture includes processor, hard Disk, memory, system bus, BIOS storage chips etc. are similar with general computer architecture, but highly reliable due to needing to provide Service, it is therefore more demanding in processing capacity, stability, reliability, security, scalability, manageability etc..
However, existing server architecture can not save BIOS storage chips, hardware cost is high and is unfavorable for the height of module It is integrated.The reason is that, it is necessary to read BIOS image files from BIOS storage chips, just when server architecture loads BIOS System can be guided to start, it can be seen that, BIOS storage chips can not save, since server architecture has to set up BIOS storages Chip, therefore hardware cost is high and is unfavorable for the highly integrated of module.
The content of the invention
The embodiment of the present invention is designed to provide a kind of server architecture, it is intended to which solving existing server architecture can not save Fall BIOS storage chips, hardware cost it is high and be unfavorable for module it is highly integrated the problem of.
The embodiment of the present invention is achieved in that a kind of server architecture, including processor CPU, north bridge chips, south bridge core Piece, the server architecture further include baseboard management controller BMC：
The CPU or the South Bridge chip pass through LPC low pin count mesh interfaces and the SPI controller of the BMC Serial Peripheral Interface controller is connected；
The storage medium of the BMC is divided into two regions, first area storage BMC code, second area storage BIOS code。
Further, in the server architecture, the Firmware firmwares of the BMC are connected in the SPI controller。
Further, in the server architecture, the CPU or the South Bridge chip pass through the SPI The controller connections Firmware.
Further, in the server architecture, the storage medium of the BMC is Flash Rom flash memories.
Further, in the server architecture, the storage medium of the BMC is RAM.
Further, in the server architecture, the BIOS code are BIOS image files.
Another embodiment of the present invention is to provide a kind of operation method based on above-mentioned server architecture, including：
The storage address of first area storage BMC code is labeled as ROMA addresses by the BMC；
The storage address of second area storage BIOS code is labeled as ROMB addresses；
Wherein, the ROMB addresses are different addresses from the ROMA addresses.
In the present invention, the CPU or the South Bridge chip pass through LPC low pin count mesh interfaces and the SPI of the BMC Controller Serial Peripheral Interface controllers are connected；The storage medium of the BMC is divided into two regions, and first area is deposited Store up BMC code, second area storage BIOS code.Since BMC has BIOS code, solves existing server rack Structure can not save BIOS storage chips, hardware cost it is high and be unfavorable for module it is highly integrated the problem of.CPU is obtained in BMC BIOS code, advantageous effect are following two aspect, on the one hand eliminate BIOS storage chips, reduce hardware cost, favorably In the highly integrated of server architecture, the pattern that BIOS code are transmitted on the other hand is extended, enhances the intelligence of server architecture Degree can be changed.
Description of the drawings
Fig. 1 is the structure diagram of server architecture provided in an embodiment of the present invention；
Fig. 2 is CPU provided in an embodiment of the present invention or the connection figure of the South Bridge chip and BMC；
Fig. 3 is the implementing procedure figure of operation method provided in an embodiment of the present invention；
Fig. 4 BMC Flash ROM division ROMA addresses provided in an embodiment of the present invention and the sample figure of ROMB addresses；
Fig. 5 is the design sketch of BMC Flash ROM division ROMA addresses and ROMB addresses provided in an embodiment of the present invention；
Fig. 6 is the implementing procedure figure of acquisition BIOS code provided in an embodiment of the present invention；
Fig. 7 is the implementing procedure figure of modification BIOS code provided in an embodiment of the present invention.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, it is right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.
It should be appreciated that ought use in this specification and in the appended claims, term " comprising " and "comprising" instruction Described feature, entirety, step, operation, the presence of element and/or component, but it is not precluded from one or more of the other feature, whole Body, step, operation, element, component and/or its presence or addition gathered.
It is also understood that the term used in this description of the invention is merely for the sake of the mesh for describing specific embodiment And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on Other situations are hereafter clearly indicated, otherwise " one " of singulative, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is Refer to any combinations and all possible combinations of one or more of the associated item listed, and including these combinations.
As used in this specification and in the appended claims, term " if " can be according to context quilt Be construed to " when ... " or " once " or " in response to determining " or " in response to detecting ".Similarly, phrase " if determine " or " if reading [described condition or event] " can be interpreted to mean according to context " once it is determined that " or " in response to true It is fixed " or " once detecting [described condition or event] " or " in response to detecting [described condition or event] ".
Embodiment one
Fig. 1 is the structure diagram of server architecture provided in an embodiment of the present invention, and details are as follows：
A kind of server architecture, including processor CPU, north bridge chips, South Bridge chip, the server architecture further includes base Board management controller BMC；
The CPU or the South Bridge chip pass through LPC low pin count mesh interfaces and the SPI controller of the BMC Serial Peripheral Interface controller is connected；
The storage medium of the BMC is divided into two regions, first area storage BMC code, second area storage BIOS code。
Fig. 2 is CPU provided in an embodiment of the present invention or the connection figure of the South Bridge chip and BMC, and details are as follows：
Wherein, the South Bridge chip is connected by LPC low pin count mesh interface, Pcie interfaces and USB interface with BMC It connects.
Pcie interfaces are PCI Express bus interface.
Wherein, the BMC passes through LPC interfaces, receiving area division instruction；
According to default division proportion, the storage region of storage medium is divided into two regions, first area storage BMC Code, second area storage BIOS code.
Wherein, the BMC detects whether to receive BIOS more new commands；
If the BMC receives the BIOS more new commands, then the BIOS of second area is updated in storage medium code。
In embodiments of the present invention, CPU obtains BIOS code in BMC, and advantageous effect is following two aspect, a side Face eliminates BIOS storage chips, reduces hardware cost, is conducive to the highly integrated of server architecture, on the other hand extends The pattern of BIOS code transmission enhances the intelligence degree of server architecture.
Embodiment two
Fig. 3 is the implementing procedure figure of operation method provided in an embodiment of the present invention, and details are as follows：
The storage address of first area storage BMC code is labeled as ROMA addresses by S301, the BMC；
The storage address of second area storage BIOS code is labeled as ROMB addresses by S302；
Wherein, the ROMB addresses are different addresses from the ROMA addresses.
Fig. 4 BMC Flash ROM division ROMA addresses provided in an embodiment of the present invention and the sample figure of ROMB addresses.
CPU south bridge south bridges, by the SPI controller connections of LPC and BMC, BMC's Firmware is hung over below SPI controller.
In Rom map, by the storage address of Firmware storage BMC code labeled as ROMA addresses, Firmware is deposited The storage address for storing up BIOS code is labeled as ROMA addresses.
In embodiments of the present invention, CPU obtains BIOS code in BMC, and advantageous effect is following two aspect, a side Face eliminates BIOS storage chips, reduces hardware cost, is conducive to the highly integrated of server architecture, on the other hand extends The pattern of BIOS code transmission enhances the intelligence degree of server architecture.
Embodiment three
Fig. 5 is the design sketch of BMC Flash ROM division ROMA addresses and ROMB addresses provided in an embodiment of the present invention, in detail It states as follows：
In Figure 5, the BMC rom of 32MB are divided into two regions, 0-24MB is first area, for storing BMC Code, 24MB to 32MB are second area, for storing BIOS code regions.
Setting up procedure is as follows：
1) it is configured on the SPI controller of BMC,
The Flash Rom of 32MB are divided into 2 regions, ROMA：00000000h~18000000h (24MB) and ROMB: 18000000h~1f000000h (8MB).
2) according to AST2400 specifications：
Control SCU2C：Misc.Control Register offset 2C positions, Bit0 are set to Enable.
BMC codes are placed on 00000000h~18000000h, and the execution of BMC codes is not changed.Bios code It is placed on 18000000h~1f000000h.
When CPU accesses SPI controller by LPC, SPI controller is ROMB address resolution into BIOS Flash addresses.
Example IV
The embodiment of the present invention describes the process that CPU accesses SPI controller, and details are as follows：
When the CPU accesses the SPI controller by LPC, the SPI controller the ROMB address resolution into BIOS Flash addresses.
Embodiment five
Fig. 6 is the implementing procedure figure of acquisition BIOS code provided in an embodiment of the present invention, and details are as follows：
S301, the CPU detect whether to receive BMC loadings instruction or BIOS loading instructions；
S302 if receiving BMC loading instruction, then obtains the from the storage medium of the baseboard management controller The BMC code in one region；
S303 if receiving the BIOS loadings instruction, obtains the secondth area from the storage medium of baseboard management controller The BIOS code in domain.
Embodiment six
Fig. 7 is the implementing procedure figure of modification BIOS code provided in an embodiment of the present invention, and details are as follows：
S401, the processor detect whether to receive BIOS modification instructions；
S402, if the processor receives the BIOS modifications instruction, then in the storage of the baseboard management controller The BIOS code of second area are changed in medium.
Through the above description of the embodiments, it is apparent to those skilled in the art that the present invention can borrow Help software that the mode of required common hardware is added to realize.The program can be stored in read/write memory medium, described Storage medium, as random access memory, flash memory, read-only memory, programmable read only memory, electrically erasable programmable storage Device, register etc..The storage medium is located at memory, and processor reads the information in memory, this hair is performed with reference to its hardware Method described in bright each embodiment.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, all should by the change or replacement that can be readily occurred in It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.

Claims (10)

  1. A kind of 1. server architecture, including processor CPU, north bridge chips, South Bridge chip, which is characterized in that the server rack Structure further includes baseboard management controller BMC：
    The CPU or the South Bridge chip are serial by LPC low pin count mesh interfaces and the SPI controller of the BMC Peripheral bus controller is connected；
    The storage medium of the BMC is divided into two regions, first area storage BMC code, second area storage BIOS code。
  2. 2. server architecture as described in claim 1, which is characterized in that the Firmware firmwares of the BMC are connected in the SPI controller。
  3. 3. server architecture as claimed in claim 2, which is characterized in that the CPU or the South Bridge chip pass through described The SPI controller connections Firmware.
  4. 4. server architecture as described in claim 1, which is characterized in that the storage medium of the BMC dodges for Flash Rom It deposits.
  5. 5. server architecture as described in claim 1, which is characterized in that the storage medium of the BMC stores for non-volatile RAM Device.
  6. 6. server architecture as described in claim 1, which is characterized in that the BIOS code are BIOS image files.
  7. 7. a kind of operation method based on server architecture described in claim 1, which is characterized in that including：
    The storage address of first area storage BMC code is labeled as ROMA addresses by the BMC；
    The storage address of second area storage BIOS code is labeled as ROMB addresses；
    Wherein, the ROMB addresses are different addresses from the ROMA addresses.
  8. 8. operation method as claimed in claim 7, which is characterized in that the operation method further includes：
    When the CPU accesses the SPI controller by LPC, the SPI controller is the ROMB address resolution into BIOS Flash addresses.
  9. 9. operation method as claimed in claim 7, which is characterized in that the operation method further includes：
    The CPU detects whether to receive BMC loadings instruction or BIOS loading instructions；
    If receiving the BMC loadings instruction, then first area is obtained from the storage medium of the baseboard management controller BMC code；
    If receiving the BIOS loadings instruction, the BIOS of second area is obtained from the storage medium of baseboard management controller code。
  10. 10. operation method as claimed in claim 7, which is characterized in that the operation method further includes：
    The processor detects whether to receive BIOS modification instructions；
    If the processor receives the BIOS modifications instruction, then changed in the storage medium of the baseboard management controller The BIOS code of second area.
CN201610998053.6A 2016-11-11 2016-11-11 Server architecture and operation method Active CN108073238B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109828774A (en) * 2018-12-29 2019-05-31 苏州中晟宏芯信息科技有限公司 A kind of server system and its starting method
CN113031975A (en) * 2021-03-24 2021-06-25 山东英信计算机技术有限公司 Method and device for sharing storage chip by multiple images and server

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140047224A1 (en) * 2012-08-07 2014-02-13 American Megatrends, Inc. Method of flashing bios using service processor and computer system using the same
CN103593250A (en) * 2013-11-19 2014-02-19 浪潮电子信息产业股份有限公司 Realizing method for modifying BIOS Setup option out of band
JP2015184935A (en) * 2014-03-25 2015-10-22 日本電気株式会社 I2c bus arbitration system and arbitration method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140047224A1 (en) * 2012-08-07 2014-02-13 American Megatrends, Inc. Method of flashing bios using service processor and computer system using the same
CN103593250A (en) * 2013-11-19 2014-02-19 浪潮电子信息产业股份有限公司 Realizing method for modifying BIOS Setup option out of band
JP2015184935A (en) * 2014-03-25 2015-10-22 日本電気株式会社 I2c bus arbitration system and arbitration method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109828774A (en) * 2018-12-29 2019-05-31 苏州中晟宏芯信息科技有限公司 A kind of server system and its starting method
CN113031975A (en) * 2021-03-24 2021-06-25 山东英信计算机技术有限公司 Method and device for sharing storage chip by multiple images and server

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