WO2015058533A1

WO2015058533A1 - Information processing method and electronic device

Info

Publication number: WO2015058533A1
Application number: PCT/CN2014/079457
Authority: WO
Inventors: 周栋树; 张迪煊; 陈卓伟; 韦晓成
Original assignee: 华为技术有限公司
Priority date: 2013-10-25
Filing date: 2014-06-09
Publication date: 2015-04-30
Also published as: CN103559159A

Abstract

An information processing method and an electronic device. The information processing method comprises: a master programmable logic device (PLD) is correspondingly connected to an N-number of data lines of a set of serial general purpose input/output (SGPIO) bus via an N-number of data pins and communicates with at least two slave PLDs via the one set of SGPIO, where N is a number of pins of either slave PLD that are connected with the SGPIO bus; and, the slave PLDs communicate with the master PLD via the one set of SGPIO bus.

Description

The present invention claims the priority of the Chinese Patent Application entitled "An Information Processing Method and Electronic Equipment", filed on October 25, 2013, with the Chinese Patent Office, Application No. 201310513375. The entire content of which is incorporated herein by reference.

The present invention relates to the field of electronic technologies, and in particular, to an information processing method and an electronic device. Background technique

With the continuous development of science and technology, electronic technology has also developed rapidly, and there are more and more types of electronic products. People are increasingly demanding electronic devices. For example, taking the server as an example, with the large-scale development of information technology, the processing capability of the server, which is an important component of the data center, is becoming higher and higher, and accordingly, the functions that the server can achieve are getting stronger and stronger. The specifications are also getting higher and higher, and of course the complexity is also increased. Specifically, the number of boards in a server and the number of programmable logic devices (PLDs) are increasing, and multiple boards and multiples are available. The connection between programmable logic devices is also becoming more complex.

At present, the data communication between the main PLD on the server board and multiple slave PLDs is usually based on the serial universal input/output SGPI O protocol, and the SGPI O protocol is a point-to-point full-duplex communication interface using 4-bit signal lines. The bit signal lines are the clock line CLOC load signal line i_c data input line and the data output line CATA0UT. The main PLD sends an LCAD signal every 12 clocks and data cycles, receives the LCAD signal from the PLD to complete the loading of 12-bit data, and the communication between the PLDs can realize the bidirectional transmission of 12-bit parallel data through the 4-bit serial interface. .

However, since the communication mode between the primary PLD and the secondary PLD is point-to-point, there is a shortage of the main PLD data pin resources in the prior art, and the main board where the primary PLD is located and the slave from which the PLD is located. The connector pins between the boards define complex technical issues. Summary of the invention

The embodiment of the present invention provides an information processing method and an electronic device, which are used to solve the problem that the main PLD data pin resource is existing in the prior art, and the connector between the main board where the main PLD is located and the slave board where the PLD is located. Pins define complex technical issues.

An embodiment of the present invention provides an information processing method, where the method includes: a main programmable logic device PLD is connected to N data lines of a serial universal input/output SGPI O bus through N data pins, and Communicating with at least two slave PLDs through the set of SGPI O buses, wherein N is a number of pins of the slave PLD connected to the SGPI O bus; and the slave PLD passes the set of SGPI O buses Communicate with the primary PLD.

Optionally, the primary PLD communicates with the at least two slave PLDs by using the set of SGPI O buses, including: the primary PLD sends the first information to the at least two slave PLDs by a clock cycle; After the PLD communicates with the at least two slave PLDs through the set of SGPI O buses, the method further includes: comparing, by the PLD, the destination address in the first information received by the PLD with an address corresponding to the PLD, and comparing the As a result, the first data in the first information is processed.

Optionally, the processing, by the PLD, the first data in the first information according to the comparison result, that: the destination address of the slave PLD in the first information received is the same as the address corresponding to the PLD. After the first data in the first information is saved, or the destination address of the PLD that is received by the first information is different from the address corresponding to the first information, the PLD discards the first information. First data.

Optionally, the communicating from the PLD to the primary PLD by using the set of SGPI O buses includes: the destination address of the slave PLD after receiving the first information is the same as the address corresponding to the PLD. And transmitting, after the Mth data loading period, the second information to the primary PLD, where M is a positive integer.

Optionally, when N is 4, the N data lines include a clock line, a loading signal line, a data input line and a data output line; a main clock pin of the main PLD is connected to the clock line, a main load pin is connected to the load signal line, and a main data input pin is connected to the data input line; a main data output pin is connected to the data output line; the slave clock pin of the slave PLD is connected to the clock line, the load pin is connected to the load signal line, and the data input pin is connected to the The data output lines are connected to and connected to the data input lines from the data output pins.

Optionally, after the slave PLD communicates with the master PLD through the set of SGPI O buses, the method further includes: stopping outputting the level through the slave data output pins.

Optionally, the slave data output pin is an open-drain output, and the data input line is connected to a pull-up resistor for pulling the data input line level; the slave PLD is passing the group After the SGPI O bus communicates with the main PLD, the method further includes: outputting a high level through the slave data output pin.

Another aspect of the present invention further provides an electronic device, including: a main programmable logic device PLD and at least two slave PLDs, wherein the master PLD passes through N data pins and a set of serial general purpose input/output SGPI O N data lines of the bus are connected, wherein N is a number of pins connected to the SGPI 0 bus from the PLD; the main PLD is used to pass the set of SGPI 0 buses and at least two slave PLDs Communicating; the slave PLD for communicating with the primary PLD over the set of SGPI 0 buses.

Optionally, the primary PLD is specifically configured to: send the first information to the at least two slave PLDs according to a clock cycle; the slave PLD is further configured to: use the received destination address in the first information The address corresponding to the self is compared, and the first data in the first information is processed according to the comparison result.

Optionally, the slave PLD is specifically configured to: after the destination address in the received first information is the same as the address corresponding to the first information, save the first data in the first information, or After the destination address in the first information is different from the address corresponding to the first information, the first data in the first information is discarded.

Optionally, the slave PLD is specifically configured to: a destination address in the received first information After the address corresponding to itself is the same, the second information is sent to the primary PLD in the subsequent Mth data loading period, where M is a positive integer.

Optionally, when N is 4, the N data lines include a clock line, a load signal line, a data input line, and a data output line; a main clock pin of the main PLD and the clock line Connected, a main load pin is connected to the load signal line, a main data input pin is connected to the data input line, and a main data output pin is connected to the data output line; the slave clock pin of the slave PLD is The clock lines are connected, connected to the load signal line from a load pin, connected to the data input line from a data input pin, and connected to the data output line from a data output pin.

Optionally, the slave PLD is further configured to stop outputting the level through the slave data output pin after communicating with the master PLD through the set of SGPI O buses.

Optionally, the electronic device further includes: a pull-up resistor for raising the level of the data input line; the slave data output pin is an open-drain output, and the slave PLD is further configured to: pass After the set of SGPI O buses communicate with the main PLD, a high level is output through the slave data output pin.

One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages.

Since the primary PLD is connected to the N data lines of a group of SGPI O buses through N data pins, and communicates with at least two slave PLDs through the set of SGPI O buses, where N is one of the slaves The number of pins connected to the SGPI O bus by the PLD, and the technical solution for communicating with the primary PLD from the PLD through the set of SGPI O buses, the communication mode between the primary PLD and the secondary PLD is no longer a point-to-point communication mode. Instead, they communicate with each other through a set of SGPI O buses. The main PLD only needs to be connected to a group of SGPI O buses through N data pins. The PLD only needs to be connected to the set of SGPI O buses through N data pins. The mutual communication between the primary PLD and the secondary PLD can be implemented, and the situation that the primary PLD needs to provide a multiple of the data pins from the PLD when the primary PLD is connected in a point-to-point manner from the PLD is avoided, so that the prior art is solved. The main PLD data pin resources are tight, and the main board where the main PLD is located and the slave board from which the PLD is located The connector pins between the two define complex technical problems, which saves the data pin resources of the main PLD, and simplifies the technical effect of defining the complexity of the main PLD and the connector pins between the PLDs. . DRAWINGS

1 is a schematic diagram showing a connection relationship between a primary PLD and a plurality of secondary PLDs in a server in the prior art;

2 is a flowchart of an information processing method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a connection relationship between a primary PLD and multiple secondary PLDs according to an embodiment of the present disclosure;

4 is a schematic diagram of a primary PLD transmitting first information to a PLD according to an embodiment of the present invention; FIG. 5 is a schematic diagram of a simulation waveform when a primary PLD is communicated with a PLD according to an embodiment of the present invention; The provided slave PLD is configured as an open-drain output from the output pin. detailed description

Before the technical solutions in the embodiments of the present invention are specifically described, in order to enable a person skilled in the art to better understand the technical solutions in the embodiments of the present invention, the following is a prior art solution in conjunction with FIG. And the technical problems existing in the prior art are described. details as follows:

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a connection relationship between a primary PLD and a plurality of secondary PLDs in a server in the prior art. As shown in FIG. 1, the communication mode between the primary PLD and the secondary PLD of the server is point-to-point. That is to say, the main PLD and the slave PLD are directly connected through the 4-bit signal line. Thus, in the case where one master PLD is connected to multiple slave PLDs, it is required to have four times of data pins on the master PLD from the number of PLDs, which easily causes data pin resources of the master PLD to be tight, and may even cause the master PLD. The number of data pins is not enough, and if one is from the board From the PLD, the number of connector pins between the slave board and the motherboard also needs to be four times the number of PLDs on the slave board, and the number of PLDs on each slave board is different, so the motherboard where the master PLD is located is caused. The definition of the connector pin between the slave board and the slave board where the PLD is located is complicated.

Therefore, in the prior art, there is a problem that the main PLD data pin resource is tight, and the motherboard where the main PLD is located and the connector pin between the slave boards where the PLD is located are complicated.

To this end, the embodiment of the present invention provides an information processing method and an electronic device, which are used to solve the problem that the main PLD data pin resource is existing in the prior art, and between the main board where the main PLD is located and the slave board where the PLD is located. The connector pins define complex technical issues.

The technical solution in the embodiment of the present invention is to solve the above technical problem. The general idea is as follows: The embodiment of the present invention provides an information processing method, which includes: a main programmable logic device PLD through a N data pin and a set of serial The N data lines of the general-purpose input/output SGPI O bus are connected and communicated with at least two slave PLDs through a set of SGPI 0 total M lines, where N is a number of pins connected from the PLD to the SGPI O bus; The PLD communicates with the primary PLD through a set of SGPI O buses.

It can be seen from the above that the primary PLD is connected to the N data lines of a group of SGPI O buses through N data pins, and communicates with at least two slave PLDs through a set of SGPI O buses, where N For a number of pins connected from the PLD to the SGPI O bus, and a technical solution for the PLD to communicate with the primary PLD through the set of SGPI O buses, the communication between the primary PLD and the secondary PLD is no longer a point-to-point communication method. Instead, they communicate with each other through a set of SGPI O buses. The main PLD only needs to be connected to a group of SGPI O buses through N data pins. The PLD only needs to be connected to the set of SGPI O buses through N data pins. That is, the mutual communication between the primary PLD and the secondary PLD can be realized, and the situation that the primary PLD needs to provide the data pin from the multiple of the PLD when the primary PLD and the PLD are connected in a point-to-point manner is avoided, so the prior art is solved. The main PLD data pin resources are tight, and the motherboards where the main PLD is located and the connector pins between the slave boards where the PLDs are located define complex technical problems, which saves the data pin resources of the main PLD. And where the main motherboard PLD PLD where the connector from between the plates The pin defines the technical effect of the complexity.

In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the drawings and specific embodiments.

An embodiment of the present invention provides an information processing method. Referring to FIG. 2, FIG. 2 is a flowchart of an information processing method according to an embodiment of the present invention. As shown in FIG. 2, the method includes:

51: The main programmable logic device PLD is connected to the N data lines of a set of serial general-purpose input/output SGPI O buses through N data pins, and communicates with at least two slave PLDs through a set of SGPI O buses. Where N is the number of pins connected from the PLD to the SGPI O bus;

52: The PLD communicates with the primary PLD through the set of SGPI O buses.

In this embodiment, the PLD may be a CPLD (Conpl ex Progranmabl e Logi c Devi ce, Complex Programmable Logic Device) or an FP (Fiel d - Progranmabl e Gat e Array). Make restrictions.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of a connection relationship between a primary PLD and a plurality of secondary PLDs according to an embodiment of the present invention. As shown in FIG. 3 , the primary PLD passes through four data pins and a set of SGPI O buses. The four data lines are connected, and the PLD is connected to the four data lines of the set of SGPI 0 buses through four data pins, and the number of data pins connected to the set of SGPI O buses by the main PLD and a slave PLD and The number of data pins connected to the SGPI O bus is equal, that is, the main PLD only needs to be connected to the data line in the SGPI O bus through four data pins, so that communication with the PLD connected to the SGPI O bus can be realized. The four data lines of the set of SGPI O buses include a clock line, a load signal line, a data input line and a data output line. The main clock pin of the main PLD is connected to the clock line, and the main load pin and the main The load signal line is connected, the main data input pin is connected to the data input line, the main data output pin is connected to the data output line, the slave clock pin of the PLD is connected to the clock line, the load pin is connected to the load signal line, and the slave number Input pin is connected to the data output line connected to the data from the data output pins of the input line.

Of course, in practical applications, by the introduction of this embodiment, those skilled in the art can increase or decrease the number of data lines of the SGPI O bus according to actual conditions, and do not limit the number of data lines of the SGPI O bus. System. In the following part, the description will be made of the case where the main PLD is connected to four data lines of a group of SGPI 0 buses through four data pins. It should be noted that the main PLD introduced in this embodiment passes. The case of four data pins and four data lines of a group of SGPI 0 buses is for the sake of example only, and is not intended to limit the technical solution in the embodiments of the present invention.

As shown in FIG. 3, in this embodiment, only the main PLD needs to pass the main clock pin, the main load pin, the main data input pin, and the main data output pin and a group of SGPIs compared with the prior art. The O bus is connected, that is, the mutual communication between the main PLD and the slave PLD can be realized, and the main PLD as shown in FIG. 1 needs 16 data pins to realize communication with and from the PLD, so the main cause is solved. When the communication mode between the PLD and the slave PLD is point-to-point communication, the main PLD needs to have technical problems of data pin resource shortage caused by multiple PLD connections at the same time, and realizes the technical effect of saving the data pin resource of the main PLD.

At the same time, the slave PLD is connected to a group of SGPI O buses from the clock pin, from the load pin, from the data input pin, and from the data output pin, regardless of the number of PLDs from the board, between the motherboard and the slave board. The definition of the connector pins is consistent with the definition of a set of SGPI O buses, so the technical problems of the connector pins defined between the prior art boards and the respective boards are solved, and the motherboard in which the main PLD is simplified is realized. The technical effect of the complexity is defined by the connector pins between the slave boards from which the PLD is located.

In step S1, the main programmable logic device PLD communicates with at least two slave PLDs through a set of SGPI O buses. Specifically, the master PLD may send the first information to at least two slave PLDs by clock cycle.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of the primary PLD sending the first information to the PLD according to the embodiment of the present invention. As shown in FIG. 4, the primary PLD sends the data output line of the SGPUI bus to all the PLDs according to the clock cycle. A message, the first information including the destination address and the first data. In the specific implementation process, the data bit number of the first information, the data bit number of the destination address, and the data bit number of the first data may be selected according to actual conditions, for example, the first information may be 16-bit data, the data of the destination address. The number of bits can be 4 bits of data, and the first number of bits can be 12 bits of data. In practical applications, if the number of PLDs is large, and the 4-bit data is not enough to allocate all addresses from the PLD, the number of bits of the destination address can be increased to meet the requirement for all the addresses allocated from the PLD, so that each slave PLD All can be assigned a corresponding address, of course, after increasing the number of bits of the destination address, the number of bits of the first data can be reduced or the number of bits of the first information can be increased, and then the time interval for loading the load signal of the main load pin is adjusted accordingly. Yes, of course, through the introduction of this embodiment, the person skilled in the art can also adjust the number of bits of the first data according to actual conditions, for example, adjust the first information to 18 bits or 19 bits, etc., Let me repeat.

As shown in FIG. 4, the main PLD sends the first information to all the slave PLDs through the data output line according to the clock cycle. In the first information, the first 4 bits of data are the destination address, and the last 12 bits are the first data, and When the information is sent, the loading signal is sent through the loading signal line, and the loading of the first information is completed after the PLD receives the loading signal. In practical applications, from the time the load signal line issues the first data load signal to the second data load signal, it can be called a data load cycle.

After receiving the first information, the PLD compares the destination address in the first information with its own address, and processes the first data in the first information according to the comparison result, for example, in the first information. The destination address is 0001. For example, the corresponding address assigned by the first PLD is 0001. After receiving the first information from the PLD, the first destination information 0001 in the first information is compared with the corresponding address 0001. If the addresses are the same, it indicates that the destination of the first information is the first slave PLD, and the first slave PLD saves the first data in the first information, thereby implementing communication between the master PLD and the slave PLD.

After receiving the first information from the PLD, such as the second slave PLCL, the third slave PLD, etc., the destination address 0001 in the first information is compared with the address corresponding to itself, because the destination address and the second address in the first information The address corresponding to the PLD itself from the PLCL third is different, so the second slave PLCL third slave PLD and the like will discard the first data in the first information.

After the destination address in the first information received by the PLD is the same as the address corresponding to itself, the second information is sent to the primary PLD in the subsequent M data loading period, thereby implementing the slave PLD and the master. The communication between the PLDs is a preset positive integer, for example, 1, 2, 3, etc., and is not limited herein. Please refer to FIG. 5. FIG. 5 is a simulation waveform diagram of the main PLD and the slave PLD according to an embodiment of the present invention. As shown in FIG. 5, the main PLD is continuously sent from the PLD through a data output line of the SGPI 0 bus. Information, and the PLD distinguishes according to the address, and the data input line of a group of SGPI 0 buses is used to transmit information to the main PLD, thereby realizing the continuous transmission of waveforms on the entire set of SGPI 0 buses.

In the specific implementation process, in order to avoid a certain slave PLD transmitting data, other slave PLDs will pull the data input line of a group of SGPI 0 bus, for example, keep the data input line high, and then cause Data transmission is abnormal. It can be adopted by configuring the slave data output pin from the PLD to a high-impedance state, for example, sending a second message from the PLD to the master PLD, that is, from the PLD through a group of SGPI 0 buses and the master PLD. After communication, stop the output level from the slave data output pin of the PLD, that is, after the PLD communicates with the master PLD, the slave data output pin of the PLD is configured to a high-impedance state, thereby ensuring that the slave PLD is not The data input line will be pulled.

In addition to the above-described way of configuring the slave data output pin from the PLD to a high-impedance state to ensure that the data input line is not pulled from the PLD, the embodiment of the present invention also provides a slave output pin through the slave PLD. The way the open-drain output (CD output) is configured ensures that the data input line is not pulled from the PLD.

Please refer to FIG. 6 again. FIG. 6 is a schematic diagram of the slave PLD from the output pin configured as an open-drain output according to an embodiment of the present invention. As shown in FIG. 6, the PLD is configured as an open-drain output, and is in the main A pull-up resistor is added to the main input pin of the PLD. One end of the pull-up resistor is connected to the pull-up voltage, and the other end of the pull-up resistor is connected to the data input line. Of course, the main input pin can also be configured inside the main PLD. Pull up to achieve line and logic.

In this way, when the data input line of a group of SGPI O bus is in a high state, the accuracy of any information sent from the PLD to the main PLD can be ensured, for example, the PLD outputs a high level from the data output pin through the PLD. Then the entire data input line is in a high state, and the main PLD receives the high level information through the main data input pin, and the output from the PLD through the data output pin is low. At the level, since the data output pin is an open-drain output, the entire data input line is pulled low, and the main PLD receives low-level information through the main data input pin, thereby realizing the guarantee of arbitrary The effect of the PLD on the accuracy of the information generated by the primary PLD.

Of course, through the introduction of this embodiment, those skilled in the art can select other suitable manners to ensure that the information is normally sent from the PLD to the primary PLD to meet the actual situation, and will not be described here. .

Based on the same inventive concept, an embodiment of the present invention further provides an electronic device including: a main programmable logic device PLD and at least two slave PLDs, a main PLD through a data pin and a set of serial general purpose input/output SGPI O The root data lines of the bus are connected, wherein Ν is a number of pins connected from the PLD to the SGPI O bus; the main PLD is used to communicate with at least two slave PLDs through a set of SGPI O buses; Communicates with the primary PLD over a set of SGPI O buses.

In a specific implementation process, the primary PLD is specifically configured to: send the first information to the at least two slave PLDs according to a clock cycle; and the slave PLD is further configured to: compare the destination address in the received first information with the address corresponding to the first PLD. And processing the first data in the first information according to the comparison result.

In a specific implementation process, the PLD is specifically configured to: after the destination address in the received first information is the same as the address corresponding to the first information, save the first data in the first information, or in the first information received. After the destination address is different from the address corresponding to itself, the first data in the first information is discarded.

In the specific implementation process, the PLD is specifically configured to: after the destination address in the received first information is the same as the address corresponding to itself, send the second information to the primary PLD in the subsequent M data loading period, where M is A positive integer.

In a specific implementation process, when N is 4, the N data lines include a clock line, a load signal line, a data input line, and a data output line; the main clock pin of the main PLD is connected to the clock line, and the main load is The pin is connected to the load signal line, the main data input pin is connected to the data input line, the main data output pin is connected to the data output line; the main clock pin of the PLD is connected to the clock line, the load pin and the load signal line are loaded. Connected, connected from the data input pin to the data input line, from the data input The output pin is connected to the data output line.

In the implementation process, the slave PLD is also used to stop the output level from the data output pin after communicating with the master PLD through a set of SGPI 0 buses.

In a specific implementation process, the electronic device further includes: a pull-up resistor for pulling the data input line level; the data output pin is an open-drain output, and the slave PLD is further used to: pass through a group of SGPI O bus After communicating with the main PLD, a high level is output from the data output pin.

The electronic device in this embodiment and the information processing method in the foregoing embodiment are based on two aspects under the same inventive concept. The implementation process of the method has been described in detail above, so those skilled in the art can refer to the foregoing description. The structure and implementation process of the electronic device in this embodiment are clearly understood. For the sake of brevity of the description, details are not described herein again.

The technical solution in the foregoing embodiments of the present invention has at least the following technical effects or advantages: The primary PLD is connected to the N data lines of a group of SGPI O buses through N data pins, and passes through a group of SGPI Os. The bus communicates with at least two slave PLDs, where N is a number of pins connected from the PLD to the SGPI O bus, and a technical solution for communicating with the master PLD from the PLD through the set of SGPI O buses, the master PLD and the slave PLD The communication mode is no longer a point-to-point communication method, but communicates with each other through a set of SGPI O buses. The main PLD only needs to be connected to a group of SGPI O buses through N data pins, and only N through the PLD. The data pin is connected to the set of SGPI O buses, which can realize mutual communication between the primary PLD and the secondary PLD, and avoids the need for the primary PLD to provide a multiple of the number of PLDs when the primary PLD and the secondary PLD are connected in a point-to-point manner. The situation of the data pin, so that the resource shortage of the main PLD data pin existing in the prior art is solved, and the main board where the main PLD is located and the slave board where the PLD is located are Connector pin definitions complicated technical problem to achieve a primary resource saving data pins of PLD, PLD simplifies board where the main and the PLD where technical complexity results from the connector pins defined between the plates.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Therefore, the present invention can be implemented in an entirely hardware embodiment, fully software implemented For example, or in combination with an embodiment of software and hardware aspects. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, O ROV1 optical storage, etc.) containing computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, devices (system λ and computer program products) according to embodiments of the invention. It is understood that each of the flowcharts and/or block diagrams can be implemented by computer program instructions. / or a combination of blocks and flow diagrams and/or blocks in a flowchart and/or block diagram. Processors for providing such computer program instructions to a general purpose computer, special purpose computer, embedded processor or other programmable data processing device To generate a machine such that instructions executed by a processor of a computer or other programmable data processing device generate functions for implementing a process in a flow or a flow and/or a block diagram in a block or blocks. s installation.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and the modifications

Claims

Rights request

1. An information processing method, characterized in that the method includes:

The master programmable logic device PLD is connected to N data lines of a set of serial general-purpose input/output SGPI 0 buses through N data pins, and communicates with at least two slave PLDs through the set of SGPI 0 buses, Where N is the number of pins connected to the SGPI 0 bus of a slave PLD; and

The slave PLD communicates with the master PLD through the set of SGPI 0 buses.

2. The method of claim 1, wherein the master PLD communicates with at least two slave PLDs through the set of SGPI 0 buses, including:

The master PLD sends the first information to the at least two slave PLDs in a clock cycle; after the master PLD communicates with the at least two slave PLDs through the set of SGPI 0 buses, it also includes:

The slave PLD compares the destination address in the received first information with its corresponding address, and processes the first data in the first information according to the comparison result.

3. The method of claim 2, wherein the slave PLD processes the first data in the first information according to the comparison result, including:

After the destination address in the received first information is the same as its corresponding address, the slave PLD saves the first data in the first information; or

After the destination address in the received first information is different from its corresponding address, the slave PLD discards the first data in the first information.

4. The method of claim 3, wherein the slave PLD communicates with the master PLD through the set of SGPI 0 buses, including:

After the destination address in the received first information is the same as its corresponding address, the slave PLD sends the second information to the master PLD in the Mth data loading cycle, where M is a positive integer.

5. The method of claim 1, wherein when N is 4, the N data lines include a clock line, a loading signal line, a data input line and a data output line;

The main clock pin of the main PLD is connected to the clock line, the main loading pin is connected to the loading signal line, the main data input pin is connected to the data input line, and the main data output pin is connected to the data The output lines are connected;

The slave clock pin of the slave PLD is connected to the clock line, the slave load pin is connected to the load signal line, the slave data input pin is connected to the data output line, the slave data output pin is connected to the data The input lines are connected.

6. The method of claim 5, wherein after the slave PLD communicates with the master PLD through the set of SGPI 0 buses, it further includes:

Stops the output level via the slave data output pin.

7. The method of claim 5, wherein the slave data output pin is an open-drain output, and the data input line is connected to a pull-up resistor for pulling up the level of the data input line. ;

After the slave PLD communicates with the master PLD through the set of SGPIO buses, it further includes: outputting a high level through the slave data output pin.

8. An electronic device, characterized in that it includes: a master programmable logic device PLD and at least two slave PLDs. The master PLD communicates with a set of serial general-purpose input/output SGPIO buses through N data pins. The data lines are connected correspondingly, where N is the number of pins connected to the slave PLD and the SGPI O bus;

The master PLD is used to communicate with at least two slave PLDs through the set of SGPIO buses; and the slave PLD is used to communicate with the master PLD through the set of SGPIO buses.

9. The electronic device according to claim 8, wherein the master PLD is specifically configured to: send the first information to the at least two slave PLDs in a clock cycle;

The slave PLD is also used for:

Compare the destination address in the received first information with its corresponding address, and The first data in the first information is processed according to the comparison result.

10. The electronic device according to claim 9, wherein the slave PLD is specifically used for:

After the destination address in the received first information is the same as the address corresponding to itself, the first data in the first information is saved, or the destination address in the received first information corresponds to itself. After the addresses are different, the first data in the first information is discarded.

11. The electronic device according to claim 10, wherein the slave PLD is specifically used for:

After the destination address in the received first information is the same as its corresponding address, the second information is sent to the main PLD in the Mth data loading cycle, where M is a positive integer.

12. The electronic device according to claim 8, wherein when N is 4, the N data lines include a clock line, a loading signal line, a data input line and a data output line; The main clock pin of the main PLD is connected to the clock line, the main load pin is connected to the load signal line, the main data input pin is connected to the data input line, the main data output pin is connected to the data output line connected; connected

The main clock pin of the slave PLD is connected to the clock line, the slave load pin is connected to the load signal line, the slave data input pin is connected to the data input line, the slave data output pin is connected to the data The output lines are connected.

13. The electronic device of claim 12, wherein the slave PLD is further configured to: after communicating with the master PLD through the set of SGPI 0 buses, stop passing the slave data output pipe. pin output level.

14. The electronic device according to claim 12, wherein the electronic device further includes: a pull-up resistor for pulling up the level of the data input line;

The slave data output pin is an open-drain output, and the slave is used to: after communicating with the master PL line through the group of SGPI Qg, lines, output the slave data through the slave data output pin. level.