CN102880571A - Synchronous serial connection device - Google Patents
Synchronous serial connection device Download PDFInfo
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- CN102880571A CN102880571A CN2012102925402A CN201210292540A CN102880571A CN 102880571 A CN102880571 A CN 102880571A CN 2012102925402 A CN2012102925402 A CN 2012102925402A CN 201210292540 A CN201210292540 A CN 201210292540A CN 102880571 A CN102880571 A CN 102880571A
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Abstract
The invention provides a synchronous serial connection device, which comprises a first logic device, a first serial connector, a second logic device and a second serial connector, wherein the first serial connector is in butt joint with the second serial connector; and the first logic device is used for converting output signals of a plurality of pins on a parallel input output (IO) physical interface into a data frame according to a predetermined resolution protocol, sending the data frame to the second serial connector through the first serial connector, resolving the data frame from the second serial connector into input signals of a plurality of pins on the parallel IO physical interface according to the predetermined resolution protocol, and defining the data frame according to a data frame synchronization signal which is generated by the first logic device or the second logic device. By adoption of the synchronous serial connection device, the parallel IO physical interface of a plurality of IO signal lines can be converted into a serial interface by using a small number of pins.
Description
Technical field
The present invention relates to the electronic equipment internal signal transmission technology, relate in particular to a kind of synchronous serial coupling arrangement.
Background technology
In electronic equipment, especially mainboard and backboard can have been used in a large number in the network equipment and the memory device.Need a lot of parallel IO mouths to carry out the exchange of status information between mainboard and backboard, have the connector of a lot of pins to connect with regard to needing mainboard to be connected with backboard like this.Yet such scheme cost is high, and the exchange that needs a large amount of connector of welding to solve the status information between mainboard and backboard has increased the connector cost and taken a large amount of device spaces, is unfavorable for the designer trends of the complicated and miniature compact of electronic equipment.
The use serial transmission can reduce the number of pins of connector, such as the typically transformation of hard disk from parallel interface to serial line interface.SPI in the prior art (Serial Peripheral Interface--Serial Peripheral Interface (SPI)) bus system is a kind of synchronous serial Peripheral Interface, it can make MCU(Micro Control Unit, micro-control unit) communicate with exchange message with serial mode with various peripherals.This interface uses 4 lines: the slave of serial time clock line (SCLK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and Low level effective is selected line SS.The SPI interface is actually two simple shift registers at internal hardware, and the data of transmission are 8.Mainly there is following shortcoming in such scheme: at first, the data of SPI transmission are 8, can not represent the mainboard of a large amount of (tens and even up to a hundred individual) and the IO state between backboard.Secondly, each data and the IO pin of SPI serial are mapped, so flexibility ratio is lower; In addition, the data access mode of SPI interface is the address date mode, and data transmit does not carry out continuously, state that can't real-time continuous reflection I/O Parallel mouth; At last, the realization logic of SPI interface is complicated, take a large amount of logical device resources and decipher.
Summary of the invention
In view of this, the invention provides a kind of synchronous serial coupling arrangement, comprise the first logical device and the first serial connector that are positioned on the first circuit board, and be positioned at the second logical device and the second serial connector on the second circuit board of first circuit board opposite end; Wherein
Described the first serial connector docks with the second serial connector, and described the first serial connector is connected in the front end physical interface of the first logical device, and the back-end physical interface of described the first logical device is connected in the I/O Parallel physical interface on the first circuit board;
Described the first logical device is used for according to predetermined analysis protocol the output signal of some pins on the I/O Parallel physical interface being converted to a Frame, and sends to described the second serial connector by the first serial connector; And to be used for according to predetermined analysis protocol will be the input signal of some pins on the described I/O Parallel physical interface from the data frame analyzing of the second serial connector;
Described the first logical device is further used for according to the data-frame sync signal that self produces or the second logical device produces and the data-frame sync signal of transmission defines Frame.。
The present invention is by using a small amount of pin to realize that the also IO physical interface of a large amount of IO signal wires is to the conversion of serial line interface, can be so that connector be accomplished very miniaturization, because serial protocol design of the present invention is very succinct, therefore can realize with this relatively simple logical device of CPLD fully.
Description of drawings
Fig. 1 is synchronous serial coupling arrangement frame diagram in one embodiment of the present invention.
Fig. 2 is the signal schematic representation of transceiving data process in one embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the invention is described in detail.Please refer to Fig. 1, a kind of synchronous serial coupling arrangement of the present invention, comprise the first logical device and the first serial connector that are positioned on the first circuit board, and be positioned at the second logical device and the second serial connector on the second circuit board of first circuit board opposite end.Below take first circuit board as electronic equipment the mainboard of (such as the network storage equipment), second circuit board is that the backboard of electronic equipment is example.The first serial connector of mainboard docks with the second serial connector of backboard.Described the first serial connector is connected in the front end physical interface of the first logical device, and the back-end physical interface of described the first logical device is connected in the I/O Parallel physical interface on the mainboard; Described the second serial connector is connected in the front end physical interface of the second logical device, and the back-end physical interface of described the second logical device is connected in the I/O Parallel physical interface on the backboard.
Link to each other by 5 signal wires between first and second serial connector; Wherein CLK is the clock signal that backboard sends to mainboard, and the first logical device on the mainboard can be with this clock signal as the reference clock of self working.Frame is the data-frame sync signal that backboard sends to mainboard, and the first logical device defines the end of the Frame that the second logical device sends on the backboard according to Frame.Mainboard receives and mainboard is sent as two two-way data frame transfer passages.To be the first logical device send to the preparation commencing signal of the second logical device by the Ready signal pin to mainboard Ready, and the expression mainboard prepares to begin to transmit the active data frame.It should be noted that CLK and Frame signal also can send to the second logical device by the first logical device, this depends on developer's actual demand.Same reason mainboard Ready can become the backboard Ready that the second logical device sends to the first logical device.
Please refer to Fig. 2, in the present invention, Frame is followed predetermined serial protocol customization, and its size also is predefined, can comprise N data bit, each data bit can correspond to the state of an IO signal wire in N the IO signal wire on the I/O Parallel physical interface.By such setting, the state of a plurality of signal wires of I/O Parallel physical interface on mainboard or the backboard (can be understood as 1 or 0) can be placed in the Frame and be sent to the opposite end, design has avoided prior art to use 8 complex logic design problems that data bit causes like this, because the signal wire quantity on the I/O Parallel physical interface may be considerably beyond 8, and may not be 8 integral multiple, therefore the good working condition of I/O Parallel physical interface to be obtained, the logic development design of very complex need to be carried out on standard agreement bases such as existing SPI.
It may be consistent that backboard sends to the length that mainboard and mainboard send to the Frame of backboard.Yet consider that in actual applications it many times be not full symmetric.Such as the first logical device need to send the Frame that comprises N data bit, and the second logical device need to send the Frame that comprises M data bit, and N might be different from M.Suppose that N is that 80, M is 100, in the present embodiment, the Frame of both sides of the present invention receives and finishes so synchronously:
Step 10, the Frame signal offers the first logical device (sending the short side of Frame) by the second logical device (sending the long side of Frame).
Step 20, when the first logical device is ready for sending data, it sends first the Ready signal (in the present embodiment, the Ready signal is the equal of the commencing signal that both sides' log-on data sends), then generate a forward data frame according to predetermined serial protocol and represent 80 signal line states on the I/O Parallel physical interface on the mainboard, this forward data frame (80 data bit) is sent to the second logical device.
Step 30, the second logical device represents 100 signal line states on the I/O Parallel physical interface on the backboard according to predetermined reverse data frame of serial protocol generation after receiving the Ready signal at once, then sends first reverse data frame (100 data bit) to the first logical device.
Step 40, the second logical device send after the reverse data frame, send a Frame signal to the first logical device; The second logical device just can begin to send second reverse data frame after sending the Frame signal; The Frame signal is exactly in other words rhythm of its interval that sends Frame for the second logical device,
Step 50 when the second logical device sends the Frame signal to the first logical device, is resolved the forward data frame of the first logical device according to predetermined serial protocol.According to predetermined serial protocol definition; the forward data frame of the first logical device only has 80; therefore can send in theory during this period of time 100 data bit from sending the Ready signal to sending first Frame signal; therefore the second logical device may receive 100 data bit (usually can be placed in the buffer memory); but 80 data bit that the second logical device only intercepts (behind the Frame rising edge) behind the Frame signal according to predetermined serial protocol are as valid data, and 20 data bit in back all abandon.Then the second logical device becomes it with 80 IO signal line states according to predetermined serial protocol and sends to by the back-end physical interface on 80 signal wires of the I/O Parallel physical interface on the backboard, and wherein which data bit which IO signal wire corresponds to and can freely define.Please refer to a simple examples among Fig. 2, because the data bit An that the first logical device sends is before the Frame signal begins, so the second logical device of backboard can discard it, only keeps A0, A1, A2, A3, A4; Same reason, the Bn that the second logical device sends also can be discarded by the first logical device.
Step 60, the first logical device determines that the reverse data frame finishes after receiving the Frame signal, can with before the data of 100 data bit of buffer memory read out as a Frame, then according to predetermined serial protocol it is become with 100 IO signal line states and sends on 100 signal wires of the I/O Parallel physical interface on the mainboard by the back-end physical interface.
In addition, between the first and second logical device except transmitting the IO signal, can also transmit the control signal of Bearer Control order, state such as the status lamp on the control current electronic device panel, with the command word of different implications represent the state of status lamp, such as, use 2'b00 to represent to go out, 2'b01 represents long bright, 2'b 10 expression fixed frequency flickers etc.
The present invention is by using a small amount of pin (such as 5) to realize that the I/O Parallel physical interface of a large amount of IO signal wires is to the conversion of serial line interface, can be so that connector be accomplished miniaturization, and because number of pin is considerably less, the number of pins of existing a lot of AN connector all surpasses 5, therefore these connector major parts can be used in the present invention, do not need to do variation physically, only need to develop above-mentioned more succinct logic function.Because serial protocol design of the present invention is very succinct, therefore can realize with this relatively simple logical device of CPLD fully.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. a synchronous serial coupling arrangement comprises the first logical device and the first serial connector that are positioned on the first circuit board, and is positioned at the second logical device and the second serial connector on the second circuit board of first circuit board opposite end; Wherein
Described the first serial connector docks with the second serial connector, and described the first serial connector is connected in the front end physical interface of the first logical device, and the back-end physical interface of described the first logical device is connected in the I/O Parallel physical interface on the first circuit board;
Described the first logical device is used for according to predetermined analysis protocol the output signal of some pins on the I/O Parallel physical interface being converted to a Frame, and sends to described the second serial connector by the first serial connector; And to be used for according to predetermined analysis protocol will be the input signal of some pins on the described I/O Parallel physical interface from the data frame analyzing of the second serial connector;
Described the first logical device is further used for according to the data-frame sync signal that self produces or the second logical device produces and the data-frame sync signal of transmission defines Frame.
2. synchronous serial coupling arrangement as claimed in claim 1, it is characterized in that, described the second logical device is used for according to predetermined analysis protocol the output signal of some pins on the I/O Parallel physical interface on the second circuit board being converted to a Frame, and sends to described the first serial connector by the second serial connector; And to be used for according to predetermined analysis protocol will be the input signal of some pins on the described I/O Parallel physical interface from the data frame analyzing of the first serial connector;
The data-frame sync signal that wherein said the second logical device produces and sends according to the first logical device or the data-frame sync signal that self produces define Frame.
3. synchronous serial coupling arrangement as claimed in claim 1 is characterized in that, the Frame length that described the first logical device sends is different from the Frame length that the second logical device sends.
4. synchronous serial coupling arrangement as claimed in claim 1 is characterized in that, the Frame length that the Frame length that the first or second logical device of generation data-frame sync signal sends sends greater than the opposite end logical device.
5. synchronous serial coupling arrangement as claimed in claim 1 is characterized in that, described first and second serial connector includes two Frame transmission pin, synchronizing signal pin and clock signal pins; Wherein said the first logical device is further used for the second logical device on the second circuit board and sends clock signal as this second logical device reference clock.
6. synchronous serial coupling arrangement as claimed in claim 1 is characterized in that the described first or second logical device is CPLD.
7. synchronous serial coupling arrangement as claimed in claim 1, it is characterized in that, it is characterized in that, described first and second serial connector all further comprises the Ready signal pin, and described the first logical device is used for sending the Ready signal by the Ready signal pin before being ready for sending Frame.
8. synchronous serial coupling arrangement as claimed in claim 1 is characterized in that, described the first serial connector is less than or equal to 5 by the number of pin that the first logical device uses.
9. such as the described synchronous serial coupling arrangement of claim 1-8, it is characterized in that the described Frame that defines comprises: be discarded in Frame signal data bit before.
10. such as the described synchronous serial coupling arrangement of claim 1-8, wherein said input signal comprises control signal, is used for the status lamp on this device place electronic equipment of control.
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| CN2012102925402A CN102880571A (en) | 2012-08-16 | 2012-08-16 | Synchronous serial connection device |
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| CN2012102925402A CN102880571A (en) | 2012-08-16 | 2012-08-16 | Synchronous serial connection device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559159A (en) * | 2013-10-25 | 2014-02-05 | 华为技术有限公司 | Information processing method and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040023522A1 (en) * | 2002-08-01 | 2004-02-05 | Cheng-Chun Chang | Intelligent universal connector |
| CN102567587A (en) * | 2012-01-04 | 2012-07-11 | 青岛海信信芯科技有限公司 | FPGA (field programmable gate array) interconnection method and device utilizing same |
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- 2012-08-16 CN CN2012102925402A patent/CN102880571A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040023522A1 (en) * | 2002-08-01 | 2004-02-05 | Cheng-Chun Chang | Intelligent universal connector |
| CN102567587A (en) * | 2012-01-04 | 2012-07-11 | 青岛海信信芯科技有限公司 | FPGA (field programmable gate array) interconnection method and device utilizing same |
Non-Patent Citations (1)
| Title |
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| 雷印胜等: "《微型计算机接口技术》", 31 May 2011, article "可编程串行通信控制器8251A", pages: 181-184 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559159A (en) * | 2013-10-25 | 2014-02-05 | 华为技术有限公司 | Information processing method and electronic device |
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Application publication date: 20130116 |