CN101546286B - Method and device for logic analysis of high-speed serial bus - Google Patents
Method and device for logic analysis of high-speed serial bus Download PDFInfo
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Abstract
The invention provides a method and a device for the logic analysis of a high-speed serial bus. The method comprises the following steps: receiving a bus signal of the high-speed serial bus; copying the bus signal with a signal shunting module to generate a first signal and a second signal; feeding the first signal back to the high-speed serial bus; and resolving the second signal to acquire parallel data. Through the shunting processing of the signal in the high-speed serial bus, the use of the one path of shunt signal obtain in logic analysis through resolution, and the feedback of the other path of shunt signal to the high-speed serial bus, the method can analyze data transmitted in the high-speed serial bus under a condition of not influencing the data transmission of the high-speed serial bus.
Description
Technical field
The present invention relates to a kind of high-speed serial bus analytics and device, belong to data communication technology field.
Background technology
The interconnected local bus that often adopts between CPU (Central Process Unit is called for short CPU) and the peripheral components thereof is like peripheral component interconnection (Peripheral ComponentInterconnect is called for short PCI) local bus.Along with development of technology, increasingly high to the data rate requirement of local bus, so high-speed serial bus is born thereupon.The high-speed serial bus that occurs at present is varied, and nonstandardized technique is arranged, and also has standardized; Peripheral component high-speed interconnect standard (PCI Express for example; Be called for short PCIE) universal serial bus, PCIE is a kind of high-speed serial bus standard, these high-speed serial bus often have following characteristics:
(1) point-to-point connection is adopted in the connection of bus between device.
(2) only form with the reception data bus by sending data bus, and do not have synchronous clock bus and other control bus, the band inner control is adopted in the control and management of bus.So-called band inner control is meant the method that managing control information and data message use unified physical channel to transmit; The band outer control is opposite with the band inner control, is meant through the different physical channel independence transfer management control informations and the method for data message.
(3) the synchronous clock bus is mixed in the data bus, extracts synchronous clock at receiving end by the clock recovery device in the receiving trap.
(4) owing to be not with the outer control bus; Needing to adopt band inner control agreement to carry out total line traffic control, in order to distinguish band inner control command word and the data of being transmitted, need (can be 4-bit (bit to control command word waiting for transmission and data; Be called for short b) data or 8-bit data) carry out extended coding; So that distinguish data and control command word, like the 8b/10b coding of PCI Express, the character code that is about to 8bit is converted into the character code of 10bit through the mechanism of mapping.The effect of 8b/10b coding is that 0 and 1 number is reached unanimity basically, reaches the direct current equilibrium, and assurance has enough hopping edges so that the clock recovery device of receiver can recover synchronous clock.
(5) in order to reduce the noise and the electromagnetic interference (EMI) of high-speed bus transmission, often carry out data transmission with the differential mode transmission manner.Difference mode signal is meant equal and opposite in direction, a pair of signal in the opposite direction, and the transmission of difference mode signal is called the differential mode transmission.
(6) in order to reduce the required energy of bus transfer; Except each word waiting for transmission being carried out the 8b/10b coding; Also in transmitter, before the 8b/10b coding, carry out the scrambler operation earlier; Promptly adopt special data sequence (like pseudo-random sequence) and data character code to be sent to multiply each other; Carry out conversion to sent the data character code, do having guaranteed can not repeat for a long time on the transmission signal line to occur a certain specific sequence string like this, a certain space double vibrations electric flux and magnetic energy externally send on the transmission signal line thereby reduce.Adopt corresponding descrambler to parse data at receiving end.
Because the data of on universal serial bus, transmitting have been passed through aforesaid technical finesse, are not common binary-coded data sequences, make people directly to observe the data sequence of being transmitted on the high-speed serial bus through oscillograph.When people carry out system debug, test, transmission performance analysis or efficiency analysis, only use oscillograph can't accomplish.
The bus data analysis often is very important in system debug test and system effectiveness analysis, for example: the system delay analysis, performance evaluation, fault analysis, or even device issue track location etc.
In order to accomplish the purpose of system debug test and systematic analysis, the logic analyser that people are accustomed to adopting professional equipment producer to provide is analyzed the data transmission on the bus.Its method of testing is as shown in Figure 1.Equipment 001 is PCIE root node equipment (PCIE Root Complex; Be called for short PCIE RC); Equipment 003 is PCIE endpoint device (PCIE Endpoint); Equipment 001 and equipment 003 send bus 002 and PCI Express through PCI Express to receive bus 004 interconnected, and 003 and 004 closes and is called universal serial bus, and universal serial bus is of coupled connections through ac coupling capacitor 007.Proving installation logic analyser 006 uses miniature connecting line type A (SubMiniature version A; Being called for short SMA) test cable 005 is connected to PCI Express and sends and receive bus and obtain the data sequence on the transfer bus, and logic analyser is data that can Direct observation with the decoded data sequence that obtains.Ac coupling capacitor is can the isolated DC common mode electrical level, and the energy of position signal that guarantees to change can expedite capacitor in the two ends transmission; SMA test cable is a kind of high speed signal test that is specifically designed to, and connects the cable of signal to be tested to proving installation.
Adopt the high-speed serial bus logic analyser can arrive the purpose of bus data transimiison analysis.But the logic analyser that specialized factory provides often costs an arm and a leg, and utilization factor is not high, often can't reach desirable cost performance for non-large-scale debugging test, and general Application Design producer is unwilling to bear the testing apparatus of this costliness.
Because PCI Express bus is a kind of high-speed serial bus of point-to-point connection,, often require PCIE endpoint device 003 is broken off in addition, carry out simulation test and replace equipment 003 with logic analyser in order to guarantee the reliability of transmission signals.The shortcoming of doing like this is to test by direct-on-line, in some occasion (like location of mistake), can't use.
In order to realize online detection, some logic analysis producer has adopted through centre bus sniffer (Mid Bus Prober) and connected the method for logic analyser to the PCIE bus, and is as shown in Figure 2.008 and 009 of centre bus sniffer such as Fig. 2.The principle of work of this device is: on former bus, reserve the sensing point that the centre bus sniffer is installed; The centre bus sniffer is installed on the sensing point of reservation; The sub-fraction energy of the signal that the centre bus sniffer obtains on the bus to be transmitted from bus through sensing point; Then this extremely low-energy signal is amplified and shaping on device, be sent to logic analyser through the high-speed transfer cable again.In order not influence the transmission of former bus, the centre bus sniffer must be the device of a kind of high impedance, low electric capacity, and must have the ability that high speed signal is amplified.Because above three characteristics, the centre bus sniffer need adopt the device with extraordinary electrical specification, and its cost is that cost is high relatively, complex design.Simultaneously,, unavoidably the signal on the former bus is exerted an influence,, cause test inaccurate if connect the improper distorted signals that might make on the former bus because the centre bus sniffer is to take out portion of energy from bus.In addition, because the centre bus sniffer is a kind of electromechanical device of relative complex, its volume ratio is bigger, in some highdensity designs, often can't reserve the space of placing the centre bus sniffer.
Summary of the invention
The purpose of this invention is to provide a kind of high-speed serial bus analytics and device, under the situation that does not influence the high-speed serial bus data transmission, promptly can realize the transmission data on the high-speed serial bus are analyzed.
For realizing above-mentioned purpose, the invention provides a kind of high-speed serial bus analytics, said method comprises:
Receive the bus signals of high-speed serial bus, said bus signals is copied as first signal and secondary signal, first signal is returned said high-speed serial bus, and secondary signal resolved obtain parallel data through the signal shunt module.
To achieve these goals, the present invention also provides a kind of high-speed serial bus logic analysis unit, and said device comprises signal shunt module and signal resolution module;
Said signal shunt module is used for said bus signals is copied as first signal and secondary signal, and first signal is returned said high-speed serial bus, and secondary signal is sent to signal resolution module;
Said signal resolution module is connected with the signal shunt module, is used for secondary signal resolved obtaining parallel data.
The invention provides a kind of easy use high-speed serial bus analytics and device cheaply; Handle through the signal on the high-speed serial bus being carried out shunt; The shunting sign that obtains is leaded up to resolve and is used for logic analysis, and one the tunnel returns high-speed serial bus, under the situation that does not influence the high-speed serial bus data transmission, promptly can analyze the transmission data on the high-speed serial bus; And simplicity of design, cost is lower.
Description of drawings
Fig. 1 is prior art high-speed serial bus logic analysis scheme one synoptic diagram
Fig. 2 is prior art high-speed serial bus logic analysis scheme two synoptic diagram
Fig. 3 is a kind of high-speed serial bus analytics of the present invention embodiment one synoptic diagram
Fig. 4 is a kind of high-speed serial bus analytics of the present invention embodiment two synoptic diagram
Fig. 5 is a kind of high-speed serial bus analytics of the present invention embodiment three synoptic diagram
Fig. 6 is a kind of high-speed serial bus analytics of the present invention embodiment four synoptic diagram
Fig. 7 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment one synoptic diagram
Fig. 8 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment two synoptic diagram
Fig. 9 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment three synoptic diagram
Figure 10 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment four synoptic diagram
Figure 11 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment five synoptic diagram
Figure 12 is a kind of high-speed serial bus logic analysis unit of the present invention embodiment six synoptic diagram
Embodiment
The invention provides a kind of high-speed serial bus analytics, Fig. 3 has provided a kind of high-speed serial bus analytics of the present invention embodiment one synoptic diagram, said method comprising the steps of:
Step S1, the bus signals of reception high-speed serial bus;
Step S2 copies as first signal and secondary signal through the signal shunt module with said bus signals;
For example can said bus signals be copied as first signal and secondary signal through the high-frequency clock driver; The high-frequency clock driver is a kind of electric current and voltage and fan-out capability that is used to increase clock signal, or one tunnel clock signal is strengthened the device for multichannel output.
The inventor finds in the process of embodiment of the present invention; The high-frequency clock driver can carry out shunt to any high-speed serial bus signal through the direct current equilibrium treatment; Its principle of carrying out shunt is following: because the PCIE physical signalling is the direct current equalizing signal through the 8b/10b coding; Be that coding in each 10bit character code of transmitting on the signal transmssion line all guarantees the hopping edge of 0 enough level translation to 1 level or 1 level translation to 0 level, 0 level that occurs in each character code simultaneously and the quantity of 1 level are in a basic balance.PCIE bus per second can transmit 2.5G bit level signal in PCI Express 1.0 standards, and PCIE bus per second can transmit 5G bit level signal in PCIExpress 2.0 standards.If 0 level and 1 level of each character code of PCIE transmission alternately occur, then the PCIE physical signalling is exactly the clock signal of a 1.25G hertz (Hz) or 2.5GHz.And 8b/10b coding is several 0 and several 1 signal that alternately occurs; Therefore the PCIE physical signalling can be regarded near a near clock signal that variation or the 2.5GHz 1.25GHz, changes as; This clock signal can adopt the high-frequency clock driver that its driving is copied as two-way output; The original signal transmission path is returned in a road of two-way output, the transmission of continuity original signal, and other one the tunnel supplies analytical test to use.Because PCI Express 1.0 signal frequencies are up to 1.25GHz; PCI Express 2.0 signal frequencies are up to 2.5GHz, and the high-frequency clock driver of the logic analysis unit that is therefore designed need select for use the high speed device that can drive more than the 1.25GHz maybe can drive the above high speed device of 2.5GHz.
The present invention is applicable to the logic analysis to the high-speed serial bus of any process direct current equilibrium treatment; Comprise and be not limited to the PCIE universal serial bus; For example also comprise 10 gigabit Ethernet accessory unit interfaces (X Attachment Unit Interface; Abbreviation XAUI) universal serial bus, the 4th grade of the 2nd stage (System Packet Interface Level 4Phase 2 of system's packet interface; Abbreviation SPI 4.2) universal serial bus, serial gigabit Media Independent Interface (Serial Gigabit Media IndependentInterface is called for short SGMII), the quick input and output agreement of serial (Serial RapidInput/Output is called for short SRIO) etc.
Step S3 returns first signal to said high-speed serial bus;
Step S4 resolves secondary signal and to obtain parallel data, specifically can for: secondary signal is carried out descrambling and decoding obtains parallel data.For example; Because bus signals is the signal through scrambler is operated and the 8b/10b coding obtains; Therefore can resolve secondary signal through descrambling and 8b/10b decoding, obtain parallel data, supervisory control signals, synchronizing clock signals and the bus state indicator signal of 8bit or 16bit.
Fig. 4 has provided a kind of high-speed serial bus analytics of the present invention embodiment two synoptic diagram, and present embodiment also comprises except the step that comprises method embodiment one:
Step S5 stores said parallel data.Specifically can pass through field programmable gate array (Field-Programmable Gate Array; Be called for short FPGA) parallel data is stored in the internal memory; For example said internal memory can be second generation double-speed Synchronous Dynamic Random Access Memory (Double Data Rate 2Synchronous Dynamic Random Access Memory is called for short DDR2 SDRAM).FPGA is as special IC (Application Specific Integrated Circuit; Abbreviation ASIC) a kind of semi-custom circuit in the field occurs; Both solve the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.Parallel data stored be convenient to that data are sent to the terminal and analyze and show.
Fig. 5 has provided a kind of high-speed serial bus analytics of the present invention embodiment three synoptic diagram, and present embodiment also comprises except the step that comprises embodiment two:
Step S6 is sent to the universal asynchronous receiving-transmitting terminal with said parallel data and preserves or show.Said universal asynchronous receiving-transmitting terminal is the centralized host computer system of a kind of universal asynchronous receiving-transmitting, for example can be personal computer (Personal Computer is called for short PC) terminal.Said parallel data is sent to the universal asynchronous receiving-transmitting terminal to be convenient to long data are preserved, analyzed and show.
Fig. 6 has provided a kind of high-speed serial bus analytics of the present invention embodiment four synoptic diagram, and present embodiment also comprises except the step that comprises embodiment one:
Step S7 outputs to oscillograph with said parallel data.Specifically can use oscilloprobe to survey and resolve the parallel data that obtains, and send to oscillograph, thereby realize real-time monitored data on the high-speed serial bus.
Present embodiment also can carry out above-mentioned expansion on the basis of method embodiment two and method embodiment three.
The present invention also provides a kind of high-speed serial bus logic analysis unit, and Fig. 7 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment one synoptic diagram, and said device comprises: signal shunt module M1 and signal resolution module M2;
Said signal shunt module M1 is used for said bus signals is copied as first signal and secondary signal, first signal is returned said high-speed serial bus, and secondary signal is sent to signal resolution module M2;
Said signal shunt module specifically can be the high-frequency clock driver, and the high-frequency clock driver heavily drives the bus signals of high-speed serial bus such as PCIE system and is two-way, and one the tunnel returns original system, and one the tunnel is used for test.
Said signal resolution module M2 is connected with signal shunt module M1, is used for secondary signal resolved obtaining parallel data.
Said signal resolution module specifically can be PCIE physical layer interface device (PCIE PHY); Secondary signal is carried out descrambling to use PCIE PHY and decoding obtains parallel data; PCIE PHY is device or a device of realizing PCIE agreement physical layer function, can realize descrambling and decoding to the PCIE signal.For example; Because bus signals is the signal through scrambler is operated and the 8b/10b coding obtains; Therefore can use PCIEPHY that secondary signal is carried out descrambling and 8b/10b decoding, obtain parallel data, supervisory control signals, synchronizing clock signals and the bus state indicator signal of 8bit or 16bit.
Fig. 8 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment two synoptic diagram; Present embodiment also comprises memory module M3 except the architectural feature that comprises device embodiment one, M2 is connected with signal resolution module; Be used to receive said parallel data, and store said parallel data.
Fig. 9 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment three synoptic diagram, and present embodiment also is divided into field programmable gate array unit M31 and internal storage location M32 with said memory module M3 except the architectural feature that comprises device embodiment two;
Said field programmable gate array unit M31 is used to receive said parallel data, carries out buffer memory, and sends to internal storage location M32;
Said internal storage location M32 is connected with field programmable gate array unit M31, is used to store said parallel data.
Said field programmable gate array unit specifically can be FPGA, and memory modules can be DDR2SDRAM.
Said high-speed serial bus logic analysis unit can also comprise the universal asynchronous receiving-transmitting terminal, is used to receive the said parallel data that said field programmable gate array unit sends, and preserves or show.
Said high-speed serial bus logic analysis unit can also comprise oscillograph, is used to receive the said parallel data that signal resolution module is sent, and shows.
Figure 10 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment four synoptic diagram; Present embodiment also is divided into said field programmable gate array unit M31 and resolves interface controller M311, memory i/f controller M312, global controller M313 and universal asynchronous receiving-transmitting terminal interface controller M314 except the architectural feature that comprises device embodiment three;
Said parsing interface controller M311 is used to receive parallel data that signal resolution module the sends row cache of going forward side by side, and sends to memory i/f controller M312 then;
Said memory i/f controller M312 is connected with parsing interface controller M311, is used for storing parallel data into internal storage location M32, and reads the parallel data of internal storage location M32 storage and send to global controller M313;
Said global controller M313 is connected with memory i/f controller M312 with parsing interface controller M311, is used for parallel data is read from internal storage location M32 through memory i/f controller M312, and sends to universal asynchronous receiving-transmitting terminal interface controller M314;
Said universal asynchronous receiving-transmitting terminal interface controller M314 is connected with global controller M313, is used for that the parallel data that global controller M313 sends is sent to the asynchronous communication terminal and stores and show.
Figure 11 provides a kind of high-speed serial bus logic analysis unit of the present invention embodiment five synoptic diagram, and present embodiment is the more excellent embodiment of the present invention.
Present embodiment high speed universal serial bus is PCIE, and the PCIE system is by PCIE root node equipment 114, PCIE endpoint device 121, and PCIE sends bus 115,119 and PCIE receives bus 116,120, and bus ac coupling capacitor 117 and 118 is formed.When the transmission bus requirements of 115,117,119 compositions carried out the logic analysis test, 117 ac coupling capacitors need remove.
Said high-speed serial bus logic analysis unit is by forming like lower component: high-frequency clock driver 102, PCIE PHY 105, FPGA 110, DDR2 sdram memory 106, universal asynchronous receiving-transmitting (UniversalAsynchronous Receiver/Transmitter is called for short UART) terminal and oscillograph 113.
Said high-frequency clock driver can be clock driver ICS858011, and PCIE PHY can be PCIEPHY XIO1100.
High-frequency clock driver 102 obtains the PCIE bus signals through bus 101; The PCIE bus signals of PCIE system heavily driven be two-way; The bus 104 of leading up to is returned original system as the system communication passage, and one the tunnel is used for test, sends to PCIE PHY 105 through bus 103.
Because the signal that the PCIE high-speed serial bus is carried is the low-yield signal that changes at a high speed; The signal that transmitter sends can only drive a receiver at most; Therefore this bus two ends only allow respectively to connect a transmitter and a receiver, i.e. said point-to-point connection in the PCIE standard.If directly connect the test cable to former transfer bus, then former driver need drive two receivers, then possibly cause to drive deficiency, causes receiver to receive error in data.Therefore, be difficult to from the PCIE high-speed serial bus, directly take out test signal.The way of general logic analyser is the centre bus sniffer that adopts through particular design, and this device is still unavoidably to exerting an influence on the former transfer bus, and is difficult for using.
It is the characteristic through the direct current equalizing signal of 8b/10b coding that present embodiment has utilized the PCIE physical signalling; Adopt the high-frequency clock driver; Utilize it to carry out signal replication, designed a circuit that takes out signal on the high-speed serial bus, realize taking out test signal from the PCIE high-speed serial bus.
Because the data sequence of transmitting on the PCIE bus is the data sequence of handling through scrambler, 8b/10b coding etc., but not binary code sequence, this raw data can't be analyzed.This programme utilizes PCIEPHY that the original test signal of taking out is handled the binary-coded conventional sequence of output.
The output of bus 103 is inputs of PCIE PHY 105.PCIE PHY 105 carries out the technical finesse of PCIE Physical layers such as descrambling, 8b/10b decoding with the serial data of input; Then on bus 107, export 8bit parallel data, supervisory control signals, synchronizing clock signals and bus state indicator signal; Condition indicative signal indication bus state connects situation, bus transfer error situation like bus; Whether the data on the bus are effective, and whether bus inserts extended byte etc.PCIE PHY is output as the 8bit parallel data of decoding, i.e. the conventional coded data of true transmission on the PCIE bus.Therefore the data directly transmitted on the oscilloscope apparatus direct-on-line Real Time Observation bus through 108 and 113 compositions of the output signal of bus 107.
Storage and display system that FPGA 110, DDR2 sdram memory 106 and UART terminal are formed are preserved and are exported the data of taking out from the PCIE bus and supply analysis to use.
Data are preserved automatically and through the data transmission situation on the UART terminal analysis PCIE bus in order to realize analyzing, and the output signal of bus 107 is input to FPGA 110.FPGA 110 stores the 8bit parallel data on the bus 107 in the DDR2 sdram memory 106 into.The data that will be stored in simultaneously in the DDR2 sdram memory 106 send to UART terminal 112 through bus 111.UART terminal 112 shows the data that send and preserves.
The inner structure design of said FPGA 110 is shown in figure 12.
PCIE phy interface controller 202 carries out buffer memory with the parallel data that bus 107 sends, and sends to DDR2 sdram memory interface controller 208 then.
DDR2 sdram memory interface controller 208 writes the DDR2 sdram memory with the data that PCIE phy interface controller 202 sends through bus 109.The data that while DDR2 sdram memory interface controller 208 also can be read the DDR2 sdram memory send to global controller 207.
The function of global controller 207 comprises:
(1) start address that will preserve the DDR2 sdram memory of PCIE parallel data is written in the PCIEPHY interface controller 202;
(2) according to the data length indicator of PCE phy interface controller 202 data are read from the DDR2 sdram memory through DDR2SDRAM memory i/f controller 208, and send to UART interface controller 210;
(3) receive UART interface controller 210 and pass the command word of coming, and resolve, send the FPGA internal control signal according to command word.
The internal work process of FPGA 110 is following:
The start address that global controller 207 will be preserved the DDR2 sdram memory of PCIE parallel data is written to 202PCIE phy interface controller;
PCIE phy interface controller 202 begins to store the parallel data from the total line drawing of PCIE from start address; Carrying out automatic memory address adds up; Preserve EO address and the total data volume that is written to the DDR2 sdram memory simultaneously, and start address is updated to the EO address.
When global controller 207 receives the video data order that UART interface controller 210 sends over; Data are read from the DDR2 sdram memory through DDR2 sdram memory interface controller 208; And send to UART interface controller 210; Send to the demonstration of UART terminal and preserve confession system designer analysis use through UART interface controller 210.
When global controller 207 receives the order that clears data that UART interface controller 210 sends over, then start address and end address in the PCIE phy interface controller 202 are changed to initial value again.And reset to 0 being written to DDR2 sdram memory data total amount.
Easy in order to design, global controller 207 receives only the demonstration that the 210UART interface controller sends over and removes two kinds of orders, and other orders are not carried out.
Because the technical characterstic of high-speed serial bus such as PCIE bus; Make system designer can't only adopt equipment commonly used such as oscillograph that high-speed serial bus is analyzed and tested; And must acquire complicacy and the higher logical analysis device of cost; Reach the purpose that system debug is tested by logical analysis device, use logic analyser need dispose some not wield sniffers, cause the test difficulty toward contact.Simultaneously,, unavoidably the signal on the former bus is exerted an influence,, cause test inaccurate if connect the improper distorted signals that might make on the former bus because the centre bus sniffer is to take out portion of energy from bus.
The invention provides a kind of easy use high-speed serial bus analytics and device cheaply; Handle through the signal on the high-speed serial bus being carried out shunt, the shunting sign that obtains is leaded up to resolve and is used for logic analysis, and one the tunnel returns high-speed serial bus; Under the situation that does not influence the high-speed serial bus data transmission, promptly can analyze the transmission data on the high-speed serial bus; And simplicity of design, cost is lower, and the parallel data that the present invention also obtains parsing stores in the internal memory; And parallel data is sent to the universal asynchronous receiving-transmitting terminal preserve and show, be convenient to carry out logic analysis.Apparatus of the present invention only need to cooperate the purpose that can reach online high-speed serial bus logic analysis with common equipment such as oscillograph or PC terminal etc., have made things convenient for the debugging test of high-speed serial bus system.
Parts of giving an example in apparatus of the present invention such as high-frequency clock driver, PCIE PHY, DDR2 sdram memory etc. are not as limitation of the present invention; The similar realization all can be substituted in the device of the present invention with the device of above-mentioned parts identical function, all belongs to protection scope of the present invention.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (6)
1. a high-speed serial bus analytics is characterized in that, said method comprises:
Receive the bus signals of high-speed serial bus, said bus signals is copied as first signal and secondary signal, first signal is returned said high-speed serial bus, and secondary signal resolved obtain parallel data through the signal shunt module; Store said parallel data, said parallel data is sent to the universal asynchronous receiving-transmitting terminal preserves or show;
Said signal shunt module is specially the high-frequency clock driver, and said high-frequency clock driver is a kind of electric current and voltage and fan-out capability that is used to increase clock signal, or one tunnel clock signal is strengthened the device for multichannel output.
2. high-speed serial bus analytics according to claim 1 is characterized in that, to secondary signal resolve obtain parallel data after, also comprise: said parallel data is outputed to oscillograph.
3. high-speed serial bus analytics according to claim 1 is characterized in that, said secondary signal is resolved obtains parallel data and be specially: secondary signal is carried out descrambling and decoding obtains parallel data.
4. a high-speed serial bus logic analysis unit is characterized in that, comprising: signal shunt module and signal resolution module;
Said signal shunt module is used for said bus signals is copied as first signal and secondary signal, and first signal is returned said high-speed serial bus, and secondary signal is sent to signal resolution module; Said signal shunt module is specially the high-frequency clock driver;
Said signal resolution module is connected with the signal shunt module, is used for secondary signal resolved obtaining parallel data;
Memory module is connected with signal resolution module, is used to receive said parallel data, and stores said parallel data; Said memory module comprises field programmable gate array unit and internal storage location; Said field programmable gate array unit is used to receive said parallel data, carries out buffer memory, and sends to internal storage location; Said internal storage location is connected with the field programmable gate array unit, is used to store said parallel data;
The universal asynchronous receiving-transmitting terminal is used to receive the said parallel data that said field programmable gate array unit sends, and preserves or show.
5. high-speed serial bus logic analysis unit according to claim 4 is characterized in that, also comprises oscillograph, is used to receive the said parallel data that signal resolution module is sent, and shows.
6. high-speed serial bus logic analysis unit according to claim 5 is characterized in that, said field programmable gate array unit comprises: resolve interface controller, memory i/f controller, global controller and universal asynchronous receiving-transmitting terminal interface controller;
Said parsing interface controller is used to receive parallel data that signal resolution module the sends row cache of going forward side by side, and sends to memory i/f controller then;
Said memory i/f controller is connected with the parsing interface controller, is used for storing parallel data into internal storage location, and reads the parallel data of internal storage location storage and send to global controller;
Said global controller is connected with the parsing interface controller with memory i/f controller, is used for parallel data is read from internal storage location through memory i/f controller, and sends to the universal asynchronous receiving-transmitting terminal interface controller;
Said universal asynchronous receiving-transmitting terminal interface controller is connected with global controller, is used for that the parallel data that global controller is sent is sent to the asynchronous communication terminal and stores and show.
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| US8738852B2 (en) * | 2011-08-31 | 2014-05-27 | Nvidia Corporation | Memory controller and a dynamic random access memory interface |
| CN103970695B (en) * | 2013-01-25 | 2017-03-01 | 北京旋极信息技术股份有限公司 | RapidIO method for monitoring bus |
| CN104102608A (en) * | 2014-07-23 | 2014-10-15 | 四川和芯微电子股份有限公司 | Logic analyzer |
| CN104660470A (en) * | 2015-03-03 | 2015-05-27 | 北京华力创通科技股份有限公司 | Device and method for detecting Rapid IO bus protocol |
| KR102329802B1 (en) * | 2015-07-23 | 2021-11-22 | 삼성전자주식회사 | Test Board, Test Equipment, Test System and Test Method |
| CN108833243B (en) * | 2018-06-07 | 2020-05-29 | 浙江大学 | High-speed optical data bus based on passive optical bus technology |
| CN112241384B (en) * | 2019-07-19 | 2022-07-01 | 上海复旦微电子集团股份有限公司 | Universal high-speed serial differential signal shunt circuit and method |
| CN110737624A (en) * | 2019-09-23 | 2020-01-31 | 天津市英贝特航天科技有限公司 | circuit for realizing PCIE bus switching peripheral mounting |
| CN114443400B (en) * | 2022-04-11 | 2022-08-02 | 飞腾信息技术有限公司 | Signal testing method and device, system on chip, electronic equipment and storage medium |
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| CN101197649A (en) * | 2008-01-03 | 2008-06-11 | 福建星网锐捷网络有限公司 | Peripheral unit interconnection high speed bus interface and switchboard port testing method and system |
| CN100478935C (en) * | 2007-10-10 | 2009-04-15 | 福建星网锐捷网络有限公司 | PCIE channel expansion device, system and its collocation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100478935C (en) * | 2007-10-10 | 2009-04-15 | 福建星网锐捷网络有限公司 | PCIE channel expansion device, system and its collocation method |
| CN101197649A (en) * | 2008-01-03 | 2008-06-11 | 福建星网锐捷网络有限公司 | Peripheral unit interconnection high speed bus interface and switchboard port testing method and system |
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