WO2009031737A1 - Universal high-speed real-time monitoring device for embedded systems - Google Patents
Universal high-speed real-time monitoring device for embedded systems Download PDFInfo
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- WO2009031737A1 WO2009031737A1 PCT/KR2008/001075 KR2008001075W WO2009031737A1 WO 2009031737 A1 WO2009031737 A1 WO 2009031737A1 KR 2008001075 W KR2008001075 W KR 2008001075W WO 2009031737 A1 WO2009031737 A1 WO 2009031737A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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Abstract
The present invention relates to a universal high-speed real-time monitoring device for embedded systems. The monitoring device (4) receives monitoring data packets from a target embedded system (2) and transmits the monitoring data packets to a host PC (6) while receiving a monitoring start signal or monitoring stop signal from the host PC and outputting the signal to the target embedded system. The monitoring device (4) includes differential signal transceivers, a digital isolator, a first processor, asynchronous dual-port FIFO RAM, a second processor, a USB interface chip or a USB processor, a voltage regulator, an isolated DC/DC converter, a target side power-ground section, a host side power-ground section, a serial communication connector, and a USB communication connector. Accordingly, the target embedded system is completely electrically isolated from the host PC.
Description
Description
UNIVERSAL HIGH-SPEED REAL-TIME MONITORING DEVICE FOR EMBEDDED SYSTEMS
Technical Field
[1] The present invention relates, in general, to a universal high-speed real-time monitoring device for embedded systems, and, more particularly, to a universal highspeed real-time monitoring device for embedded systems, which can debug the electronic circuits, CPU firmware, embedded software and device drivers of a target embedded system with a host PC, such as a typical desktop or notebook PC, equipped with a USB communication port, by performing high-speed synchronous serial communication with the target embedded system. Background Art
[2] Generally, in embedded systems, such as most digital electronic devices and electronic equipment, for example, wired/wireless communication systems, network equipment, industrial automation systems, medical electronic devices, office equipment, electric home appliances, audio/video devices, vehicle electronic devices, and aerospace electronic devices, a microcontroller (MCU) or a Digital Signal Processor (DSP), used as a Central Processing Unit (CPU), performs signal processing and controls, as well as high-speed calculation on digital data, thus enabling the operation of the embedded systems. The monitoring of an embedded system is required in order not only to verify and debug hardware electronic circuits,
[3] the CPU firmware or embedded software at the time of developing such an embedded system, but also to periodically evaluate the performance and operating states of the embedded system which has been installed to perform its unique embedded task.
[4] Meanwhile, with the realization of high speed and high performance embedded systems, the importance of the function of monitoring/debugging the dynamic execution states of embedded systems in real time, beyond the breakpoint debugging function for a target MCU/DSP, has gradually increased in the process for developing embedded systems. Therefore, international semiconductor manufacturing companies, which manufacture MCU/DSP cores, provide an embedded system developer with a real-time monitoring function through the JTAG port or dedicated high-speed data communication port of an MCU/DSP by including an on-chip debugging silicon module in MCU/DSP cores, thus improving the real-time visibility of the execution states of a CPU.
[5] However, since such a dedicated on-chip debugging silicon module can be applied
only to a specific MCU/DSP core, there is a difficulty in that, whenever an MCU/DSP platform is changed, an embedded system developer must also replace the current development equipment for embedded systems with a new development equipment including the integrated development environment suitable for the platform and expensive subsidiary hardware, and also must learn about the usage of the new development equipment. Further, since various limitations arise in the high-speed realtime monitoring performance when using a dedicated on-chip debugging silicon module, due to a number of technical difficulties accompanying high-speed real-time monitoring, there are many problems in monitoring a high-performance embedded system, which is operating at high speed, in real time. Disclosure of Invention Technical Problem
[6] Accordingly, the present invention has been made keeping in mind the above problems arising in the prior art, and an object of the present invention is to provide a universal high-speed real-time monitoring device for embedded systems which does not temporarily stop a target embedded system or does not generate any interrupt, by using a high-speed synchronous serial communication module which is the universal peripheral communication module of an MCU/DSP, without using a dedicated debugging silicon module, thereby debugging the electronic circuits, the CPU firmware, embedded software or device drivers of the target embedded system in real time, or monitoring the high-speed execution states thereof in real time, without interfering with the execution of a CPU. Technical Solution
[7] In order to accomplish the above object, the present invention provides a universal high-speed real-time monitoring device for embedded systems, wherein a target embedded system generates monitoring data packets and transmits the monitoring data packets to a host PC through the universal real-time monitoring device. In this case, the target embedded system transmits the monitoring data packets to the universal realtime monitoring device in a high-speed synchronous serial communication manner. The target embedded system operates in the master mode for high-speed synchronous serial communication, and the universal real-time monitoring device operates in the slave mode. At the time of performing USB communication between the universal real-time monitoring device and the host PC, the universal real-time monitoring device transmits the monitoring data packets received from the target embedded system to the host PC, and the host PC transmits a monitoring start signal or monitoring stop signal to the universal real-time monitoring device. Accordingly, the universal real-time monitoring device functions as a data buffer to enable asynchronous high-speed com-
munication to be performed between the target embedded system and the host PC. [8] In accordance with an aspect of the present invention, there is provided a universal high-speed real-time monitoring device for embedded systems, which transmits monitoring data about a target embedded system to a host Personal Computer (PC) in real time, wherein a first monitoring data transmission start signal is transmitted to the target embedded system when a monitoring start signal is received from the host PC and a first monitoring data transmission stop signal is transmitted to the target embedded system when a monitoring stop signal is received from the host PC, and wherein a first signal, including monitoring data generated by the target embedded system in response to the first monitoring data start signal, is received from the target embedded system, so that the monitoring data is extracted from the first signal and is transmitted to the host PC, and the target embedded system stops generating the first signal in response to the first monitoring data stop signal.
Advantageous Effects
[9] As described above, the present invention provides a universal high-speed real-time monitoring device for embedded systems, in which a target embedded system performs high-speed communication with the universal real-time monitoring device in real time by using a high-speed synchronous serial communication module, which is the universal peripheral communication module of a CPU, so that the real-time monitoring device of the present invention can be applied to all target embedded systems, each having a CPU provided with a universal peripheral communication module. Brief Description of the Drawings
[10] FIG. 1 is a diagram showing the construction of a universal high-speed real-time monitoring system for embedded systems according to the present invention;
[11] FIG. 2 is a detailed block diagram showing universal real-time monitoring device according to a first embodiment of the present invention; and
[12] FIG. 3 is a detailed block diagram showing universal real-time monitoring device according to a second embodiment of the present invention. Mode for the Invention
[13] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
[14] FIG. 1 is a diagram showing the construction of a universal high-speed real-time monitoring system for embedded systems according to the present invention. The universal high-speed real-time monitoring system includes a target embedded system 2, universal real-time monitoring device 4, a host PC 6, such as a typical desktop PC or notebook PC, a USB communication cable 8, and a serial communication cable 10.
[15] The target embedded system 2 and the universal real-time monitoring device 4 are
connected to each other through the serial communication cable 10, and are configured to perform high-speed synchronous serial communication. The target embedded system, operating in the master mode, transmits real-time monitoring data packets to the universal real-time monitoring device 4, operating in the slave mode. Meanwhile, the universal real-time monitoring device 4 and the host PC 6 are connected to each other through the USB communication cable 8 and are configured to perform USB communication. Accordingly, the universal real-time monitoring device 4 functions as an asynchronous data buffer, and thus transmits the real-time monitoring data packets, received from the target embedded system 2, to the host PC 6 at high speed. Meanwhile, in the serial communication cable 10, composed of four pairs of twisted cables, three pairs of twisted cables respectively function as the signal line for a differential monitoring data packet transmission command signal 12, and the signal lines for a differential digital clock signal 14 and a differential digital data signal 16 on highspeed synchronous serial communication, and the remaining pair of twisted cables functions as the ground line. The universal high-speed real-time monitoring device for embedded systems of the present invention is operated as set forth in the following description.
[16] When a user inputs a monitoring start signal using the host PC 6, the monitoring start signal is transmitted to the universal real-time monitoring device 4 through USB communication. Then, the universal real-time monitoring device 4 generates a differential monitoring data packet transmission command signal 12 at an assertive logic level, and transmits the resulting signal to the target embedded system 2. When a differential monitoring data packet transmission command signal 12 is at an assertive logic level, the target embedded system 2, after a unique embedded process has been completed, generates monitoring data packets implemented on the basis of monitoring variables corresponding to the content of the register or memory of a CPU core, or the variables of firmware, and outputs the generated monitoring data packets to the universal realtime monitoring device 4 as a differential digital clock signal 14 and a differential digital data signal 16 for high-speed synchronous serial communication. The universal real-time monitoring device 4 extracts monitoring data packets from the input differential digital clock signal 14 and the input differential digital data signal 16 for highspeed synchronous serial communication, and transmits the extracted monitoring data packets to the host PC 6 through USB communication. Then, the host PC 6 displays monitoring variables on the screen of a monitor in the form of real-time graphs, and stores the monitoring variables in a hard disc drive.
[17] Meanwhile, when the user inputs a monitoring stop signal using the host PC 6, the monitoring stop signal is transmitted to the universal real-time monitoring device 4 through USB communication. Then, the universal real-time monitoring device 4
generates the differential monitoring data packet transmission command signal 12 at a deassertive logic level, and outputs the resulting signal to the target embedded system 2. When the input differential monitoring data packet transmission command signal is at a deassertive logic level, the target embedded system 2 executes only a unique embedded process, and does not generate monitoring data packets.
[18] Therefore, as described above, the differential monitoring data packet transmission command signal 12 becomes the differential monitoring data packet transmission start signal when it is at an assertive logic level, whereas the differential monitoring data packet transmission command signal 12 becomes the differential monitoring data packet transmission stop signal when it is at a deassertive logic level.
[19] The detailed block diagram of the universal real-time monitoring device 4, which functions as a data buffer to enable asynchronous high-speed communication between the target embedded system 2 and the host PC 6, according to a first embodiment of the present invention, is shown in FIG. 2. The universal real-time monitoring device 4 includes a differential signal transceivers 41, a digital isolator 42, a first processor 43, asynchronous dual-port FIFO Random Access Memory (RAM) 44, a second processor 45, a USB interface chip 46, a voltage regulator 47, an isolated DC/DC converter 48, a target side power- ground 50, a host side power- ground 51, a serial communication connector 52, and a USB communication connector 53.
[20] The operation of the universal real-time monitoring device 4 of the present invention, having the above construction, will be described below.
[21] First, the universal real-time monitoring device 4 is a USB peripheral device, which is connected to the USB port of the host PC 6 through the USB communication cable 8 to be operated, and is supplied with 5V DC power from the host PC 6. In the universal real-time monitoring device 4, since the target side power-ground section 50 is completely isolated from the host side power- ground section 51 both by the digital isolator 42 for isolating digital signals and by the isolated DC/DC converter 48 for isolating DC power sources, the universal real-time monitoring device 4 and the host PC 6 can be protected from high voltage or high current caused by electrical surges or ground loops on the serial communication cable 10. The voltage regulator 47 regulates the 5V DC voltage supplied from the USB port of the host PC 6 to the voltage level required by the host side power-ground section 51. The isolated DC/DC converter 48 not only completely isolates the target side power-ground section 50 from the host side power- ground section 51, but also converts the 5 V DC voltage supplied from the USB port of the host PC 6 into the voltage level required by the target side power-ground section 50.
[22] Therefore, the differential signal transceivers 41 and the serial communication connector 52 are supplied with operating power from the target side power-ground
section 50, and the first processor 43, the asynchronous dual-port FIFO RAM 44, the second processor 45, the USB interface chip 46, the voltage regulator 47, and the USB communication connector 53 are supplied with operating power from the host side power- ground section 51.
[23] The differential signal transceivers 41 are electrically connected to the serial communication connector 52, and is configured to convert both the differential digital clock signal 15 and the differential digital data signal 16 for high-speed synchronous serial communication, which are transmitted from the target embedded system 2, into a digital clock signal and a digital data signal, which are single-ended signals, respectively, and to output the digital clock signal and the digital data signal to the digital isolator 42. Meanwhile, the differential signal transceivers 41 are configured to receive a single-ended monitoring data packet transmission command signal, generated by the first processor 43 and output from the digital isolator 42, to convert this signal into the differential monitoring data packet transmission command signal 12, and to output the differential monitoring data packet transmission command signal to the target embedded system 2 through the serial communication connector 52. In this way, the target embedded system 2 and the universal real-time monitoring device 4 perform high-speed synchronous serial communication using differential signals, thus enabling high-speed synchronous serial communication therebetween over a long distance.
[24] The digital isolator 42 enables the differential signal transceivers 41, belonging to the target side power- ground section 50, and the first processor 43, belonging to the host side power- ground section 51, to respectively input/output the digital clock signal and the digital data signal for high-speed synchronous serial communication and the monitoring data packet transmission command signal which are completely electrically isolated.
[25] The first processor 43 receives the digital clock signal and the digital data signal for high-speed synchronous serial communication from the digital isolator 42 while operating in the master mode for high-speed synchronous serial communication, extracts the monitoring data packets, generated by the target embedded system 2, from the received signals, and sequentially records the monitoring data packets in the asynchronous dual-port FIFO RAM 44 through the writing port of the asynchronous dual- port FIFO RAM 44. Further, the first processor 43 receives a monitoring data packet transmission command signal 49 from the second processor 45, and outputs the monitoring data packet transmission command signal 49 to the digital isolator 42.
[26] The second processor 45 sequentially reads the monitoring data packets through the reading port of the asynchronous dual-port FIFO RAM 44, and outputs the monitoring data packets to the USB interface chip 46. Further, the second processor 45 reads the monitoring start signal or monitoring stop signal, transmitted by the host PC 6, from
the USB interface chip 46, and outputs a monitoring data packet transmission command signal 49 at an assertive logic level, i.e. monitoring data packet transmission start signal, to the first processor 43 when the host PC 6 transmits the monitoring start signal. Conversely, when the host PC 6 transmits the monitoring stop signal, the second processor 45 outputs a monitoring data packet transmission command signal 49 at a deassertive logic level, i.e. monitoring data packet transmission stop signal, to the first processor 43.
[27] In this way, the asynchronous dual-port FIFO RAM 44 sequentially receives the monitoring data packets from the first processor 43 through the writing port and sequentially outputs the monitoring data packets to the second processor 45 through the reading port. The writing port and the reading port of the asynchronous dual-port FIFO RAM 44 can be accessed to simultaneously, and thus the asynchronous dual-port FIFO RAM 44 functions as buffer memory that enables the first processor 43 and the second processor 45 to asynchronously exchange monitoring data packets with each other.
[28] The USB interface chip 46 is electrically connected to the USB communication connector 53 and is configured to enable USB communication with the host PC 6 through a USB protocol engine and a USB transceiver, which are included in the USB interface chip 46. The USB interface chip 46 further includes a transmission FIFO buffer and a reception FIFO buffer, which are separate components. Accordingly, the USB interface chip 46 sequentially records the monitoring data packets, which are read by the second processor 45 from the asynchronous dual-port FIFO RAM 44 and are output to the USB interface chip 46, in the transmission FIFO buffer, thus transmitting the monitoring data packets to the host PC 6 at the time of USB communication. Meanwhile, the USB interface chip 46 records the monitoring start signal or the monitoring stop signal, which is transmitted from the host PC 6 to the USB interface chip 46 through the USB communication connector 53, in the reception FIFO buffer, thereby enabling the second processor 45 to read the monitoring start signal or the monitoring stop signal from the USB interface chip 46.
[29] As described above, the monitoring start signal or the monitoring stop signal, generated by the host PC 6, sequentially passes through the USB communication cable 8, the USB communication connector 53, the USB interface chip 46, the second processor 45, the signal line for the monitoring data packet transmission command signal 49, the first processor 43, the digital isolator 42, the differential signal transceivers 41, the serial communication connector 52, and the signal line for the differential monitoring data packet transmission command signal 12 of the serial communication cable 10, and is then received by the target embedded system 2.
[30] In contrast, the monitoring data packets, generated by the target embedded system 2, sequentially pass through the signal line for the differential digital clock signal 14 and
the signal line for the differential digital data signal 16 on high-speed synchronous serial communication of the serial communication cable 10, the serial communication connector 52, the differential signal transceivers 41, the digital isolator 42, the first processor 43, the asynchronous dual-port FIFO RAM 44, the second processor 45, the USB interface chip 46, the USB communication connector 53, and the USB communication cable 8, and are then received by the host PC 6.
[31] FIG. 3 is a detailed block diagram showing the universal real-time monitoring device
4 according to a second embodiment of the present invention. The same reference numerals are used to designate the same components as those of the first embodiment of FIG. 1, and only the difference between the first and second embodiments is described.
[32] In FIG. 3, all of the functions of the second processor 45 and the USB interface chip
46 according to the first embodiment are integrated into a USB processor 54, so that the USB processor 54 is directly electrically connected to a USB communication connector 53, and performs USB communication with the host PC 6 through a USB protocol engine and a USB transceiver, which are included in the USB processor 54.
[33] The USB processor 54 sequentially reads monitoring data packets through the reading port of asynchronous dual-port FIFO RAM 44, and sequentially records the monitoring data packets in the transmission FIFO buffer included therein, thus transmitting the monitoring data packets to the host PC 6 at the time of USB communication. Further, the USB processor 54 records a monitoring start signal or a monitoring stop signal, transmitted from the host PC 6, in the reception FIFO buffer included therein, outputs a monitoring data packet transmission command signal 49 at an assertive logic level, i.e. monitoring data packet transmission start signal, to the first processor 43 when the monitoring start signal is received, and outputs a monitoring data packet transmission command signal 49 at a deassertive logic level, i.e. monitoring data packet transmission stop signal, to the first processor 43 when the monitoring stop signal is received.
[34] As described above, the monitoring start signal or the monitoring stop signal, generated by the host PC 6, sequentially passes through the USB cable 8, the USB communication connector 53, the USB processor 54, the signal line for the monitoring data packet transmission command signal 49, the first processor 43, the digital isolator 42, the differential signal transceivers 41, the serial communication connector 52, and the signal line for the differential monitoring data packet transmission command signal 12 of the serial communication cable 10, and is then received by the target embedded system 2. In contrast, the monitoring data packets generated by the target embedded system 2 sequentially pass through the signal line for the differential digital clock signal 14 and the signal line for the differential digital data signal 16 on high-speed
synchronous serial communication of the serial communication cable 10, the serial communication connector 52, the differential signal transceivers 41, the digital isolator 42, the first processor 43, the asynchronous dual-port FIFO RAM 44, the USB processor 54, the USB communication connector 53, and the USB communication cable 8, and are then received by the host PC 6. Industrial Applicability
[35] As described above, the present invention provides a universal high-speed real-time monitoring device for embedded systems, in which a target embedded system performs high-speed communication with universal real-time monitoring device in real time using a high-speed synchronous serial communication module, which is the universal peripheral communication module of a CPU, so that the real-time monitoring device of the present invention can be applied to all target embedded systems, each having a CPU provided with a universal peripheral communication module.
[36] Further, the present invention is advantageous in that, since a target embedded system transmits monitoring data packets through high-speed synchronous serial communication, transmission time is very short, so that the electronic circuits, the CPU firmware, embedded software or device drivers of the target embedded system can be debugged in real time, or the high-speed execution states can be monitored in real time, using a host PC through universal real-time monitoring device without interfering with the execution of the unique process of the target embedded system.
[37] Further, the present invention is advantageous in that, since universal real-time monitoring device receives monitoring data packets from a target embedded system in a differential signal transmission manner via a serial communication cable composed of four pairs of twisted cables, the target embedded system can be debugged in real time, or the performance or high-speed operation states of the target embedded system can be monitored in real time even when the target embedded system is located more than 100m away from the universal real-time monitoring device, rather than being placed adjacent thereto, due to the conditions of a working environment.
[38] However, when the target embedded system and the real-time monitoring device are separated through such a long cable, the grounds thereof may not have the same potential due to variation in the industrial environment. If the grounds of the target embedded system and the real-time monitoring device are not isolated from each other, high current may flow through a ground loop, thereby not only deteriorating the measurement quality of a monitoring signal, but also damaging both the real-time monitoring device and the host PC. However, in the universal real-time monitoring device of the present invention, a target side power-ground section and a host-side power-ground section are completely isolated from each other by a digital isolator and
an isolated DC/DC converter, thereby protecting the universal real-time monitoring device and the host PC from high voltage or high current caused by electrical surges occurring in an industrial environment, such as the ON/OFF operation of a large- capacity motor, an Electrostatic Discharge (ESD), or a stroke of lightning.
[39] Meanwhile, when a Serial Peripheral Interface (SPI) is used as the peripheral communication module of a CPU, synchronous serial communication can be conducted at a maximum transfer rate over 20 Mbps. In this case, it is profitable to use the RS-422 (TIA/EIA-422-B standard) transmission method rather than Low- Voltage Differential Signaling (LVDS) (TIA/EIA-644 standard) as a differential signal transmission method from the standpoint of the influence of noise on a transmission line and the transmission distance. It is more profitable to use twisted cables rather than untwisted cables for a synchronous serial communication cable from the standpoint of the influence of noise attributable to the installation environment of a transmission line, EMI, and transmission distance.
[40] Therefore, as the synchronous serial communication cable, a four-pair CAT5 Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) cable, which is used as communication lines for Ethernet, which is the most widely used LAN standard, can be used. In particular, a direct-type cable, rather than a cross-type cable, is used. As the serial communication connector, an RJ-45 8-pin connector, used for Ethernet communication, can be used. A pair of twisted cables, which are connected to the third pin and the sixth pin of each of RJ-45 8-pin connectors installed at both ends of a direct-type four-pair CAT5 UTP/STP cable, can be used as a ground line.
[41] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
[42]
Claims
[1] A universal high-speed real-time monitoring device for embedded systems, transmitting monitoring data about a target embedded system to a host Personal
Computer (PC) in real time, wherein: a first monitoring data transmission command signal is transmitted to the target embedded system when a monitoring start signal or a monitoring stop signal is received from the host PC, and a first signal, including monitoring data generated by the target embedded system in response to the first monitoring data start signal, is received from the target embedded system, so that the monitoring data is extracted from the first signal and is transmitted to the host PC.
[2] The universal high-speed real-time monitoring device for embedded systems according to claim 1 comprises: a first stage, connected to the target embedded system and configured to convert a received signal into a required format and to transmit a resultant signal; a second stage, connected to the host PC and configured to extract the monitoring data; and a first element, disposed between the first and second stages and configured to transmit signals therebetween.
[3] The universal high-speed real-time monitoring device for embedded systems according to claim 2, wherein the first stage comprises: a first connector, connected to the target embedded system; and a signal conversion unit, configured to receive the first signal from the target embedded system through the first connector, convert the first signal into a second signal, transmit the second signal to the second stage through the first element, receive a second monitoring data transmission command signal from the second stage through the first element, convert the second monitoring data transmission command signal into the first monitoring data transmission command signal, and transmit the first monitoring data transmission command signal to the target embedded system through the first connector.
[4] The universal high-speed real-time monitoring device for embedded systems according to claim 2, wherein the second stage comprises: a second connector connected to the host PC; a first processor for receiving a second signal, obtained by converting the first signal, from the first stage through the first element, extracting the monitoring data from the second signal, storing the monitoring data in memory, receiving a second monitoring data transmission command signal from a second processor,
and transmitting the second monitoring data transmission command signal to the first stage through the first element; and the second processor for reading the monitoring data from the memory, transmitting the read monitoring data to the host PC through the second connector, and transmitting the second monitoring data transmission command signal to the first processor when a monitoring start signal or a monitoring stop signal is received from the host PC through the second connector.
[5] The universal high-speed real-time monitoring device for embedded systems according to claim 3, wherein: the first signal and the first monitoring data transmission command signal have forms of differential signals, the second signal and the second monitoring data transmission command signal have forms of single-ended signals, and the first signal and the second signal each comprise a digital clock signal and a digital data signal.
[6] The universal high-speed real-time monitoring device for embedded systems according to claim 4, wherein: the second stage further comprises a voltage regulator for regulating supplied operating power to the voltage level required for the second stage, and supplying the voltage to the second stage, and the operating power is supplied from the host PC through the second connector.
[7] The universal high-speed real-time monitoring device for embedded systems according to claim 2, wherein: the monitoring device further comprises a second element disposed between the first and second stages, the second element converting supplied operating power into the voltage level required for the first stage and supplying the voltage to the first stage, and the operating power is supplied from the host PC through a connector disposed on the second stage to connect to the host PC.
[8] The universal high-speed real-time monitoring device for embedded systems according to claim 7, wherein the first element is a digital isolator and the second element is an isolated DC/DC converter.
[9] The universal high-speed real-time monitoring device for embedded systems according to claim 4, wherein the second processor comprises: a processor unit for reading the monitoring data from the memory, outputting the monitoring data to an interface unit, reading the monitoring start signal or the monitoring stop signal from a reception buffer of the interface unit, and outputting the second monitoring data transmission command signal to the first
processor; and the interface unit including means for performing communication with the host PC through the second connector, the interface unit being provided with a transmission buffer for recording the monitoring data and the reception buffer for recording the monitoring start signal or the monitoring stop signal, the interface unit transmitting the monitoring data recorded in the transmission buffer to the host PC, and wherein the means provided in the interface unit and configured to perform communication comprises a USB protocol engine and a USB transceiver.
[10] The universal high-speed real-time monitoring device for embedded systems according to claim 1, wherein: the monitoring device transmits or receives signals to or from the target embedded system in a high-speed synchronous serial communication manner, and the monitoring device transmits or receives signals to or from the host PC in an asynchronous USB communication manner.
[11] The universal high-speed real-time monitoring device for embedded systems according to claim 1, wherein the monitoring device is operated such that, when a monitoring stop signal is received from the host PC, the monitoring device transmits the monitoring data transmission stop signal to the target embedded system, thus stopping generation of the monitoring data by the target embedded system.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070091268A KR20090026230A (en) | 2007-09-09 | 2007-09-09 | Universal high-speed real-time monitoring device for embedded systems |
| KR10-2007-0091268 | 2007-09-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2009031737A1 true WO2009031737A1 (en) | 2009-03-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2008/001075 WO2009031737A1 (en) | 2007-09-09 | 2008-02-25 | Universal high-speed real-time monitoring device for embedded systems |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20090026230A (en) |
| WO (1) | WO2009031737A1 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2013505727A (en) * | 2009-09-27 | 2013-02-21 | オーピーエックス バイオテクノロジーズ， インコーポレイテッド | Process for producing 3-hydroxypropionic acid and other products |
| US8652816B2 (en) | 2007-12-04 | 2014-02-18 | Opx Biotechnologies, Inc. | Compositions and methods for 3-hydroxypropionate bio-production from biomass |
| US8809027B1 (en) | 2009-09-27 | 2014-08-19 | Opx Biotechnologies, Inc. | Genetically modified organisms for increased microbial production of 3-hydroxypropionic acid involving an oxaloacetate alpha-decarboxylase |
| CN104035422A (en) * | 2014-06-23 | 2014-09-10 | 中国北方车辆研究所 | Data calculation method based on smart mobile terminal |
| CN105657868A (en) * | 2016-01-29 | 2016-06-08 | 努比亚技术有限公司 | Mobile terminal and interface control method thereof |
| US9512057B2 (en) | 2013-03-15 | 2016-12-06 | Cargill, Incorporated | 3-hydroxypropionic acid compositions |
| US10047383B2 (en) | 2013-03-15 | 2018-08-14 | Cargill, Incorporated | Bioproduction of chemicals |
| CN109413354A (en) * | 2018-11-19 | 2019-03-01 | 天津津航技术物理研究所 | A kind of infrared detector interface adaption device |
| US10337038B2 (en) | 2013-07-19 | 2019-07-02 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
| US10465213B2 (en) | 2012-08-10 | 2019-11-05 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
| US10494654B2 (en) | 2014-09-02 | 2019-12-03 | Cargill, Incorporated | Production of fatty acids esters |
| US11345938B2 (en) | 2017-02-02 | 2022-05-31 | Cargill, Incorporated | Genetically modified cells that produce C6-C10 fatty acid derivatives |
| US11408013B2 (en) | 2013-07-19 | 2022-08-09 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
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| CN103578258A (en) * | 2013-09-10 | 2014-02-12 | 昆山奥德鲁自动化技术有限公司 | Long-range Ethernet-based analog signal collector |
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| US8652816B2 (en) | 2007-12-04 | 2014-02-18 | Opx Biotechnologies, Inc. | Compositions and methods for 3-hydroxypropionate bio-production from biomass |
| US9428778B2 (en) | 2009-09-27 | 2016-08-30 | Cargill, Incorporated | Method for producing 3-hydroxypropionic acid and other products |
| US8809027B1 (en) | 2009-09-27 | 2014-08-19 | Opx Biotechnologies, Inc. | Genetically modified organisms for increased microbial production of 3-hydroxypropionic acid involving an oxaloacetate alpha-decarboxylase |
| JP2013505727A (en) * | 2009-09-27 | 2013-02-21 | オーピーエックス バイオテクノロジーズ， インコーポレイテッド | Process for producing 3-hydroxypropionic acid and other products |
| US8883464B2 (en) | 2009-09-27 | 2014-11-11 | Opx Biotechnologies, Inc. | Methods for producing 3-hydroxypropionic acid and other products |
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| US10100342B2 (en) | 2009-09-27 | 2018-10-16 | Cargill, Incorporated | Method for producing 3-hydroxypropionic acid and other products |
| US9388419B2 (en) | 2009-09-27 | 2016-07-12 | Cargill, Incorporated | Methods for producing 3-hydroxypropionic acid and other products |
| US10465213B2 (en) | 2012-08-10 | 2019-11-05 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
| US9512057B2 (en) | 2013-03-15 | 2016-12-06 | Cargill, Incorporated | 3-hydroxypropionic acid compositions |
| US10047383B2 (en) | 2013-03-15 | 2018-08-14 | Cargill, Incorporated | Bioproduction of chemicals |
| US10155937B2 (en) | 2013-03-15 | 2018-12-18 | Cargill, Incorporated | Acetyl-CoA carboxylases |
| US10815473B2 (en) | 2013-03-15 | 2020-10-27 | Cargill, Incorporated | Acetyl-CoA carboxylases |
| US10337038B2 (en) | 2013-07-19 | 2019-07-02 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
| US11408013B2 (en) | 2013-07-19 | 2022-08-09 | Cargill, Incorporated | Microorganisms and methods for the production of fatty acids and fatty acid derived products |
| CN104035422A (en) * | 2014-06-23 | 2014-09-10 | 中国北方车辆研究所 | Data calculation method based on smart mobile terminal |
| US10494654B2 (en) | 2014-09-02 | 2019-12-03 | Cargill, Incorporated | Production of fatty acids esters |
| CN105657868A (en) * | 2016-01-29 | 2016-06-08 | 努比亚技术有限公司 | Mobile terminal and interface control method thereof |
| US11345938B2 (en) | 2017-02-02 | 2022-05-31 | Cargill, Incorporated | Genetically modified cells that produce C6-C10 fatty acid derivatives |
| CN109413354A (en) * | 2018-11-19 | 2019-03-01 | 天津津航技术物理研究所 | A kind of infrared detector interface adaption device |
| CN109413354B (en) * | 2018-11-19 | 2021-08-06 | 天津津航技术物理研究所 | Infrared detector interface switching device |
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| KR20090026230A (en) | 2009-03-12 |
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