CN101197649A

CN101197649A - Peripheral unit interconnection high speed bus interface and switchboard port testing method and system

Info

Publication number: CN101197649A
Application number: CNA2008100559621A
Authority: CN
Inventors: 李振华
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Fujian Star Net Communication Co Ltd
Priority date: 2008-01-03
Filing date: 2008-01-03
Publication date: 2008-06-11
Anticipated expiration: 2028-01-03
Also published as: CN101197649B

Abstract

The invention relates to a PCIe bus interface bandwidth test method, comprising the followings steps that: the data received by an Ethernet test device line speed is stored into a second memory module by a first network interface module through a first PCIe bus interface and a second PCIe bus interface, or the data in the second memory module is sent out by the first network module through the first network module; a first CPU calculates the data volume received from the Ethernet test device line speed by the first network interface module per unit time or the data volume sent by the first network interface module line speed. The invention also provides a PCIe bus interface performance test method and a PCIe exchange port bandwidth and performance test method. The method provided by the invention overcomes the shortcomings of the prior art and realizes the adoption of the Ethernet test device to test the PCIe bus interface and the bandwidth and performance of the PCIe exchange port.

Description

Peripheral unit interconnection high speed bus interface and switchboard port testing method and system

Technical field

The present invention relates to a kind of bus interface method of testing, relate in particular to a kind of with Ethernet network test equipment test for external devices interconnect bus interface and the bandwidth of switch ports themselves and the method for testing and the system of performance.

Background technology

The interconnected high speed of external equipment (Peripheral Component Interconnect Express, abbreviation PCIe) bus is interconnected (the Peripheral Component Interconnect of external equipment, abbreviation PCI) bus is a kind of, the PCIe bus has been continued to use existing P CI bus programming concept and communication standard, only needs to revise physical layer and need not to revise software and just can be converted to the PCIe system with having pci system now.The PCIe bus adopts transmitting-receiving serial physical layer separately to substitute the parallel physical layer signal of pci bus, and the PCIE bus has faster rate, can replace most existing internal bus.Transfer of data on the PCIe bus is a unit with message (Packet), and the length minimum of message is 1byte, the maximum message segment length difference that distinct device is supported, and the packet maximum length of PCIe normalized definition is 4096bytes.

The connection of PCIe bus is to be based upon on the point-to-point connection basis of a two-way sequence, this is referred to as " transmission channel ", transmit and receive different pieces of information and can use different transmission channels, connection between two PCIe equipment is called " link ", this has formed 1 group or more transmission channel, the link of minimum support 1 transmission channel of each equipment (x1), also can have 2,4,8,16, the link of 32 passages, the PCIe bus interface can be divided into x1 according to the difference of link width between the equipment, x2, x4, x8, x16, this several types of x32, x1 represents to have only a transmission channel, x2 on the PCIe bus interface, x4, x8, x16, the implication of x32 by that analogy.The unidirectional effective bandwidth of the PCIe bus of different link widths as shown in Table 1.Unidirectional effective bandwidth is the maximum bandwidth of having only a direction (Data Receiving direction/data receiver to) to exist data flow to be on the value PCIe bus interface, the maximum bandwidth that two-way effective bandwidth is meant both direction on the PCIe bus interface (Data Receiving direction and data receiver to) all exists data flow to be.

Link width	Unidirectional effective bandwidth
Link width	Unidirectional effective bandwidth	x1	2Gb/s
x2	4Gb/s	x1	2Gb/s
x2	4Gb/s	x4	8Gb/s
x8	16Gb/s	x4	8Gb/s
x8	16Gb/s	x16	32Gb/s
x32	64Gb/s	x16	32Gb/s

Table one

Since the PCIe protocol definition with the similar address space mapping mechanism of PCI, make PCIe equipment to pass through memory device on other devices on memory read/write (Memory Read/Write) the operational access PCIe bus as local memory device.

PCIe switch (PCIe Switch) is a kind of many mouthfuls PCIe switching equipment, and it can realize the transmission of PCIe data flow between two ports.

Smartbit is a kind of ethernet network testing equipment of multiport, it can the various types of Ethernet message datas of linear speed ground transmission/reception, the length of message and content can be at random, and can carry out various statistics and analysis to the message data of transmission/reception.The notion of linear speed is meant that band width in physical on the link reaches 100,000,000 or gigabit in the network test equipment.Band width in physical on the link has comprised two parts at this moment, a part is effective Ethernet data bag, another part comprises some extra expenses (as leading character, frame gap or the like), so the valid data that transmit on the link linear speed time do not reach 100,000,000 or gigabit.For example, in kilomega network, the per second message data that can to transmit 1488095 length be 64 bytes on linear speed transmission time link, actual bandwidth is 1488095 * 64 * 8=761.9Mbps (byte equals 8 bits), as seen actual bandwidth does not reach gigabit, and the remaining bandwidth on the bus has been used for extra expense.

PCIe bus interface method of testing mainly contains two kinds in the prior art:

First method is to use special PCIe bus interface testing equipment to test, and this method can be carried out the test of scientific system to the PCIe bus interface, but cost is than higher.

Second method is to use direct memory access (DMA) (Direct Memory Access is called for short DMA) method, and this method can be tested on the actual maximum bandwidth of PCIe interface simply and easily.But there is deficiency aspect the reliability and stability of test PCIe interface.Because in the time of the reliability and stability of test PCIe interface, need on the PCIe interface, transmit the data of random content random-length for a long time, and the data flow transmitted amount to reach the maximum bandwidth of PCIe interface.Under the dma mode, the PCIe data message of each random content random-length all needs CPU to generate, because the operational capability of CPU is limited, the data traffic of transmitting on the PCIe interface can't reach its maximum bandwidth in this case, so just can not measure the reliability and stability of PCIe interface.

Summary of the invention

The objective of the invention is at the deficiencies in the prior art, a kind of peripheral unit interconnection high speed bus interface and switch ports themselves bandwidth and performance test methods are provided, realize performance and the bandwidth of utilizing existing ethernet network testing equipment to come test for external devices interconnect high speed bus interface and switch ports themselves.

The invention provides a kind of peripheral unit interconnection high speed bus interface bandwidth test method, comprise: first Network Interface Module will store second memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that ethernet network testing equipment linear speed receives, or first Network Interface Module transfers out the data in second memory module by first Network Interface Module;

The data volume that first Network Interface Module receives from described ethernet network testing equipment linear speed in the first CPU unit of account time, or the data volume of described first Network Interface Module linear speed transmission;

Wherein, described first Network Interface Module, first memory module, first CPU and first peripheral unit interconnection high speed bus interface belong to the first peripheral unit interconnection high speed bus equipment, and described second memory module and second peripheral unit interconnection high speed bus interface belong to the second peripheral unit interconnection high speed bus equipment.

The present invention also provides a kind of peripheral unit interconnection high speed bus interface performance test methods, comprising:

First Network Interface Module will store second memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that ethernet network testing equipment linear speed receives, and/or first Network Interface Module transfers out the data in second memory module by the first Network Interface Module linear speed;

Second Network Interface Module will store described first memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that described ethernet network testing equipment receives, and/or second Network Interface Module sends the data in described first memory module by the described second Network Interface Module linear speed;

The data volume that first Network Interface Module receives from described ethernet network testing equipment linear speed in the first CPU unit of account time, and/or the data volume of described first Network Interface Module linear speed transmission;

The data volume that the first peripheral unit interconnection high speed bus interface linear speed receives and/or linear speed sends in the first CPU unit of account time;

The data volume that described second Network Interface Module receives from described ethernet network testing equipment linear speed in the second CPU unit of account time, and/or the data volume of described second Network Interface Module linear speed transmission;

The data volume that the second peripheral unit interconnection high speed bus interface linear speed receives and/or linear speed sends in the second CPU unit of account time;

Based on the above data volume that obtains peripheral unit interconnection high speed bus interface is carried out performance test;

First Network Interface Module, first CPU, first peripheral unit interconnection high speed bus interface, first memory module belong to the first peripheral unit interconnection high speed bus equipment, and second Network Interface Module, second CPU, second peripheral unit interconnection high speed bus interface, second memory module belong to the second peripheral unit interconnection high speed bus equipment.

The present invention also provides a kind of peripheral unit interconnection high speed bus switch ports themselves bandwidth test method, comprising:

The data that the 3rd Network Interface Module will receive from ethernet network testing equipment linear speed store the memory module in one or more all the other peripheral unit interconnection high speed bus equipment the peripheral unit interconnection high speed bus equipment pond into by the port to be tested of peripheral unit interconnection high speed bus switch, or the data in the memory module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond are sent by described the 3rd Network Interface Module linear speed;

The data volume that described the 3rd Network Interface Module receives from ethernet network testing equipment linear speed in the 3rd CPU unit of account time, or the data volume of described the 3rd Network Interface Module linear speed transmission;

Wherein, described the 3rd Network Interface Module, the 3rd CPU belong to the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond, described the 3rd peripheral unit interconnection high speed bus equipment by the peripheral unit interconnection high speed bus switch port and peripheral unit interconnection high speed bus equipment pond in one or more all the other peripheral unit interconnection high speed bus equipment transfering datas.

The present invention also provides a kind of peripheral unit interconnection high speed bus switch ports themselves performance test methods, comprising:

The data that the 3rd Network Interface Module will receive from ethernet network testing equipment linear speed store the memory module in one or more all the other peripheral unit interconnection high speed bus equipment the peripheral unit interconnection high speed bus equipment pond into by the port to be tested of peripheral unit interconnection high speed bus switch, and/or the data in the memory module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond are sent by described the 3rd Network Interface Module linear speed;

Network Interface Module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except described the 3rd peripheral unit interconnection high speed bus equipment will store described the 3rd memory module into from the port to be tested that the data communication device that described ethernet network testing equipment linear speed receives is crossed peripheral unit interconnection high speed bus devices exchange machine respectively, and/or the Network Interface Module that the Network Interface Module in one or more all the other the peripheral unit interconnection high speed bus equipment except described the 3rd peripheral unit interconnection high speed bus equipment is crossed the data communication device in described the 3rd memory module separately in the peripheral unit interconnection high speed bus equipment pond transfers out;

CPU in all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment is each data volume that receives since the network test equipment linear speed in the unit of account time respectively, and/or the unit of account data volume exported of network interface separately in the time respectively of the CPU in one or more all the other the peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond;

CPU in all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment is unit of account separately data volume that the peripheral unit interconnection high speed bus interface linear speed receives and/or linear speed sends in the time respectively;

The data volume that described the 3rd Network Interface Module receives from ethernet network testing equipment linear speed in the 3rd CPU unit of account time, and/or the data volume of described the 3rd Network Interface Module linear speed transmission;

The data volume that described the 3rd peripheral unit interconnection high speed bus interface linear speed receives and/or linear speed sends in the 3rd CPU unit of account time;

Based on the above data volume that obtains the peripheral unit interconnection high speed bus switch ports themselves is carried out performance test;

The 3rd Network Interface Module, the 3rd CPU, the 3rd peripheral unit interconnection high speed bus interface, the 3rd memory module belong to the 3rd peripheral unit interconnection high speed bus equipment.

The present invention also provides a kind of peripheral unit interconnection high speed bus interface bandwidth and Performance Test System, comprising:

The first peripheral unit interconnection high speed bus equipment;

The second peripheral unit interconnection high speed bus equipment;

The ethernet network testing equipment links to each other with the second peripheral unit interconnection high speed bus equipment with the described first peripheral unit interconnection high speed bus equipment respectively, is used to produce message data and the linear speed reception and the linear speed transmission data of random content random-length.

The present invention also provides a kind of peripheral unit interconnection high speed bus switch ports themselves bandwidth and Performance Test System, comprising:

The peripheral unit interconnection high speed bus equipment pond that a plurality of peripheral unit interconnection high speed bus equipment are formed;

The peripheral unit interconnection high speed bus switch, each peripheral unit interconnection high speed bus equipment all links to each other with a port in the peripheral unit interconnection high speed bus switch in the peripheral unit interconnection high speed bus equipment pond;

The ethernet network testing equipment links to each other with each peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond respectively, is used to produce the Ethernet message data of random-length random content and linear speed receives and linear speed transmission data.

The bandwidth of peripheral unit interconnection high speed bus interface provided by the invention and switch ports themselves and performance test methods, having overcome prior art needs the defective of special PCIe bus interface testing equipment, reduced cost, and the message of the random-length random content that the existing Ethernet network test equipment is produced carries out read-write operation, overcome prior art and produced the defective that message is subjected to the restriction of CPU arithmetic speed, realized utilizing existing ethernet network testing equipment that PCIe bus interface and switch ports themselves are carried out bandwidth test and performance test by CPU.

Also in conjunction with the accompanying drawings the present invention is described in further detail below by specific embodiment.

Description of drawings

Figure 1 shows that the present invention carries out the schematic diagram of read/write operation to PCIe equipment;

Figure 2 shows that PCIe bus interface bandwidth of the present invention and Performance Test System embodiment one schematic diagram;

Figure 3 shows that PCIe bus switch machine port bandwidth of the present invention and Performance Test System embodiment one schematic diagram.

Embodiment

The structure of the PCIe equipment among the present invention is: comprise CPU at least, and CPU has a plurality of gigabit mouths, all have 4 gigabit mouths at least as MPC8548, the MPC8572 of Freescale company (Freescale), MPC8641 etc., also comprise at least one PCIe interface.

The related test to the PCIe bus interface comprises the bandwidth test and the performance test of PCIe bus interface among the present invention.Bandwidth test specifically is meant the maximum bandwidth that unidirectional write operation on the PCIe interface, unidirectional read operation, two-way write operation, two-way read operation can reach.Performance test specifically comprises the stability and the reliability testing of PCIe interface transmitting data, has or not packet loss and wrong phenomenon on the test PCIe bus interface when two-way read-write operation all reaches maximum bandwidth on the PCIe bus interface.

Be illustrated in figure 1 as the present invention carries out read/write operation to PCIe equipment schematic diagram, the one PCIe equipment 1 comprises first memory module 11, first CPU (CPU) 12, first Network Interface Module 13 and a PCIe bus interface 14, the 2nd PCIe equipment 2 comprises second memory module 21, second CPU (CPU) 22, second Network Interface Module 23 and the 2nd PCIe bus interface 24, the message that first Network Interface Module 13 in the one PCIe equipment 1 receives is not directly to store first memory module 11 into, but message being dumped to second memory module 21 in the 2nd PCIe equipment 2 by a PCIe bus interface 14 and the 2nd PCIe bus interface 24, the process that the message that a PCIe equipment 1 is received dumps to the 2nd PCIe equipment 2 does not need the participation of first CPU (CPU) 12 and second CPU (CPU) 22.The above operation is called the write operation of 1 pair the 2nd PCIe equipment 2 of a PCIe equipment.

First Network Interface Module 13 in the one PCIe equipment 1 reads message by a PCIe bus interface 14 and the 2nd PCIe bus interface 24 and the message that reads is transferred out by first Network Interface Module 13 from second memory module 21 of the 2nd PCIe equipment 2, a PCIe equipment 1 reads message and the process that message transmissions is gone out do not needed the participation of first CPU (CPU) 12 and second CPU (CPU) 22 from second memory module 22 of the 2nd PCIe equipment 2.The above operation is called the read operation of 1 pair the 2nd PCIe equipment 2 of a PCIe equipment.

Read operation involved in the present invention and write operation all refer to above-described read/write operation, need to prove in addition, when PCIe equipment carries out read or write in the embodiment of the invention, PCIe equipment all PCIe bus interface and Network Interface Module is set to linear speed, so just can receive and send data by linear speed.

Smartbit is a kind of common ethernet test equipment, Smartbit can produce the Ethernet message data of random-length random content and can receive and send data by linear speed, the Ethernet message data that the present invention utilizes the Smartbit network test equipment to produce the random-length random content is tested the performance of PCIe bus interface, overcome prior art and need use the defective of special test equipment, do not need to increase extra cost, and compare with dma mode, the present invention produces message by existing network test equipment, can transmit the performance that also can test transfer of data on the PCIe bus well on the PCIe bus by linear speed.

Be illustrated in figure 2 as PCIe bus interface test system embodiment one schematic diagram of the present invention, the present embodiment system comprises a PCIe equipment 1, the 2nd PCIe equipment 2, and ethernet network testing equipment 3, comprise first memory module 11 in the one PCIe equipment 1, first CPU (CPU) 12, first Network Interface Module 13 and a PCIe bus interface 14, comprise second memory module 21 in the 2nd PCIe equipment 2, second CPU (CPU) 22, second Network Interface Module 23 and the 2nd PCIe bus interface 24, the one PCIe bus interface 14 link to each other with the 2nd PCIe bus interface 24.Need to prove for PCIe bus interface method of testing of the present invention, employed ethernet network testing equipment is not limited to Smartbit, it also can be other existing network test equipment, as NuStream or the like, the above first Network Interface Module 13 and second Network Interface Module 23 are the network interface of the message data that produces with the corresponding reception network test equipment of network test equipment, for example for Smartbit, Network Interface Module is exactly a gigabit ethernet interface.

Peripheral unit interconnection high speed bus interface bandwidth test method of the present invention specifically relates generally to following several aspect:

1, a PCIe equipment carries out the PCIe bus interface bandwidth test method of unidirectional write operation to the 2nd PCIe equipment;

2, a PCIe equipment carries out the PCIe bus interface bandwidth test method of unidirectional read operation to the 2nd PCIe equipment;

3, PCIe equipment and the 2nd PCIe equipment carry out the PCIe bus interface bandwidth test method of two-way write operation;

4, PCIe equipment and the 2nd PCIe equipment carry out the PCIe bus interface bandwidth test method of two-way read operation.

Be that example explanation the present invention is based on test macro shown in Figure 2 with the Smartbit network test equipment below, more than the concrete principle of four aspect method of testings.

1, for Smartbit, first Network Interface Module and second Network Interface Module are gigabit ethernet interface.The maximum bandwidth of the single gigabit ethernet interface of existing C PU is no more than 1Gb/s, and PCIe bus effective bandwidth under the x1 situation just can reach 2Gb/s, so CPU has 3 gigabit ethernet interfaces in the present embodiment system requirements PCIe equipment, PCIe equipment can be initiated the write operation of 1x3=Gb/s like this, and can only test the PCIe bus interface of x1 type, if the PCIe bus interface of test other types, then require the quantity of the gigabit ethernet interface of increase CPU, can reach linear speed in the time of could guaranteeing when having only bandwidth that the CPU gigabit Ethernet receives data the PCIe bus interface tested and transmit the maximum data bandwidth that reality can be transmitted on the aptitude test PCIe bus interface greater than the effective bandwidth of PCIe.

At first, 3 gigabit ethernet interfaces in the one PCIe equipment receive the Ethernet message from Smartbit, because PCIe provides the address space mapping mechanism, the one PCIe equipment can directly be visited second memory module in the 2nd PCIe equipment by a PCIe bus interface and the 2nd PCIe bus interface, so the message data that 3 gigabit ethernet interfaces of a PCIe equipment receive stores second memory module in the 2nd PCIe equipment into by a PCIe bus interface and the 2nd PCIe bus interface, the data traffic that the one PCIe equipment receives the Ethernet message equals a PCIe equipment carries out flow from write operation to the 2nd PCIe equipment, the message data flow that receives from Smartbit in the CPU statistical test time in the PCIe equipment can obtain a PCIe equipment to the bandwidth of the 2nd PCIe tables of equipment to write operation with this flow divided by the testing time then.Concrete computational methods are as follows:

B＝(N*L*8)/t (1)

Wherein B be a PCIe equipment to the 2nd PCIe tables of equipment to the write operation bandwidth, unit is Mbps; N is the Ethernet message number that receives in the testing time; L is the length of Ethernet message, and unit is byte; T is the testing time, and unit is s; Because 1byte=8bit, just can obtain in the testing time t data quantity transmitted on the PCIe bus interface so the length of N message need be multiply by 8 in the formula (1) during computation bandwidth.

2, the one PCIe equipment is specially the PCIe bus interface bandwidth test method that the 2nd PCIe equipment carries out unidirectional read operation: the gigabit ethernet interface in the PCIe equipment is according to address spatial mappings mechanism, directly the data in second memory module in the 2nd PCIe equipment are transferred out from the gigabit ethernet interface of a PCIe equipment, the data traffic that the one CPU statistics of the one PCIe equipment is exported from the gigabit ethernet interface of a PCIe equipment just can obtain the bandwidth that a PCIe equipment carries out unidirectional read operation to the 2nd PCIe equipment divided by the testing time then.Computational methods and formula (1) are similar, repeat no more herein.

More than 1, in 2 two described methods because a PCIe equipment might obliterated data on a PCIe bus interface and the 2nd PCIe bus interface in the process of carrying out write/read operation to the 2nd PCIe equipment, so in order to test a PCIe equipment more accurately in the bandwidth of carrying out write/read operation to the 2nd PCIe equipment, the 2nd CPU in the 2nd PCIe equipment is the interior data volume from the 2nd PCIe bus interface reception/output of statistical test time t simultaneously, then the data volume that receives/export from first Network Interface Module from Smartbit in the testing time of the data volume of the 2nd CPU statistics and CPU statistics is compared, if the two equates, illustrate that then this data volume is exactly the maximum amount of data that a PCIe equipment transmits in the testing time when the 2nd PCIe equipment carries out write/read operation, otherwise think and in the process of transfer of data, mistake occurred.

3, the PCIe bus interface bandwidth test method that the one PCIe equipment and the 2nd PCIe equipment carry out two-way write operation is: the message data that 3 gigabit ethernet interfaces of a PCIe equipment receive stores second memory module in the 2nd PCIe equipment into by a PCIe bus interface and the 2nd PCIe bus interface, simultaneously the message data that receives of 3 gigabit ethernet interfaces of the 2nd PCIe equipment stores first memory module in the PCIe equipment into by a PCIe bus interface and the 2nd PCIe bus interface, the data traffic that receives from Smartbit in the one CPU statistical test time of the one PCIe equipment, the data traffic that receives from Smartbit in the 2nd CPU statistical test time of the 2nd PCIe equipment, the PCIe equipment that calculates respectively then is to the bandwidth of the 2nd PCIe equipment write operation and the 2nd PCIe equipment bandwidth to a PCIe equipment write operation, and sum of the two promptly is the bandwidth that PCIe equipment and the 2nd PCIe equipment carry out two-way write operation.

4, the PCIe bus interface bandwidth test method that the one PCIe equipment and the 2nd PCIe equipment carry out two-way read operation is: the gigabit ethernet interface in the PCIe equipment is according to address spatial mappings mechanism, directly the data in second memory module in the 2nd PCIe equipment are transferred out from the gigabit ethernet interface of a PCIe equipment, gigabit ethernet interface in the 2nd PCIe equipment is according to address spatial mappings mechanism simultaneously, directly the data in first memory module in the PCIe equipment are transferred out from the gigabit ethernet interface of the 2nd PCIe equipment, the data traffic of exporting from the gigabit ethernet interface of a PCIe equipment in the one CPU statistical test time of the one PCIe equipment, the data traffic of exporting from the gigabit ethernet interface of the 2nd PCIe equipment in the 2nd CPU statistical test time of the 2nd PCIe equipment, the PCIe equipment that calculates respectively then is to the bandwidth of the 2nd PCIe equipment read operation and the 2nd PCIe equipment bandwidth to a PCIe equipment read operation, and sum of the two promptly is the bandwidth that PCIe equipment and the 2nd PCIe equipment carry out two-way read operation.

More than 3, carry out in the process of two-way read/write operation on a PCIe interface and the 2nd PCIe interface might obliterated data for PCIe equipment and the 2nd PCIe equipment in 4 two described methods, the one CPU not only will add up the data volume of I/O on the gigabit ethernet interface of a PCIe equipment, also to add up the data volume of I/O on the PCIe interface, and the 2nd CPU needs the data volume of I/O on the data volume of I/O on the gigabit ethernet interface of the 2nd PCIe equipment of adding up and the 2nd PCIe interface too, the data volume of I/O on the gigabit ethernet interface that the data volume that the 2nd PCIe of the 2nd CPU statistics is gone up I/O in the testing time and a CPU add up is compared, if equate, illustrate that then the loss of data phenomenon does not appear in data transmission procedure, otherwise, illustrate that transfer of data is undesired; The data volume of I/O on the gigabit ethernet interface that the data volume that simultaneously a PCIe of CPU statistics is gone up I/O in the testing time and the 2nd CPU add up is compared, if equate, illustrate that then the loss of data phenomenon does not appear in data transmission procedure, otherwise, illustrate that transfer of data is undesired.

The above method produces the Ethernet message by Smartbit, according to PCIe address space mapping mechanism, visit the method for the memory module of another PCIe equipment by the gigabit ethernet interface of a PCIe equipment, count the data traffic that receives on the PCIe equipment gigabit ethernet interface or export and to calculate the data bandwidth that transmits on the PCIe bus interface, simultaneously can also carry out the test of two-way read-write operation data bandwidth, overcome prior art and need use special PCIe bus interface testing equipment to test the method for bandwidth, provided cost savings.

Be illustrated in figure 3 as PCIe switch ports themselves bandwidth of the present invention and Performance Test System embodiment one schematic diagram, the present embodiment system comprises a plurality of PCIe equipment and PCIe switch, each PCIe equipment connects in the PCIe switch ports themselves, a plurality of PCIe equipment are formed " PCIe equipment pond ", problem for convenience of explanation, only draw among Fig. 3 four PCIe equipment and four PCIe ports, but more PCIe equipment and PCIe port can be arranged in actual applications.As shown in Figure 3, four ports of PCIe switch 8 are connected with four PCIe equipment respectively, PCIe bus interface 14 in the one PCIe equipment 1 connects first port 81, the 2nd PCIe bus interface in the 2nd PCIe equipment 2 connects second port 82, the 3rd PCIe bus interface in the 3rd PCIe equipment 6 connects the 3rd port 83, the 4th PCIe bus interface in the 4th PCIe equipment 7 connects the 4th port 84, each PCIe equipment includes memory module, CPU Network Interface Module and PCIe bus interface, and four PCIe equipment are formed PCIe equipment pond 4.The present embodiment system also comprises ethernet network testing equipment 3.

Peripheral unit interconnection high speed bus switch ports themselves bandwidth test method of the present invention specifically relates generally to following several aspect:

1, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out the method for testing of unidirectional read operation bandwidth simultaneously to a PCIe equipment;

2, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out the method for testing of unidirectional write operation bandwidth simultaneously to a PCIe equipment;

3, PCIe equipment and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out the bandwidth of two-way write operation, just the bandwidth test of the two-way write operation on first port in the PCIe switch;

4, PCIe equipment and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment bandwidth of carrying out two-way read operation, the just bandwidth test of the two-way read operation on first port in the PCIe switch.

Be that Smartbit is that example illustrates in the system of Fig. 3 how PCIe switch single port is carried out above four kinds of tests with the ethernet network testing equipment below.

1, the Network Interface Module in each PCIe equipment is corresponding with Smartbit among Fig. 3 should be gigabit ethernet interface.The method of the unidirectional write operation bandwidth of test PCIe switch first port is: the effective bandwidth of the PCIe bus of x1 type is 2Gb/s, the effective bandwidth of the PCIe bus of x4 type is 8Gb/s, each PCI equipment has 3 gigabit ethernet interfaces in the PCIe equipment pond, the maximum data bandwidth that can transmit on each PCI equipment is 3Gb/s, if the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out write operation to a PCIe equipment simultaneously, the maximum data bandwidth that can transmit on PCIe switch first port is 3 * 3=9Gb/s so, so the present embodiment method can be tested x1, the data bandwidth that transmits on the PCIe bus of x4 type.The 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment receives the Ethernet message data from Smartbit simultaneously, the gigabit ethernet interface of these three equipment is simultaneously with first memory module in storage to the PCIe equipment that receives, the 2nd CPU in the 2nd PCIe equipment adds up the message data amount that the kilomega network interface in the 2nd PCIe equipment receives in the testing time, the 3rd CPU in the 3rd PCIe equipment adds up the message data amount that the kilomega network interface in the 3rd PCIe equipment receives in the testing time, the 4th CPU in the 4th PCIe equipment adds up the message data amount that the kilomega network interface in the 4th PCIe equipment receives in the testing time, then these three data volume sums can be drawn the data bandwidth on PCIe switch first port in the testing time, just the 2nd PCIe equipment divided by the testing time, the 3rd PCIe equipment, the unidirectional write operation bandwidth that the 4th PCIe equipment carries out to a PCIe equipment simultaneously.

2, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment while is specially to the method for testing that a PCIe equipment carries out unidirectional read operation bandwidth: the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment is read message data through first memory module of first port from a PCIe equipment simultaneously, and respectively from the 2nd PCIe equipment, the 3rd PCIe equipment, export in the gigabit ethernet interface in the 4th PCIe equipment, the 2nd CPU in the 2nd PCIe equipment adds up the message data amount that the kilomega network interface in the 2nd PCIe equipment is exported in the testing time, the 3rd CPU in the 3rd PCIe equipment adds up the message data amount that the kilomega network interface in the 3rd PCIe equipment is exported in the testing time, the 4th CPU in the 4th PCIe equipment adds up the message data amount that the kilomega network interface in the 4th PCIe equipment is exported in the testing time, then these three data volume sums can be drawn the data bandwidth on PCIe switch first port in the testing time, just the 2nd PCIe equipment divided by the testing time, the 3rd PCIe equipment, the unidirectional read operation bandwidth that the 4th PCIe equipment carries out to a PCIe equipment simultaneously.

Because the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out in the process of unidirectional read/write operation might obliterated data on the PCIe of each PCIe equipment port or on the port of PCIe switch to a PCIe equipment simultaneously, so PCIe equipment, the 2nd PCIe equipment, the 3rd PCIe equipment, the CPU of the 4th PCIe equipment needs in the statistical test time simultaneously the data volume of I/O on the data volume of I/O on the gigabit ethernet interface separately and the PCIe bus interface separately, data volume and the 2nd PCIe equipment with the PCIe interface I/O of the CPU of PCIe equipment statistics, the 3rd PCIe equipment, in the testing time of the CPU of the 4th PCIe equipment statistics on the gigabit ethernet interface separately the data volume sum of I/O compare, if the two equates, illustrate that then transfer of data is normal on PCIe bus interface and the PCIe switch ports themselves, otherwise, think that then transfer of data is undesired.

3, the one PCIe equipment is simultaneously to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out write operation, and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out write operation to a PCIe equipment simultaneously, the CPU of these four PCIe equipment distinguishes the Ethernet message data amount that receives from Smartbit in the statistical test time then, these four data volume sums can be drawn PCIe equipment and the 2nd PCIe equipment divided by the testing time, the 3rd PCIe equipment, the 4th PCIe equipment carries out the bandwidth of two-way write operation, just the bandwidth of the two-way write operation on first port in the PCIe switch.

4, the one PCIe equipment is simultaneously to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out read operation, and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out read operation to a PCIe equipment simultaneously, the Ethernet message data amount exported from kilomega network interface separately in the statistical test time respectively of the CPU of these four PCIe equipment then, these four data volume sums can be drawn PCIe equipment and the 2nd PCIe equipment divided by the testing time, the 3rd PCIe equipment, the bandwidth that the 4th PCIe equipment carries out two-way read operation, the just bandwidth of the two-way read operation on first port in the PCIe switch.

Because the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out unidirectional read/write operation and the 2nd PCIe equipment to a PCIe equipment simultaneously, the 3rd PCIe equipment, the 4th PCIe equipment and a PCIe equipment carry out in the process of economic benefits and social benefits read/write operation might obliterated data on the PCIe of each PCIe equipment port or on the port of PCIe switch, so PCIe equipment, the 2nd PCIe equipment, the 3rd PCIe equipment, the CPU of the 4th PCIe equipment needs in the statistical test time simultaneously the data volume of input and output on the data volume of input and output on the gigabit ethernet interface separately and the PCIe bus interface separately, with in the testing time of CPU statistics from the kilomega network interface of a PCIe equipment the data volume and the 2nd CPU of input and output, the 3rd CPU, in the testing time of the 4th CPU statistics on separately the PCIe bus interface data volume sum of input and output compare, if the two equates, illustrate that then transfer of data is normal on PCIe bus interface and the PCIe switch ports themselves, otherwise, think that then transfer of data is undesired; Also need the data volume sum of input and output on separately the gigabit ethernet interface in the testing time that the data volume of input and output and the 2nd CPU, the 3rd CPU, the 4th CPU add up on the PCIe bus interface in the testing time of CPU statistics is compared, if the two equates, illustrate that then transfer of data is normal on PCIe bus interface and the PCIe switch ports themselves, otherwise, think that then transfer of data is undesired.

From the above PCIe bus interface test system that comprises the PCIe switch in the method for testing of single port as can be seen, as long as remove in the PCIe equipment pond to PCIe equipment that port to be tested in the PCIe switch is connected the bandwidth sum of all the other PCIe equipment Ethernet message data that can receive simultaneously or export greater than the effective width of PCIe bus, just can realize treating the bandwidth test of test port.Require to remove in the PCIe equipment pond to PCIe equipment that port to be tested in the PCIe switch is connected the bandwidth sum of all the other PCIe equipment Ethernet message data that can receive simultaneously or export greater than the effective width of PCIe bus, be to transmit in order to make the data of transmitting on the single port in the PCIe switch can reach linear speed.More specifically, supposing has n PCIe equipment in the PCIe pond, and the Ethernet message data bandwidth that each PCIe equipment can receive or export is Z ₁, the effective bandwidth of PCIe bus is Z ₀, if the some ports in the PCIe switch are carried out bandwidth test, if all the other m PCIe equipment data bandwidth sum of receiving simultaneously or exporting is Z so ₁* m needs only Z ₁* m is greater than Z ₀, just can test this port, the value of m is less than or equal to n-1.

For example, if 5 PCIe equipment are arranged in the PCIe pond, so if first port is wherein tested, if the type of PCIe bus is x1, so only need a PCIe equipment pair PCIe equipment that links to each other with port to be tested in the PCIe pond to carry out the bandwidth that read or write just can be tested this port, if it is also passable simultaneously the PCIe equipment that links to each other with port to be tested to be carried out read or write with all the other four PCIe equipment.If the type of PCIe bus is x4, so only need that all the other 3 PCIe equipment pair PCIe equipment that links to each other with port to be tested carries out the bandwidth that read or write just can be tested this port in the PCIe pond, if it is also passable simultaneously the PCIe equipment that links to each other with port to be tested to be carried out read or write with all the other four PCIe equipment.

More than in the system that contains the PCIe switch, by in the PCIe equipment pond except that with PCIe equipment that port to be tested is connected all the other PCIe equipment pair PCIe equipment that is connected with port to be tested carry out unidirectional or two-way read/write operation, realization is to the bandwidth test of single port in the PCIe switch, need not special testing equipment, provide cost savings.

The invention still further relates to performance test to the PCIe bus interface.For system as shown in Figure 2, the method of the PCIe bus interface being carried out performance test is specially: a PCIe equipment carries out the read and write operation to the 2nd PCIe equipment, the 2nd PCIe equipment carries out the read and write operation to a PCIe equipment simultaneously, and the CPU statistics in the PCIe equipment is from the gigabit ethernet interface reception of a PCIe equipment and the data volume A of output ₅', the 2nd CPU statistics in the 2nd PCIe equipment is from the 2nd PCIe bus interface reception of the 2nd PCIe equipment and the data volume B of output ₅', the 2nd CPU statistics in the 2nd PCIe equipment is from the gigabit ethernet interface reception of the 2nd PCIe equipment and the data volume B of output simultaneously ₆', the CPU statistics in the PCIe equipment is from the PCIe bus interface reception of a PCIe equipment and the data volume A of output ₆', if A ₅'=B ₅' and A ₆'=B ₆', illustrate that mistake does not appear in PCIe bus interface data transmission channel; If A ₅'=B ₅' and A ₆'=B ₆' have any one unequal in these two equatioies, illustrate that then mistake appears in PCIe bus interface data transmission channel.The read-write operation that the one PCIe equipment and the 2nd PCIe equipment carry out all is long.

The method of the PCIe bus interface being carried out performance test can also be:

The one PCIe equipment carries out unidirectional write operation to the 2nd PCIe equipment, the data volume A that first gigabit ethernet interface receives from ethernet network testing equipment linear speed in the unit interval that a CPU is calculated ₁' the 2nd PCIe interface linear speed receives in unit interval of calculating with the 2nd CPU data volume B ₁' compare;

The one PCIe equipment carries out unidirectional read operation to the 2nd PCIe equipment, with the data volume A of first gigabit ethernet interface linear speed transmission in the unit interval of CPU calculating ₂' the 2nd PCIe interface linear speed sends in unit interval of calculating with the 2nd CPU data volume B ₂' compare;

The one PCIe equipment and the 2nd PCIe equipment carry out two-way write operation, with the data volume A of second gigabit ethernet interface in the unit interval of the 2nd CPU calculating from described ethernet network testing equipment linear speed reception ₃' a PCIe interface receives in unit interval of calculating with a CPU data volume B ₃' compare; The data volume A that first gigabit ethernet interface receives from ethernet network testing equipment linear speed in the unit interval that a CPU is calculated simultaneously ₁' the 2nd PCIe interface linear speed receives in unit interval of calculating with the 2nd CPU data volume B ₁' compare;

The one PCIe equipment and the 2nd PCIe equipment carry out two-way read operation, with the data volume A of the 2nd PCIe interface transmission in the unit interval of the 2nd CPU calculating ₄' described first gigabit ethernet interface sends in unit interval of calculating with a CPU data volume B ₄' compare; The data volume A that the first gigabit ethernet interface linear speed sends in the unit interval that a CPU is calculated simultaneously ₂' the 2nd PCIe interface linear speed sends in unit interval of calculating with the 2nd CPU data volume B ₂' compare;

The one PCIe equipment and the 2nd PCIe equipment carry out two-way read and write operation, with the data volume A of first gigabit ethernet interface in the unit interval of CPU calculating from described ethernet network testing equipment reception and transmission ₅The data volume B that the 2nd PCIe interface receives and sends in the unit interval of calculating with the 2nd CPU ₅Compare; The data volume A that second gigabit ethernet interface receives and sends from described ethernet network testing equipment in the unit interval that the 2nd CPU is calculated simultaneously ₆The data volume B that a PCIe interface receives and sends in the unit interval of calculating with a CPU ₆Compare;

If following five kinds of conditions all satisfy,

a、A ₁’＝B ₁’；

b、A ₂’＝B ₂’；

C, A ₁'=B ₁' and A ₃'=B ₃';

D, A ₂'=B ₂' and A ₄'=B ₄';

E, A ₅'=B ₅' and A ₆'=B ₆';

Judge that then transfer of data is normal between PCIe equipment and the 2nd PCIe equipment; Otherwise judge that mistake appears in transfer of data between PCIe equipment and the 2nd PCIe equipment.

In the prior art performance test of PCIe interface is based on that transfer of data has reached maximum bandwidth on the PCIe interface, in the present embodiment, owing to receive and the transmission data for linear speed on the PCIe interface, so can on the basis of PCIe interface bandwidth test, carry out the performance test of PCIe interface, in the present embodiment on the PCIe bus interface bidirectional data transfers all reach maximum bandwidth, the message data of the random-length random content that Smartibit is produced transmits operation for a long time, whether the transfer of data on the test PCIe bus interface is wrong, overcome the defective that is subjected to the restriction of CPU operating rate when the method CPU of prior art by dma mode test PCIe bus interface performance produces the message of random-length random content.

For system as shown in Figure 3, to single port in the PCIe switch carry out performance test method can for: a PCIe equipment is simultaneously to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out the read and write operation, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carries out the read and write operation to a PCIe equipment simultaneously, these four PCIe equipment CPU separately add up the data volume that the data volume that receives and send from separately Ethernet interface and PCIe bus interface separately receive and send respectively, if the data quantity C that receives and send on first Ethernet interface of a CPU of PCIe equipment statistics ₅' equal the data volume sum D that receives and send on the PCIe bus interface separately of the 2nd PCIe equipment, the 3rd PCIe equipment and the 4th PCIe equipment CPU statistics separately ₅', if the C such as data volume that receive and send on the PCIe bus interface of the CPU statistics of while the one PCIe equipment ₆' the data volume sum D that on the Ethernet interface separately of the 2nd PCIe equipment, the 3rd PCIe equipment and the 4th PCIe equipment CPU statistics separately, receives and send ₆', transfer of data does not have mistake on the PCIe switch port to be tested so; If C ₅'=D ₅' and C ₆'=D ₆' have any one to be false in these two equatioies, illustrate that then mistake appears in transfer of data on the PCIe switch port to be tested.The read and write operation that the one PCIe equipment, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out is long.

The method of single port in the PCIe switch being carried out performance test can also be:

The one PCIe equipment carries out write operation to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, the data quantity C that gigabit ethernet interface receives from the ethernet network testing equipment in the unit interval that the 3rd CPU is calculated ₁, the data volume sum D that separately PCIe interface receives in the unit interval of calculating respectively with the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment CPU separately ₁Compare;

The one PCIe equipment carries out read operation to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, the data quantity C that described gigabit ethernet interface sends in the unit interval with the 3rd CPU calculating ₂, the data volume sum D that separately PCIe interface sends in the unit interval of calculating respectively with the CPU separately of the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment ₂Compare;

The one PCIe equipment carries out write operation to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, simultaneously the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out write operation to a PCIe equipment, with the CPU separately of the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment unit of account each data volume sum C that receives since network test equipment in the time respectively ₃, the data volume D that the 3rd PCIe interface receives in the unit interval of calculating with the 3rd CPU ₃Compare; And the data quantity C that gigabit ethernet interface receives from the ethernet network testing equipment in the unit interval that the 3rd CPU is calculated ₁, the data volume sum D1 that separately PCIe interface receives in the unit interval of calculating respectively with the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment CPU separately compares;

The one PCIe equipment carries out read operation to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, simultaneously the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out read operation to a PCIe equipment, separately the data volume sum C of PCIe interface transmission in the unit interval that the CPU in all the other PCIe equipment except that described the 3rd PCIe equipment in the PCIe equipment pond is calculated respectively ₄, the data volume D that described the 3rd gigabit ethernet interface sends in the unit interval of calculating with the 3rd CPU ₄Compare; And the data quantity C that described gigabit ethernet interface sends in the unit interval with the 3rd CPU calculating ₂, the data volume sum D that separately PCIe interface sends in the unit interval of calculating respectively with the CPU separately of the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment ₂Compare;

The one PCIe equipment carries out the read and write operation to the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment carry out the read and write operation to a PCIe equipment simultaneously, with the data quantity C of gigabit ethernet interface in the unit interval of the 3rd CPU calculating from reception of ethernet network testing equipment and transmission ₅, the data volume sum that separately PCIe interface receives and sends in the unit interval of calculating respectively with the CPU separately of the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment and D ₅Compare; And in the unit interval that the CPU separately of the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment is calculated respectively each data volume sum that receives and send since network test equipment and C ₆, the data volume D that the 3rd PCIe interface receives and sends in the unit interval of calculating with the 3rd CPU ₆Compare;

If following five kinds of conditions all satisfy,

a、C ₁’＝D ₁’；

b、C ₂’＝D ₂’；

C, C ₁'=D ₁' and C ₃'=D ₃';

D, C ₂'=D ₂' and C ₄'=D ₄';

E, C ₅'=D ₅' and C ₆'=D ₆';

Judge that then transfer of data is normal between the 3rd PCIe equipment and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment, otherwise, judge that transfer of data makes a mistake between the 3rd PCIe equipment and the 2nd PCIe equipment, the 3rd PCIe equipment, the 4th PCIe equipment.

The method that the embodiment of the invention provides to PCIe bus port bandwidth and performance test, having overcome prior art needs the defective of special PCIe bus interface testing equipment, reduced cost, and the message of the random-length random content that the existing Ethernet network test equipment is produced carries out read-write operation, overcome prior art and produced the defective that message is subjected to the restriction of CPU arithmetic speed, realized utilizing existing ethernet network testing equipment that the PCIe bus interface is carried out bandwidth test and performance test by CPU.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims

1. peripheral unit interconnection high speed bus interface bandwidth test method, it is characterized in that, comprise: first Network Interface Module will store second memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that ethernet network testing equipment linear speed receives, or first Network Interface Module sends the data in second memory module by the first Network Interface Module linear speed;

2. peripheral unit interconnection high speed bus interface bandwidth test method according to claim 1, it is characterized in that, first Network Interface Module will store second memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that ethernet network testing equipment linear speed receives, when first Network Interface Module is from data volume that described ethernet network testing equipment linear speed receives in the first CPU unit of account time, also comprise:

Second Network Interface Module will store described first memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that described ethernet network testing equipment linear speed receives;

The data volume that described second Network Interface Module receives from described ethernet network testing equipment linear speed in the second CPU unit of account time;

Described second Network Interface Module, second CPU belong to the second peripheral unit interconnection high speed bus equipment.

3. peripheral unit interconnection high speed bus interface bandwidth test method according to claim 1, it is characterized in that, first Network Interface Module sends the data in second memory module by second peripheral unit interconnection high speed bus interface, first peripheral unit interconnection high speed bus interface, the first Network Interface Module linear speed, during the described first Network Interface Module linear speed sends in the first CPU unit of account time data volume, also comprise:

Second Network Interface Module sends the data in described first memory module by the described second Network Interface Module linear speed;

The data volume that the described second Network Interface Module linear speed sends in the second CPU unit of account time;

Wherein, described second Network Interface Module, second CPU belong to the second peripheral unit interconnection high speed bus equipment.

4. a peripheral unit interconnection high speed bus interface performance test methods is characterized in that, comprising:

First Network Interface Module will store second memory module into by first peripheral unit interconnection high speed bus interface and second peripheral unit interconnection high speed bus interface from the data that ethernet network testing equipment linear speed receives, and/or first Network Interface Module sends the data in second memory module by the first Network Interface Module linear speed;

5. peripheral unit interconnection high speed bus interface performance test methods according to claim 4, it is characterized in that, also comprise: with the data volume A of first Network Interface Module in the unit interval of first CPU calculating from described ethernet network testing equipment linear speed reception and linear speed transmission ₅The second peripheral unit interconnection high speed bus interface linear speed receives and the data volume B of linear speed transmission in the unit interval of calculating with second CPU ₅Compare;

With the data volume A of second Network Interface Module in the unit interval of second CPU calculating from described ethernet network testing equipment linear speed reception and linear speed transmission ₆The first peripheral unit interconnection high speed bus interface linear speed receives and the data volume B of linear speed transmission in the unit interval of calculating with first CPU ₆Compare;

If A ₅=B ₅And A ₆=B ₆, judge that then transfer of data is normal between the first peripheral unit interconnection high speed bus equipment and the second peripheral unit interconnection high speed bus equipment; Otherwise judge that mistake appears in transfer of data between the first peripheral unit interconnection high speed bus equipment and the second peripheral unit interconnection high speed bus equipment.

6. peripheral unit interconnection high speed bus interface performance test methods according to claim 4 is characterized in that, also comprises:

First Network Interface Module, first CPU, first peripheral unit interconnection high speed bus interface, first memory module belong to the first peripheral unit interconnection high speed bus equipment, and second Network Interface Module, second CPU, second peripheral unit interconnection high speed bus interface, second memory module belong to the second peripheral unit interconnection high speed bus equipment;

With the data volume A of first Network Interface Module in the unit interval of first CPU calculating from described ethernet network testing equipment linear speed reception ₁The data volume B that the second peripheral unit interconnection high speed bus interface linear speed receives in the unit interval of calculating with second CPU ₁Compare;

Data volume A with first Network Interface Module linear speed transmission in the unit interval of first CPU calculating ₂The data volume B that the second peripheral unit interconnection high speed bus interface linear speed sends in the unit interval of calculating with second CPU ₂Compare;

With the data volume A of second Network Interface Module in the unit interval of second CPU calculating from described ethernet network testing equipment linear speed reception ₃The data volume B that the first peripheral unit interconnection high speed bus interface linear speed receives in the unit interval of calculating with first CPU ₃Compare;

Data volume A with second peripheral unit interconnection high speed bus interface linear speed transmission in the unit interval of second CPU calculating ₄The data volume B that the described first Network Interface Module linear speed sends in the unit interval of calculating with first CPU ₄Compare;

With the data volume A of first Network Interface Module in the unit interval of first CPU calculating from described ethernet network testing equipment linear speed reception and linear speed transmission ₅The second peripheral unit interconnection high speed bus interface linear speed receives and the data volume B of linear speed transmission in the unit interval of calculating with second CPU ₅Compare;

If following five kinds of conditions all satisfy,

a、A ₁＝B ₁；

b、A ₂＝B ₂；

C, A ₁=B ₁And A ₃=B ₃

D, A ₂=B ₂And A ₄=B ₄

E, A ₅=B ₅And A ₆=B ₆

Judge that then transfer of data is normal between the first peripheral unit interconnection high speed bus equipment and the second peripheral unit interconnection high speed bus equipment; Otherwise judge that mistake appears in transfer of data between the first peripheral unit interconnection high speed bus equipment and the second peripheral unit interconnection high speed bus equipment.

7. a peripheral unit interconnection high speed bus switch ports themselves bandwidth test method is characterized in that, comprising:

8. peripheral unit interconnection high speed bus switch ports themselves bandwidth test method according to claim 7, it is characterized in that, when the to be tested port of the data that the 3rd Network Interface Module will receive from ethernet network testing equipment linear speed by the peripheral unit interconnection high speed bus switch stores the peripheral unit interconnection high speed bus equipment pond memory module in one or more all the other peripheral unit interconnection high speed bus equipment into, also comprise:

The data that Network Interface Module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment will receive from described ethernet network testing equipment linear speed respectively store described the 3rd memory module into by the port to be tested of peripheral unit interconnection high speed bus devices exchange machine;

CPU in all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment is interior each data volume that receives since the network test equipment linear speed of unit of account time respectively.

9. peripheral unit interconnection high speed bus switch ports themselves bandwidth test method according to claim 7, it is characterized in that, when the data in the memory module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond are sent by described the 3rd Network Interface Module linear speed, also comprise:

Network Interface Module in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment transfers out the Network Interface Module of the data in described the 3rd memory module by separately;

CPU in one or more all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment is unit of account data volume of Network Interface Module output separately in the time respectively.

10. a peripheral unit interconnection high speed bus switch ports themselves performance test methods is characterized in that, comprising:

CPU in all the other peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond except that described the 3rd peripheral unit interconnection high speed bus equipment is each data volume that receives since the network test equipment linear speed in the unit of account time respectively, and/or the unit of account data volume of Network Interface Module linear speed transmission separately in the time respectively of the CPU in one or more all the other the peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond;

11. peripheral unit interconnection high speed bus switch ports themselves performance test methods according to claim 10 is characterized in that, also comprises:

With the data quantity C of described the 3rd Network Interface Module in the unit interval of the 3rd CPU calculating from reception of ethernet network testing equipment linear speed and linear speed transmission ₅, in the unit interval of calculating respectively with the CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond separately peripheral unit interconnection high speed bus interface linear speed receive and the data volume sum of linear speed transmission and D ₅Compare;

In the unit interval that CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond is calculated respectively each since the network test equipment linear speed receive and the data volume sum of linear speed transmission and C ₆, the 3rd peripheral unit interconnection high speed bus interface linear speed receives and the data volume D of linear speed transmission in the unit interval of calculating with the 3rd CPU ₆Compare;

If C ₅=D ₅And C ₆=D ₆Judge then in the 3rd peripheral unit interconnection high speed bus equipment and the peripheral unit interconnection high speed bus equipment pond that transfer of data is normal between all the other one or more peripheral unit interconnection high speed bus equipment, otherwise, judge in the 3rd peripheral unit interconnection high speed bus equipment and the peripheral unit interconnection high speed bus equipment pond that transfer of data makes a mistake between all the other one or more peripheral unit interconnection high speed bus equipment.

12. peripheral unit interconnection high speed bus switch ports themselves performance test methods according to claim 10 is characterized in that, also comprises:

The 3rd Network Interface Module, the 3rd CPU, the 3rd peripheral unit interconnection high speed bus interface, the 3rd memory module belong to the 3rd peripheral unit interconnection high speed bus equipment;

The data quantity C that described the 3rd Network Interface Module receives from ethernet network testing equipment linear speed in the unit interval that the 3rd CPU is calculated ₁, the data volume sum D that separately peripheral unit interconnection high speed bus interface linear speed receives in the unit interval of calculating respectively with the CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond ₁Compare;

The data quantity C that described the 3rd Network Interface Module linear speed sends in unit interval with the calculating of the 3rd CPU ₂, the data volume sum D that separately peripheral unit interconnection high speed bus interface linear speed sends in the unit interval of calculating respectively with the CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond ₂Compare;

Each data volume sum C that receives since the network test equipment linear speed in the unit interval that CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond is calculated respectively ₃, the data volume D that the 3rd peripheral unit interconnection high speed bus interface linear speed receives in the unit interval of calculating with the 3rd CPU ₃Compare;

The data volume sum C that separately peripheral unit interconnection high speed bus interface linear speed sends in the unit interval that CPU in all the other peripheral unit interconnection high speed bus equipment except that described the 3rd peripheral unit interconnection high speed bus equipment in the peripheral unit interconnection high speed bus equipment pond is calculated respectively ₄, the data volume D that described the 3rd Network Interface Module linear speed sends in the unit interval of calculating with the 3rd CPU ₄Compare;

If following five kinds of conditions all satisfy,

a、C ₁＝D ₁；

b、C ₂＝D ₂；

C, C ₁=D ₁And C ₃=D ₃

D, C ₂=D ₂And C ₄=D ₄

E, C ₅=D ₅And C ₆=D ₆

Judge then in the 3rd peripheral unit interconnection high speed bus equipment and the peripheral unit interconnection high speed bus equipment pond that transfer of data is normal between all the other one or more peripheral unit interconnection high speed bus equipment, otherwise, judge in the 3rd peripheral unit interconnection high speed bus equipment and the peripheral unit interconnection high speed bus equipment pond that transfer of data makes a mistake between all the other one or more peripheral unit interconnection high speed bus equipment.

13. peripheral unit interconnection high speed bus interface bandwidth and Performance Test System is characterized in that, comprising:

The first peripheral unit interconnection high speed bus equipment;

The second peripheral unit interconnection high speed bus equipment;

14. peripheral unit interconnection high speed bus switch ports themselves bandwidth and Performance Test System is characterized in that, comprising: