CN102567587A - FPGA (field programmable gate array) interconnection method and device utilizing same - Google Patents
FPGA (field programmable gate array) interconnection method and device utilizing same Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuits and provides an FPGA (field programmable gate array) interconnection method and a device utilizing the same. The device comprises two FPGAs which are interconnected with each other through high-speed interconnection interfaces, a receiving function module and a transmitting function module are built in each FPGA, signals to be transmitted in each FPGA are integrated to be connected with the transmitting function module, and signals to be received are integrated to be connected with the receiving function module. The transmitting function module of each FPGA is connected with the receiving function module of the other FPGA through a high-speed interconnection interface. The FPGAs are interconnected by the high-speed interconnection interfaces, so that the number of signal wires and the number of pins in the FPGA interconnection structure are decreased, complexity in SOC (system on chip) design and realizing of SOC verification is reduced, SOC design efficiency and speed and realizing speed and accuracy of the SOC verification are improved. Meanwhile, layout design of SOC hardware and troubleshooting are convenient.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of FPGA interconnect device and method.
Background technology
Semiconductor industry gets into sub-micro and even after the nanoprocessing epoch, on the single IC for both chip, just can realize a complicated electronic system, such as chip for cell phone, digital television chip, DVD chip etc.Along with the progress of technology, more function all is expected on one chip, to realize.SOC (System on Chip; SOC(system on a chip); Or title system level chip) technology produces under the general orientation that integrated system (IS) changes at integrated circuit (IC) just, and along with the development of semiconductor process techniques, the IC deviser can be integrated into more and more complicated function on the single silicon-chip.Because SOC can make full use of the known designs accumulation, improved the designed capacity and the integration capability of single CPU significantly, therefore obtained development rapidly.
SOC uses FPGA (Field Programmable Gate Array, field programmable gate array) to realize the customization of logic function module usually, thereby must carry out the FPGA functional verification in the SOC performance history.But along with SOC logic scale is increasing, single FPGA is difficult to put next complete SOC design, therefore in the FPGA checking, must carry out function and cut apart, and the function of SOC is placed on respectively among two or the more FPGA verifies.As shown in Figure 1; In the prior art; When in SOC, realizing that two FPGA are interconnected; Usually it is directly interconnected to use many signal wires, if promptly from FPGA_1 to FPGA_2, need send multiclass signal (Signal_0 is to Signal_i) and receive multiclass signal (Signal_j is to Signal_n), then uses n root signal wire to send and receive various types of signal respectively.
This design of SOC and verification mode have proposed certain requirement for interconnected between a plurality of FPGA, and the number of pin of FPGA and the length of interconnection line factors such as (sequential influences) all can influence performance or the verification efficiency of SOC.And when carrying out the FPGA checking, need set up engineering, do detailed pin and divide, pin positions constraint etc., because number of pins is numerous, cabling is complicated, this work is easy to introduce mistake.
In realizing process of the present invention; The inventor finds; There is following shortcoming in above-mentioned mutual contact mode: needs carry out position constraint to the pin that uses respectively in the interconnected engineering of two FPGA, and need on hardware, provide the abundant interconnected pin of hardware to realize; Require also need the cabling of hardware interconnection line to be claimed than higher interface for some sequential, the topological design of these interconnect architectures is complicated, on engineering, is difficult to realize, and very easily makes a mistake.
In addition; Though in Chinese patent open source literature CN102116841A, disclose a kind of FPGA interconnect architecture appraisal procedure that quantizes based on model; This method is mainly extracted quantizating index through the large-scale FPGA interconnect architecture of traversal search space and is used for estimating, thereby under the situation that guarantees accuracy, has accelerated estimating velocity.But this method is just estimated it behind definite interconnect architecture, and can't make effective improvement to interconnect architecture.
Summary of the invention
The technical matters that (one) will solve
To above-mentioned shortcoming, the present invention provides a kind of FPGA interconnect device and method in order to solve FPGA interconnect architecture complicated problems in the prior art.
(2) technical scheme
In order to solve the problems of the technologies described above, on the one hand, the invention provides a kind of FPGA interconnect device, said device comprises: through two interconnected FPGA of high speed interconnecting interface; Wherein, be built-in with receiving module and sending function module among every FPGA; The signal that will send among every FPGA is concentrated into one group of signal that connects the sending function module, will receive and is concentrated into another group and connects receiving module; The sending function module of every FPGA is connected to the receiving module of another piece FPGA through a high speed interconnecting interface.
On the other hand, the present invention also provides a kind of FPGA interconnected method simultaneously, and said method comprises step:
Need between two FPGA to confirm the signal of transmission, signal is divided into the signal that receives and send both direction;
In the inner high speed transmission-receiving function module of introducing of two FPGA;
When source FPGA sends signal, signal is sampled and also string conversion, the high-speed serial signals that finally obtains is sent on the high speed interconnecting interface;
Target FPGA receives said high-speed serial signals, goes here and there and changes signal is reduced one by one, reduction back signal is delivered in the inner functional module of target FPGA used.
(3) beneficial effect
In technical scheme of the present invention; Because use high speed interconnecting interface realization FPGA's is interconnected; Saved line number signal and number of pins in the FPGA interconnect architecture, FPGA installs the complexity of pin design when having reduced the SOC design, the realization difficulty that pin is divided, pin positions retrains when having reduced the SOC checking; Improved SOC design efficiency and speed, and the speed and the accuracy that make the SOC checking realize get a promotion.In addition,, make cabling short and sweet, made things convenient for the hardware arrangement design and wrong investigation of SOC owing to reduced the cabling between two FPGA are interconnected.
Description of drawings
Fig. 1 is a FPGA interconnect architecture synoptic diagram in the prior art;
Fig. 2 is the structural representation of FPGA interconnect device in the embodiments of the invention;
Fig. 3 is the synoptic diagram that carries out conversion of signals when FPGA is interconnected in the embodiments of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills are obtained under the prerequisite of not making creative work belongs to the scope that the present invention protects.
In an embodiment of the present invention; Usually use many signal wires to connect the interconnected mode that realizes to current FPGA; Propose to use the high speed interconnecting interface to replace many signal wires and connect, the various types of signal in FPGA inside when interconnected is divided into groups, and is interconnected through a spot of high speed interconnecting interface realization between FPGA; Reduced the number of pin between the FPGA interconnect architecture in this way; Reduce the complexity of wires design, the engineering error rate is reduced greatly, improved the efficient and the speed of design verification simultaneously.
In the embodiments of the invention, the structure of FPGA interconnect device is as shown in Figure 2.In Fig. 2; In two interconnected FPGA of needs inner built-in receiving module and sending function module respectively; The signal that every FPGA will be sent is concentrated into one group of signal that is connected to the sending function module, will receives and is concentrated into another group and is connected to receiving module; The sending function module of every FPGA is connected to the receiving module of another piece FPGA through the high speed interconnecting interface, and the signal that this FPGA will be sent through the high speed interconnecting interface sends to another piece FPGA and receives the signal of sending from another piece FPGA simultaneously.
Further send signal with a FPGA 100 among Fig. 2 below, it is that example describes that the 2nd FPGA 200 receives signal.In a FPGA 100; Needs are sent to a plurality of signal Signal_0 of the 2nd FPGA 200; Signal_1, Signal_2 ... Signal_i is concentrated into one group, at first is sent to the sending function module TX_1 place of a FPGA 100 respectively through passage (like connecting line or data sendaisle etc.) separately; Sending function module TX_1 parallel receive all sends signal, and signal is carried out and goes here and there conversion, will all send signal sends to the 2nd FPGA 200 with the high-speed serial signals mode receiving module RX_2 place through the high speed interconnecting interface; In the receiving module RX_2 of the 2nd FPGA 200, the high-speed serial signals that receives is gone here and there and change, restore original a plurality of signal Signal_0 that will send among the FPGA 100, Signal_1, Signal_2 ..., Signal_i; Giving the 2nd FPGA 200 inner functional modules with signal through the passage (like connecting line or Data Receiving passage etc.) of each signal again uses.
Likewise; The one FPGA 100 receives the serial signal that the sending function module TX_2 of the 2nd FPGA 200 sends through the high speed interconnecting interface through its receiving module RX_1; It is reduced to original a plurality of signal Signal_j, Signal_j+1, Signal_j+2;, give a FPGA 100 inner functional modules behind the Signal_n and use.
By the way; The present invention has realized interconnected between two FPGA with two groups of high speed interconnecting interfaces; Because the signal that the high speed interconnecting interface passes is not mutually limited by physical pins, has obviously reduced the pin and the connecting line number that use in the FPGA interconnect architecture in the embodiments of the invention, makes that the design and installation of FPGA is faster; Pin use and cabling layout are more succinct, have improved SOC design rate and FPGA functional verification speed greatly.
In the embodiments of the invention, the detailed implementation of FPGA interconnected method is following:
(1) FPGA at SOC verifies the initial stage; The functional module that definite needs are cut apart; Promptly confirm to be placed on respectively the division of the functional module of verifying among the different FPGA; Confirm the signal that needs transmit between two FPGA according to the division of functional module, signal is divided into the signal that receives and send both direction.
(2) in the inner high speed transmission-receiving function module of introducing of two FPGA; Can use the built-in LVDS of FPGA (Low-Voltage Differential Signaling; Low Voltage Differential Signal) etc. interface is realized, and is that this functional module realizes bidirectional transmit-receive function and signal and go here and there translation function.
The realization synoptic diagram of the conversion of signals when (3) source FPGA sends signal is as shown in Figure 3, and wherein, Clock1 is clock zone at a slow speed, Signal_0; Signal_1 ..., Signal_i is this one group of signal of clock zone at a slow speed; Clock2 is the high-frequency clock territory, in this high-frequency clock territory, realizes the signal Signal_0 to the Clock1 clock zone, Signal_1; ..., the sampling of Signal_i and also string conversion are sent the high-speed serial signals Signal_tx that finally obtains on the high speed interconnecting interface; Said high speed interconnecting interface is a HSSI High-Speed Serial Interface, like USB, PCI Express etc.
(4) high-speed serial signals Signal_tx is after arriving target FPGA; The receiving module of target FPGA uses high-frequency clock territory Clock2 that this high-speed serial signals Signal_tx is received equally, goes here and there subsequently and changes the clock zone at a slow speed that signal is reverted to one by one Clock1, obtains the Signal_0 of initialization after the reduction; Signal_1; ..., the Signal_i signal is delivered to reduction back signal in the inner functional module of target FPGA and to be used.
In an embodiment of the present invention, the opposite direction that above-mentioned source target FPGA transmits a signal to the process of target FPGA is the same, and two promptly interconnected FPGA inside need be placed receiving module and sending function module respectively; Send to receiving module through the high speed interconnecting interface after the sending module processing signals, give the inner functional module of FPGA behind the receiving module recovering signal and use.
In the further embodiment of the present invention, the signal that transmits through this high speed interconnecting interface is one group of signal that the sequential correlativity is not strong preferably, for example the irrelevant data-signal of register configuration signal, one group of clock etc.Because the use asynchronous clock is handled usually when also going here and there and going here and there and changing; If the signal of sequential strong correlation; Must transmit in strict accordance with the sequential relationship of signal, otherwise may cause the problem (like phenomenons such as signal waits for too long or deadlocks) on the signal sequence; And the not strong signal of sequential correlativity need not to consider the sequential relationship between signal when conversion, makes that conversion of signals efficient is higher.
Further; The parallel signal quantity that a pair of high speed serialization transmitting-receiving interface can carry is relevant with the clock zone of use; For example; When the frequency of high-frequency clock territory Clock2 is 16 times of frequency of clock zone Clock1 at a slow speed,, can transmit 32 of parallel signals through the high speed interconnecting interface if adopt the mode of doubleclocking along sampling.
In further embodiment of the invention; Above-mentioned FPGA interconnect device is the hardware configuration on the FPGA witness plate; Said FPGA witness plate is mainly used in the checking of carrying out the SOC SOC(system on a chip); Through using said FPGA witness plate to come logic, function and/or the performance of checking SOC system fast; Thereby this witness plate also comprises the general-purpose interface that some are connected with external unit usually, such as input/output interface, image output interface (like VGA etc.), audio output interface, network interface (like Ethernet interface etc.), power interface, storage device interface, cpu i/f etc., in order to transmit the signal data of required checking content.
One of ordinary skill in the art will appreciate that; Realize that all or part of step in the foregoing description method is to instruct relevant hardware to accomplish through program; Described program can be stored in the computer read/write memory medium; This program comprise each step of the foregoing description method, and described storage medium can be: ROM/RAM, magnetic disc, CD etc. when carrying out.In addition, because the characteristic of on-site programmable gate array FPGA itself, it self also supports to realize more complicated logic function with the mode of programmed configurations except the logical cell array that possesses hardware.Therefore; Those of ordinary skills are appreciated that equally; Sending function module in the foregoing description and receiving module can be concrete hardware modules; Also can be firmware or the software function module of in FPGA, realizing through programmed configurations, these two functional modules and FPGA inside can receive signal through the connecting line of entity, the signal that directly produces in the time of also can receiving program run.In the case; Above-mentioned embodiment of the present invention should not be construed as the concrete qualification to apparatus and method of the present invention; It is not be apparatus and method of the present invention the mode of unique employing, at the scene in the programmable gate array FPGA the implementation of the functional module arbitrarily that adopts usually all should fall in protection scope of the present invention.
In sum, adopt the device and method of the above embodiment of the present invention, have following tangible beneficial effect:
1, uses less interface pin to realize the interconnected of two FPGA, saved the number of pin of using when interconnected;
FPGA installs the complexity of pin design when 2, having reduced the SOC design, has improved SOC design efficiency and speed;
The realization difficulty that pin is divided, pin positions retrains when 3, having reduced the SOC checking, the speed and the accuracy that make the SOC checking realize get a promotion;
4, reduce cabling between two FPGA are interconnected, made cabling short and sweet, made things convenient for the hardware arrangement design and wrong investigation of SOC.
Above embodiment only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and real protection scope of the present invention should be defined by the claims.
Claims (10)
1. a FPGA interconnect device is characterized in that, said device comprises: through two interconnected FPGA of high speed interconnecting interface; Wherein,
Be built-in with receiving module and sending function module among the every FPGA; The signal that will send among every FPGA is concentrated into one group of signal that connects the sending function module, will receive and is concentrated into another group and connects receiving module; The sending function module of every FPGA is connected to the receiving module of another piece FPGA through a high speed interconnecting interface.
2. device according to claim 1 is characterized in that, said high speed interconnecting interface is a HSSI High-Speed Serial Interface.
3. based on the described device of claim 1, it is characterized in that signal that will send and the signal that will receive adopt clock zone at a slow speed among the every FPGA, the signal that transmits in the high speed interconnecting interface adopts the high-frequency clock territory.
4. device according to claim 1 is characterized in that, the signal that will send among every FPGA connects the sending function module through connecting line or data sendaisle; The signal that will receive among every FPGA connects receiving module through connecting line or Data Receiving passage.
5. a FPGA interconnected method is characterized in that, said method comprises step:
Need between two FPGA to confirm the signal of transmission, signal is divided into the signal that receives and send both direction;
In the inner high speed transmission-receiving function module of introducing of two FPGA;
When source FPGA sends signal, signal is sampled and also string conversion, the high-speed serial signals that finally obtains is sent on the high speed interconnecting interface;
Target FPGA receives said high-speed serial signals, goes here and there and changes signal is reduced one by one, reduction back signal is delivered in the inner functional module of target FPGA used.
6. method according to claim 5 is characterized in that, at the FPGA checking initial stage of SOC, the definite functional module that need cut apart is according to the signal of confirming that needs transmit between two FPGA of cutting apart of functional module.
7. method according to claim 5 is characterized in that, uses the built-in LVDS interface of FPGA to realize said high speed transmission-receiving function module.
8. method according to claim 5 is characterized in that, and when conversion string signal be transformed into the high-frequency clock territory from clock zone at a slow speed, string and switching signal are transformed into clock zone at a slow speed from the high-frequency clock territory.
9. method according to claim 5 is characterized in that, the signal that transmits through the high speed interconnecting interface is one group of signal that the sequential correlativity is not strong.
10. method according to claim 8 is characterized in that, adopts doubleclocking to carry out said and string conversion and said string and conversion along the mode of sampling.
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| CN102917242A (en) * | 2012-09-10 | 2013-02-06 | 福州瑞芯微电子有限公司 | Testing system and testing method of multi-format video decoder |
| CN103150952A (en) * | 2013-03-12 | 2013-06-12 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
| CN104991883A (en) * | 2015-06-04 | 2015-10-21 | 青岛海信信芯科技有限公司 | Sending and receiving apparatuses with chip interconnection and sending and receiving method and system |
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| CN112699077A (en) * | 2020-12-30 | 2021-04-23 | 上海安路信息科技股份有限公司 | FPGA chip and interconnection method of FPGA sub-chips |
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| CN112699077A (en) * | 2020-12-30 | 2021-04-23 | 上海安路信息科技股份有限公司 | FPGA chip and interconnection method of FPGA sub-chips |
| CN112699077B (en) * | 2020-12-30 | 2024-03-29 | 上海安路信息科技股份有限公司 | FPGA chip and interconnection method of FPGA sub-chips |
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Application publication date: 20120711 |