CN115905096A

CN115905096A - SPI-based data communication system and method

Info

Publication number: CN115905096A
Application number: CN202211443201.XA
Authority: CN
Inventors: 许芳; 刘泽南; 李茹
Original assignee: Changzhou Xingyu Automotive Lighting Systems Co Ltd
Current assignee: Changzhou Xingyu Automotive Lighting Systems Co Ltd
Priority date: 2022-11-17
Filing date: 2022-11-17
Publication date: 2023-04-04

Abstract

The invention relates to the technical field of integrated circuit communication, in particular to a data communication system and method based on SPI. A communication system includes: the host comprises a first SCLK terminal, a first MOSI terminal, a first MISO terminal and n first CS terminals, wherein n is larger than 1; the slave machines are respectively connected with the first SCLK terminal, the first MOSI terminal and the first MISO terminal; and the decoder comprises n input ends and a plurality of output ends, the input ends are in one-to-one correspondence with the first CS ends, the input ends are connected with the corresponding first CS ends, the output ends are in one-to-one correspondence with the slave machines, and the output ends are connected with the corresponding slave machines. The host computer sends out a chip selection enabling signal; the input end of the decoder receives the chip selection enabling signal, and the decoder outputs a state signal according to the chip selection enabling signal and outputs the state signal through the output end of the decoder; the slave receives the state signal, and based on the state signal, the master establishes communication connection with the slave 3. The SPI-based data communication system is simple in structure and capable of reducing occupation of chip resources by pins.

Description

SPI-based data communication system and method

Technical Field

The invention relates to the technical field of integrated circuit communication, in particular to a data communication system and method based on SPI.

Background

SPI (Serial peripheral Interface) is a Serial peripheral Interface, and in the existing digital chip SPI bus communication technology, an SPI Serial bus is mainly applied to data communication between an off-chip and a chip, a chip for transmitting data is generally called a master, a chip for receiving data is generally called a slave, and the SPI bus communication includes: the chip comprises a Master (Master) and at least one Slave (Slave), wherein the Master and the Slave are respectively provided with four data signal lines which mainly comprise a serial clock line SCLK, a Master-output Slave-input signal line MOSI, a Master-input Slave-output signal line MISO and a chip selection enabling signal line CS, the four data lines of the Master and the Slave are respectively and correspondingly connected, and when the chip selection enabling signal line CS enabling signal on the Master is effective, the data communication between the chip and the chip can be realized.

As shown in fig. 1, the MISO terminal (Master Input Slave Output) represents a Master data Input and a Slave data Output; a MOSI terminal (Master Output Slave Input) for indicating Master data Output and Slave data Input; the SCLK terminal (Serial Clock) is the Clock terminal; the CS terminal is a chip selection enable signal terminal. When a master machine and a slave machine carry out data communication, under the condition that an SCLK terminal, an MOSI terminal and an MISO terminal of the master machine and the slave machine are connected through a data signal line, the master machine is connected with a chip selection enabling signal terminal CS of the master machine and the slave machine, and a chip selection enabling signal is sent to the slave machine, so that the data communication between the master machine and the slave machine can be carried out. If one host needs to perform data communication with multiple slaves, the host needs to set multiple CS chip selection enable signal terminals to be connected with the corresponding multiple slaves respectively and send chip selection enable signals to the slaves for data communication, as shown in fig. 2, the host needs to perform data communication with 4 slaves, and the host needs to add 4 CS chip selection enable signal ports to be connected with the slave CS chip selection enable signal terminals respectively for data communication, so that the host pins are redundant and occupy excessive chip resources.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: in order to solve the technical problems that pins of a host are redundant and occupy excessive chip resources in the prior art, the invention provides an SPI-based data communication system which is simple in structure and capable of reducing occupation of the chip resources by the pins.

The technical scheme adopted by the invention for solving the technical problem is as follows: an SPI-based data communication system comprising: the host comprises a first SCLK terminal, a first MOSI terminal, a first MISO terminal and n first CS terminals, wherein n is larger than 1; a plurality of slaves, each slave being connected to the first SCLK terminal, the first MOSI terminal and the first MISO terminal, respectively; and the decoder comprises n input ends and a plurality of output ends, the input ends are in one-to-one correspondence with the first CS ends, the input ends are connected with the corresponding first CS ends, the output ends are in one-to-one correspondence with the slave machines, and the output ends are connected with the corresponding slave machines.

Further, specifically, each slave includes a second SCLK terminal, a second MOSI terminal, a second MISO terminal, and a second CS terminal; the second SCLK terminal is connected with the first SCLK terminal; the second MOSI end is connected with the first MOSI end; the second MISO terminal is connected to the first MISO terminal; and the second CS ends are in one-to-one correspondence with the output ends, and are connected with the corresponding output ends.

Further, specifically, when n is less than or equal to 3 and greater than 1, one decoder chip is disposed in the decoder.

Further, specifically, when n is greater than 3, a plurality of decoder chips are disposed in the decoder.

Further, specifically, the number of the plurality of the slaves is not more than 2 ⁿ And (4) respectively.

An SPI-based data communication method, the communication method comprising:

step S1: each slave is in a waiting state, the decoder is in a working state, and the host sends out a chip selection enabling signal;

step S2: the input end of the decoder receives the chip selection enabling signal, and the decoder outputs a state signal according to the chip selection enabling signal and outputs the state signal through the output end of the decoder;

and step S3: and each slave machine receives the state signal, and the master machine establishes communication connection with the corresponding slave machine based on the state signal.

Further, specifically, the chip select enable signal is transmitted to the input terminal of the decoder through the first CS terminal.

Further, specifically, after the corresponding slave and the master establish a communication connection, the first SCLK of the master is configured to synchronize a clock signal to the corresponding slave, the first MOSI is configured to send data to the slave, and the first MISO is configured to receive data sent by the slave.

The SPI-based data communication system has the advantages that effective communication can be established between the host and the plurality of slave machines, meanwhile, the input end of the decoder is connected with the first CS end of the host through the arranged decoder, the output end of the decoder is connected with the second CS end of the corresponding slave machine, excessive redundancy of pins of the host is avoided, data connecting lines for connecting the host and the slave machines are reduced, the structure is simple, and occupation of the pins on chip resources is reduced.

Drawings

The invention is further illustrated by the following examples in conjunction with the drawings.

FIG. 1 is a prior art single master and single slave SPI communication circuit schematic.

Fig. 2 is a prior art single master and multiple slave SPI communication circuit schematic.

FIG. 3 is a circuit diagram of an SPI-based data communication system according to an embodiment of the present invention.

Fig. 4 is a flowchart of a data communication method based on SPI according to the second embodiment of the present invention.

In the figure 1, a host; 2. a decoder; 3. a slave machine.

Detailed Description

The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention. Furthermore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.

Example 1

As shown in fig. 1, which is embodiment 1 of the present invention, an SPI-based data communication system includes: a host 1, including a first SCLK terminal, a first MOSI terminal, a first MISO terminal and n first CS terminals, where n is greater than 1; a plurality of slaves 3, wherein each slave 3 is respectively connected with the first SCLK terminal, the first MOSI terminal and the first MISO terminal; and the decoder 2 comprises n input ends and a plurality of output ends, the input ends are in one-to-one correspondence with the first CS ends, the input ends are connected with the corresponding first CS ends, the output ends are in one-to-one correspondence with the slave machines 3, and the output ends are connected with the corresponding slave machines 3. When the system works, each slave machine 3 is in a waiting state, the decoder 2 is in a working state, and the host machine 1 sends out a chip selection enabling signal; the input end of the decoder 2 receives the chip selection enable signal, and the decoder 2 outputs a state signal according to the chip selection enable signal and outputs the state signal through the output end of the decoder 2; each slave 3 receives the status signal, and based on the status signal, the master 1 establishes a communication connection with the corresponding slave 3. After the corresponding slave 3 establishes communication connection with the master 1, the first SCLK terminal of the master 1 is used to synchronize clock signals to the corresponding slave 3, the first MOSI terminal is used to transmit data to the slave 3, and the first MISO terminal is used to receive data transmitted by the slave 3. While effective communication can be established between the host 1 and the slave 3, the input end of the decoder 2 is connected with the first CS end of the host 1 through the arranged decoder 2, and the output end of the decoder 2 is connected with the second CS end of the slave 3, so that the excessive redundancy of the pins of the host 1 is avoided, the data connecting lines for connecting the host 1 and the slave 3 are reduced, the structure is simple, and the occupied resources of a chip are reduced.

In an embodiment, each slave 3 comprises a second SCLK terminal, a second MOSI terminal, a second MISO terminal, and a second CS terminal; the second SCLK terminal is connected with the first SCLK terminal; the second MOSI end is connected with the first MOSI end; the second MISO terminal is connected with the first MISO terminal; and the second CS ends are in one-to-one correspondence with the output ends, and the second CS ends are connected with the corresponding output ends.

In the embodiment, when n is less than or equal to 3 and greater than 1, one decoder chip is arranged in the decoder 2; when n is greater than 3, decoder 2 has multiple decoder chips, and the number of multiple slaves is not greater than 2 ⁿ And (4) respectively. If n is 3, the number of the slave machines 3 in the SPI-based data communication system is eight at most, the decoder 2 is preferably a 3-line-8-line decoder, the chip model of the 3-line-8-line decoder is 74hc138, but is not limited thereto, and when n is 4, the number of the slave machines 3 in the SPI-based data communication system is sixteen at most and nine at least, and the decoder 2 is a 4-line-16-line decoder formed by cascading two 3-line-8-line decoders; when n is 5, the number of the slave machines 3 of the SPI-based data communication system is at most thirty two, and at least seventeen, and the decoder 2 adopts three 3-line-8-line decoders which are cascaded to form a 5-line-32-line decoder.

For example, when n is 3, the master 1 includes 3 first CS terminals, the slaves 3 are 8, the decoder 2 includes 3 input terminals and 8 output terminals, each input terminal is connected to a corresponding first CS terminal, and each output terminal is connected to a corresponding slave 3; the 3 input ends are respectively an A2 end, an A1 end and an A0 end, the 8 output ends are respectively a Y0 end, a Y1 end, a Y2 end, a Y3 end, a Y4 end, a Y5 end and a Y7 end, and when the 3-line-8-line decoder is in a working state, an input-output logic truth table is as follows:

TABLE 1 input-output logic truth table

As can be seen from the above table, each combination of input signals corresponds to a low level signal at one output terminal, i.e. the output terminal is considered to have an output signal when the output terminal is at a low level. Certainly, if necessary, it may also be defined that the output end is considered to have an input signal when the output end is at a high level, at this time, the output end is said to be at a high level and effective, 8 different combination state signals are formed after being received and decoded by the input end according to the chip selection enable signals respectively sent by the 3 first CS ends of the master 1, the 8 different combination state signals are respectively output to the second CS ends of the corresponding slaves 3, and the corresponding slaves 3 establish a communication connection with the master 1 according to the received state signals, so that sending and receiving of data signals can be realized.

To further explain that the second CS terminal of the slave 3 is active at low level, the 8 slaves 3 are respectively a first slave 3, a second slave 3, a third slave 3, a fourth slave 3, a fifth slave 3, a sixth slave 3, a seventh slave 3, and an eighth slave 3. When the 3-wire-8-wire decoder is in a working state, 3 pins of the first SCLK terminal, the first MOSI terminal and the first MISO terminal of the master 1 are respectively connected with the second SCLK terminal, the second MOSI terminal and the second MISO terminal of each slave 3, three first CS terminals of the master 1 are all set at a low level according to an input and output logic truth table, 8 output signals are formed after the three pins are received and decoded by the 3-wire-8-wire decoder, the output signals from the high to low Y7-Y0 are 11111110 respectively, the output signal from the Y0 terminal is a low level, the output signal from the Y7 terminal to the Y1 terminal is a high level, the output signal from the Y2 terminal is a high level, the second CS terminal is connected with the second slave 3, the Y2 terminal is connected with the third slave 3, the Y3 is connected with the fourth slave 3, the Y4 terminal is connected with the fifth slave 3, the Y5 terminal is connected with the seventh slave 3, the Y7 terminal is connected with the eighth slave 3, and the eighth slave 3 is connected with the third slave 3. If the master 1 needs to select to perform data communication with the seventh slave 3, only three first CS terminals CS2-CS0 of the master 1 need to be respectively set at a high level, a high level and a low level, and the signals are received and decoded by the 3-line-8-line decoder to form 8 output signals, and the signals from high to low Y7-Y0 are 10111111 respectively, the output signal of the Y6 terminal is at the low level, the other outputs Y7 and Y5-Y0 are at the high level, the decoder 2Y6 terminal is connected to the second CS terminal of the seventh slave 3, the second CS terminal of the seventh slave 3 is at the low level, that is, the second CS terminal of the seventh slave 3 is at the low level and is valid, the master 1 successfully sends a chip selection enable signal to the seventh slave 3 to implement data communication between the master 1 and the seventh slave 3, the master 1 and the other slaves 3, such as the communication modes of the second slave 3, the third slave 3 and the first slave 3 or the seventh slave 3, and the descriptions thereof are omitted here for brevity.

Example 2

Based on the same inventive concept as the SPI-based data communication system in the foregoing embodiment, the present invention also provides an SPI-based data communication method, which includes:

step S1: each slave machine 3 is in a waiting state, the decoder 2 is in a working state, and the host machine 1 sends out a chip selection enabling signal; when the master selects to communicate with a slave, the master 1 sends out a chip selection enable signal according to the connection condition of the output signal of the decoder and the slave, and the first CS end in the master 1 is respectively set to be high level or low level to enable, and the setting of the high level and the low level is determined by the high level or the low level of the master and the slave.

Step S2: the input end of the decoder 2 receives the chip selection enable signal, and the decoder 2 outputs a state signal according to the chip selection enable signal and outputs the state signal through the output end of the decoder 2; the chip selection enable signal received by the decoder outputs different state signals according to the chip selection enable signal and the input/output logic truth table, and the different state signals are output to the slave through the decoder 2.

And step S3: each slave 3 receives the state signal, and based on the state signal, the master 1 establishes communication connection with the corresponding slave 3; the second CS end of the slave 3 is configured to receive the state signal, so that the slave that needs to establish communication connection is set to a high level or a low level (active state), the master 1 successfully sends a chip select enable signal to the slave 3 that needs to communicate, and then the other slaves 3 are in an inactive state; after the corresponding slave 3 receives the chip selection enabling signal of the master 1, the master can initiate communication to the corresponding slave.

In an embodiment, the chip select enable signal is transmitted to the input terminal of the decoder 2 through the first CS terminal.

In the embodiment, after the corresponding slave 3 establishes a communication connection with the master 1, the first SCLK terminal of the master 1 is used to synchronize a clock signal to the corresponding slave 3, the first MOSI terminal is used to transmit data to the slave 3, and the first MISO terminal is used to receive data transmitted by the slave 3.

Various changes and specific examples of the SPI-based data communication system in the first embodiment of fig. 1 are also applicable to the SPI-based data communication method in the present embodiment, and those skilled in the art can clearly understand the implementation method of the SPI-based data communication method in the present embodiment through the foregoing detailed description of the SPI-based data communication system, so that details are not described again for the sake of brevity of the description.

In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. An SPI-based data communication system, comprising:

a host (1) including a first SCLK terminal, a first MOSI terminal, a first MISO terminal and n first CS terminals, n being greater than 1;

a plurality of slaves (3), wherein each slave (3) is respectively connected with the first SCLK terminal, the first MOSI terminal and the first MISO terminal; and

the decoder (2) comprises n input ends and a plurality of output ends, the input ends are in one-to-one correspondence with the first CS ends, the input ends are connected with the corresponding first CS ends, the output ends are in one-to-one correspondence with the slave machines (3), and the output ends are connected with the corresponding slave machines (3).

2. SPI-based data communication system according to claim 1, characterized in that each of said slaves (3) comprises a second SCLK terminal, a second MOSI terminal, a second MISO terminal and a second CS terminal;

the second SCLK terminal is connected with the first SCLK terminal;

the second MOSI end is connected with the first MOSI end;

the second MISO terminal is connected with the first MISO terminal; and

the second CS ends are in one-to-one correspondence with the output ends, and the second CS ends are connected with the corresponding output ends.

3. An SPI-based data communication system according to claim 1, characterized in that said decoder (2) is provided with a decoder chip when n is equal to or less than 3 and greater than 1.

4. An SPI-based data communication system according to claim 3, characterized in that a plurality of said decoder chips are provided in said decoder (2) when said n is greater than 3.

5. The SPI based data communication system according to claim 1, wherein the number of said plurality of slaves is no greater than 2 ⁿ And (4) respectively.

6. An SPI-based data communication method employing the SPI-based data communication system according to any one of claims 1 to 5, the communication method comprising:

step S1: each slave machine (3) is in a waiting state, the decoder (2) is in a working state, and the host machine (1) sends out a chip selection enabling signal;

step S2: the input end of the decoder (2) receives the chip selection enabling signal, and the decoder (2) outputs a state signal according to the chip selection enabling signal and outputs the state signal through the output end of the decoder (2);

and step S3: each slave (3) receives the state signal, and the master (1) establishes communication connection with the corresponding slave (3) based on the state signal.

7. The SPI based data communication method according to claim 6, wherein the chip select enable signal is transmitted to the input terminal of the decoder (2) through the first CS terminal.

8. The SPI-based data communication method according to claim 6, wherein after the corresponding slave (3) establishes a communication connection with the master (1), the first SCLK terminal of the master (1) is configured to synchronize clock signals to the corresponding slave (3), the first MOSI terminal is configured to transmit data to the slave (3), and the first MISO terminal is configured to receive data transmitted by the slave (3).