CN111274193A - Data processing apparatus and method - Google Patents
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Abstract
The present disclosure relates to a data processing apparatus and method. The device comprises a plurality of processing chipsets, wherein each processing chipset comprises a plurality of cascaded processing chips; the auxiliary control chip is connected to each processing chip set; the main control chip is connected to the auxiliary control chip and used for sending a data packet to be processed to the auxiliary control chip; wherein, the auxiliary control chip is used for: receiving a data packet to be processed; executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed; and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed. Through the auxiliary control chip that possesses more communication interfaces at the external main control chip, not only increased the quantity of the processing chip group with main control chip parallel connection, increased the total amount of the processing chip who is connected with main control chip moreover, improved data processing device's parallel data processing performance.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a data processing apparatus and method.
Background
With the rapid development of artificial intelligence technology, more and more processing demands for mass data appear in high-performance artificial intelligence computing platforms, and therefore, higher requirements are placed on the computing capacity of the high-performance artificial intelligence computing platforms.
In the related art, high-performance artificial intelligence computing platforms usually utilize a cascade of multiple processing chips to improve the computing power. Specifically, the high-performance artificial intelligence computing platform comprises at least one main control chip and a plurality of processing chip sets, wherein the main control chip is respectively connected to the first-stage processing chips of the processing chip sets through communication interfaces so as to control the processing chip sets, and further the computing capacity is improved.
However, since the number of communication interfaces provided in the main control chip is limited, the number of processing chipsets that can be connected in parallel is limited. Therefore, the improvement of the data processing performance of the high-performance artificial intelligence computing platform is also limited.
Disclosure of Invention
In view of this, the present disclosure provides a data processing apparatus and method to implement expansion of a communication interface in a main control chip, so that the main control chip can be connected to more processing chipsets in parallel, and data processing performance is improved.
According to an aspect of the present disclosure, there is provided a data processing apparatus, the apparatus comprising a plurality of processing chipsets, each processing chipset comprising a plurality of processing chips in cascade; an auxiliary control chip connected to each processing chipset; the main control chip is connected to the auxiliary control chip and used for sending a data packet to be processed to the auxiliary control chip; wherein, the auxiliary control chip is used for: receiving the data packet to be processed; executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed; and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
In a possible implementation manner, the to-be-processed data packet includes a group identifier of each processing chipset, the to-be-processed intermediate data packet includes a plurality of to-be-processed intermediate sub-data packets, where performing a preset operation on the to-be-processed data packet to obtain the to-be-processed intermediate data packet includes: and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification.
In a possible implementation manner, an auxiliary control chip is provided with a first communication interface and a second communication interface, and the auxiliary control chip is respectively connected to the first-level processing chips of the processing chip sets through the first communication interfaces; the main control chip is provided with a third communication interface and a fourth communication interface, and the fourth communication interface is connected to the second communication interface; the first communication interfaces and the third communication interfaces have the same interface types, and the number of the first communication interfaces is larger than that of the third communication interfaces.
In a possible implementation manner, the data format of the to-be-processed data packet is different from that of the to-be-processed intermediate data packet, where performing a preset operation on the to-be-processed data packet to obtain the to-be-processed intermediate data packet includes: and converting the data format of the data packet to be processed from the data transmission format of the second communication interface into the data transmission format of the first communication interface.
In one possible implementation, the processing chipset is configured to: processing the intermediate data packet to be processed to obtain a processing result data packet; sending the processing result data packet to an auxiliary control chip; wherein, the auxiliary control chip is further configured to: receiving the processing result data packet; determining a result type of the processing result data packet; and sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface.
In a possible implementation manner, the processing result data packet includes a plurality of sub-processing result data packets and chip identifiers respectively corresponding to the sub-processing result data packets, and the main control chip is further configured to determine, according to the chip identifiers, sub-chips used by the sub-processing result data packets.
In one possible implementation, the auxiliary control chip includes a field programmable gate array; the first communication interface comprises a universal asynchronous receiver transmitter interface; the second communication interface includes a serial peripheral interface.
According to another aspect of the present disclosure, a high performance computing device is provided that includes the data processing apparatus of the present disclosure.
According to another aspect of the present disclosure, there is provided a data processing method applied to a secondary control chip connected to a plurality of processing chip sets, the method including: receiving a data packet to be processed; executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed; and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
In a possible implementation manner, the to-be-processed data packet includes a group identifier of each processing chipset, the to-be-processed intermediate data packet includes a plurality of to-be-processed intermediate sub-data packets, where performing a preset operation on the to-be-processed data packet to obtain the to-be-processed intermediate data packet includes: and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification. .
In a possible implementation manner, the auxiliary control chip is provided with a first communication interface and a second communication interface, the data format of the to-be-processed data packet is different from that of the to-be-processed intermediate data packet, wherein a preset operation is performed on the to-be-processed data packet to obtain the to-be-processed intermediate data packet, and the method includes: and converting the data format of the data packet to be processed into the data transmission format of the first communication interface from the data transmission format of the second communication interface.
In one possible implementation, the method further includes: when a processing result data packet sent by a processing chipset is received, determining the result type of the processing result data packet, wherein the processing result data packet is obtained by the processing chipset based on the data packet to be processed; and sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface.
In a possible implementation manner, the sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface includes: and sending a sub-processing result data packet and a chip identifier to the main control chip through a communication interface corresponding to the result type in the first communication interface, so that the main control chip determines the sub-chip used by the sub-processing result data packet according to the chip identifier.
According to the data processing device and method disclosed by the embodiment of the disclosure, the auxiliary control chip with more communication interfaces is externally connected to the main control chip, so that the number of processing chip sets connected with the main control chip in parallel is increased, the total number of processing chips connected with the main control chip is increased, and the parallel data processing performance of the data processing device is improved.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure.
Fig. 2 shows a schematic structural diagram of an auxiliary control chip according to an embodiment of the present disclosure.
Fig. 3 shows a schematic structural diagram of an auxiliary control chip according to an embodiment of the present disclosure.
FIG. 4 is a schematic diagram of a high performance computing device, according to an embodiment of the present disclosure.
Fig. 5 shows a flow diagram of a data processing method according to an embodiment of the present disclosure.
Fig. 6 shows a flow diagram of a data processing method according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 shows a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure. The data processing device of the embodiment can be applied to any use scene needing to process mass data, and can be arranged in intelligent equipment such as a computer, a server, a mobile terminal or wearable equipment, so as to improve the data processing performance of the intelligent equipment.
As shown in fig. 1, the data processing apparatus 10 includes: a plurality of processing chipsets 11, each including a plurality of processing chips which are cascade-connected; an auxiliary control chip 12, said auxiliary control chip 12 being connected to the respective processing chipset 11; the main control chip 13 is connected to the auxiliary control chip 12, and the main control chip 13 is used for sending a data packet to be processed to the auxiliary control chip 12; the auxiliary control chip 12 is configured to: receiving the data packet to be processed; executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed; and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
Wherein, each processing chip set in the data processing device can be composed of a plurality of processing chips. In one example, the data processing performance of the processing chipset is related to the number of processing chips in the processing chipset, i.e. the greater the number of processing chips, the stronger the data processing performance of the processing chipset, and the fewer the number of processing chips, the weaker the data processing performance of the processing chipset. In another example, the power consumption of the processing chipset is related to the number of processing chips in the processing chipset, i.e., the greater the number of processing chips, the greater the power consumption of the processing chipset, the fewer the number of processing chips, and the less the power consumption of the processing chipset. Thus, the number of processing chips in a processing chipset may be determined in combination with the requirements of the data processing performance required in the usage scenario, and the affordable load.
In this embodiment, the processing chips may be processor chips (e.g., a central processing unit CPU, a graphics processing unit NPU, etc.), memory and storage chips (e.g., DRAM, NAND, etc.), or specific function chips (e.g., a deep learning operation chip, a cloud computing operation chip, etc.), and the disclosure does not limit the types of the processing chips.
In one possible embodiment, the plurality of processing chips connected in series may be the same chip or different chips.
In the data processing process, each processing chip is connected with the auxiliary control chip through a bus, and the output of the auxiliary control chip is used as the input of the processing chip for processing.
In one example, the pending data packet may be an input to the data processing apparatus. In the process of processing the data packet to be processed by the data processing device, after the main control chip interface in the data processing device receives the data packet to be processed sent by the external environment, the data packet to be processed is forwarded to the auxiliary control chip. After the auxiliary control chip receives the data packet to be processed, preprocessing operation is executed on the data packet to be processed, and the data packet to be processed is changed into an intermediate data packet to be processed.
In one example, the preprocessing operation may be a data format conversion operation, and correspondingly, the data format of the data packet to be processed and the data format of the intermediate data packet to be processed may not be the same; in another example, the preprocessing operation may be a data dividing operation, and correspondingly, the to-be-processed data packet may be divided into a plurality of to-be-processed intermediate sub-packets, which are collectively referred to as to-be-processed intermediate data packets for convenience of description.
After the auxiliary control chip obtains the intermediate data packets to be processed, the intermediate data packets to be processed are distributed to each processing chipset in parallel, so that the plurality of processing chipsets in the data processing device process the intermediate data packets to be processed in parallel.
According to the data processing device, the auxiliary control chip with more communication interfaces is externally connected to the main control chip, so that the number of processing chip groups connected with the main control chip in parallel is increased, the total amount of the processing chips connected with the main control chip is increased, and the parallel data processing performance of the data processing device is improved.
In a possible implementation manner, the to-be-processed data packet includes a group identifier of each processing chipset, the to-be-processed intermediate data packet includes a plurality of to-be-processed intermediate sub-data packets, where performing a preset operation on the to-be-processed data packet to obtain the to-be-processed intermediate data packet includes: and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification.
The to-be-processed data packet may include a plurality of group identifiers, where the group identifiers are used to identify the processing chip sets, and each group identifier may also have a corresponding relationship with the to-be-processed intermediate sub-data packet to indicate that the to-be-processed intermediate sub-data packet is used to be sent to the processing chip set identified by the group identifier having the corresponding relationship with the to-be-processed intermediate sub-data packet.
In one example, the group identification may be of any type of identification information for identifying the respective processing chipset in the data processing apparatus, for example, the group identification may be a chip identification of the processing chipset.
In another example, the to-be-processed data packet further includes a chip identifier, where the chip identifier is used to identify processing chips constituting a processing chipset, and any one processing chip in the data processing apparatus may have a unique chip identifier corresponding to the chip identifier. Meanwhile, each intermediate sub-packet to be processed is composed of a plurality of data segments, and the data segments are the contents which need to be processed by each processing chip. Therefore, during the data processing process, the auxiliary control chip sends each data segment to the processing chip for processing the data segment according to the chip identification.
In the embodiment, the operation of data division executed by the main control chip in the related art is handed over to the auxiliary control chip for execution, and compared with the related art, the embodiment reduces the load on the main control chip and reduces the complexity of the task carried by the main control chip in the data processing process.
Fig. 2 shows a schematic structural diagram of a data processing apparatus according to an embodiment of the present disclosure. In one possible implementation manner, as shown in fig. 2, the secondary control chip 12 is provided with a first communication interface 1201 and a second communication interface 1202, and the secondary control chip is connected to the first-level processing chips 111 of the respective processing chip sets through the first communication interfaces respectively; the main control chip 13 is provided with a third communication interface 1301 and a fourth communication interface 1302, and the fourth communication interface is connected to the second communication interface; the first communication interfaces and the third communication interfaces have the same interface types, and the number of the first communication interfaces is larger than that of the third communication interfaces.
In one possible implementation, the auxiliary control chip includes a field programmable gate array; the first communication interface comprises a universal asynchronous receiver transmitter interface; the second communication interface includes a serial peripheral interface.
In this embodiment, the auxiliary control chip may be any type of Programmable Device such as an FPGA (Field-Programmable Gate Array), a PAL (Programmable Array Logic), a GAL (generic Array Logic), a CPLD (Complex Programmable Logic Device), and the like. In one example, the secondary control chip may be, for example, an SC16IS752 chip or a VK3266 chip. The present disclosure is not limited to a particular type of secondary control chip.
In this embodiment, the auxiliary control chip may be connected to a plurality of processing chipsets, that is, the auxiliary control chip is provided with a plurality of first communication interfaces for connecting the plurality of processing chipsets, so that the auxiliary control chip is connected to the first-stage chip of the processing chipsets through the first communication interfaces, and further, the connection and communication of the auxiliary control chip to the processing chipsets are realized.
The main control chip is provided with a plurality of fourth communication interfaces, wherein the fourth communication interfaces and the second communication interfaces have the same interface type, for example, the fourth communication interfaces and the second communication interfaces may be high-speed communication protocol interfaces such as SPI (Serial peripheral interface), LVDS (Low-Voltage Differential Signaling), USB (Universal Serial Bus), PCIE (peripheral component interconnect express, high-speed Serial computer expansion Bus) and the like; and the main control chip is connected with the auxiliary control chip through the fourth communication interface and the second communication interface.
In this embodiment, the main control chip is provided with a plurality of third communication interfaces, and the interface types of the third communication interfaces are the same as those of the first communication interfaces; for example, the third communication interface and the first communication interface may each be a low-speed communication protocol interface such as a UART interface (universal asynchronous Receiver/Transmitter), an IIS interface (Integrated interface of Sound), an IIC interface (Inter-Integrated Circuit BUS), and the like.
In one example, the third communication interface is in an idle state, not connected to any components; compared with the number of the third communication interfaces arranged on the main control chip, the number of the first communication interfaces arranged on the auxiliary control chip is more, more processing chip sets can be connected, namely, the main control chip can be indirectly connected through the auxiliary control chip, and the number of the processing chip sets is more than that of the third communication interfaces, so that the parallel data processing performance of the data processing device is improved.
In this embodiment, on the premise that the interface types of the third communication interface and the first communication interface are the same, the interface types of the second communication interface and the fourth communication interface are the same, and the number of the first communication interfaces is greater than the number of the third communication interfaces, a control chip of any type may be selected as the auxiliary control chip.
In one possible embodiment, the communication interfaces of the plurality of processing chips are the same, for example, the communication interfaces of the processing chips may be low-speed communication interfaces. Therefore, the present embodiment does not limit the types of the processing chips on the premise of ensuring that the communication interfaces of the plurality of processing chips are the same.
In a possible implementation manner, the data format of the to-be-processed data packet is different from that of the to-be-processed intermediate data packet, where performing a preset operation on the to-be-processed data packet to obtain the to-be-processed intermediate data packet includes: and converting the data format of the data packet to be processed from the data transmission format of the second communication interface into the data transmission format of the first communication interface. This process may be performed in the secondary control chip.
In one example, the auxiliary control chip converts the data format of the data packet to be processed from the data format conforming to the high-speed communication protocol interface to the data format conforming to the low-speed communication protocol interface; in another example, the auxiliary control chip converts the data format of the data packet to be processed from the data format conforming to the SPI interface to the data format conforming to the UART interface.
In the embodiment, the operation of converting the data format executed by the main control chip in the related art is handed over to the auxiliary control chip for execution, and compared with the related art, the embodiment reduces the load on the main control chip and reduces the complexity of the task carried by the main control chip in the data processing process.
In one possible implementation, the processing chipset is configured to: processing the intermediate data packet to be processed to obtain a processing result data packet; sending the processing result data packet to an auxiliary control chip; wherein, the auxiliary control chip is further configured to: receiving the processing result data packet; determining a result type of the processing result data packet; and sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface.
The processing result data packets of different types may be transmitted through different first communication interfaces, for example, a processing result data packet whose result type is processing interruption may be transmitted to the main control chip by the auxiliary control chip through the pass-through interface a in the first communication interface, and a processing result data packet whose result type is processing success may be transmitted to the main control chip by the auxiliary control chip through the pass-through interface B in the first communication interface.
In a possible implementation manner, the processing result data packet includes a plurality of sub-processing result data packets and chip identifiers respectively corresponding to the sub-processing result data packets, and the main control chip is further configured to determine, according to the chip identifiers, sub-chips used by the sub-processing result data packets.
In this embodiment, the sub-processing result data packet is formed by processing the data fragment by the processing chip, in the data processing process, each processing chip in each group of processing chip sets sequentially sends the processing sub-result data packet and the chip identifier corresponding to the sub-processing result data packet to the first-stage processing chip of the group of processing chip sets along the direction connected to the auxiliary control chip, the first-stage processing chip sends the processing result data packet including the plurality of sub-processing result data packets and the chip identifier corresponding to each sub-processing result data packet to the auxiliary control chip, the auxiliary control chip sends the processing result data packet including the plurality of sub-processing result data packets and the chip identifier corresponding to each sub-processing result data packet to the main control chip, and the main control chip analyzes the received processing result data packet and the chip identifier to determine the sub-chip used by each sub-processing result data packet.
Fig. 3 shows a schematic structural diagram of an auxiliary control chip according to an embodiment of the present disclosure. In which the same reference numerals as in the above figures denote similar features.
The present embodiment may use an FPGA as an example of the auxiliary control chip. As shown in fig. 3, an RXC module (Receive Control) in the FPGA represents an accepting Control processor, an FIFO (First Input First output) module is used for representing an FIFO memory, a TXC module (Transmit Control) represents a sending Control processor, M0(Master0)/M1(Master1) represents a Master device, S0/S1/S2/S3 represents a Slave device, an AHB module represents a bus protocol module, APB _ MUX represents a communication interface of the AHB module connected with an external device, UART _ Chainx represents a communication interface of the FPGA connected with a processing chip, and SPI1_ Slave/SPI2_ Master/SPI3_ Master represents a communication interface of the FPGA connected with the Master chip.
Specifically, when the FPGA is used for processing data, the FPGA receives a to-be-processed data packet sent by the main control chip through the SPI1_ Slave, and stores the to-be-processed data packet in the FIFO memory; the TXC module decodes the control signal in the data packet to be processed, performs data division processing and/or data format conversion processing on the data packet to be processed according to a decoding result to obtain an intermediate data packet to be processed, distributes the data segment in the intermediate data packet to be processed to each processing chip through the UART _ Chainx _ x, and the processing chip processes the data segment. After the processing chip finishes processing the data segments and obtains the sub-processing result data packets, the FPGA receives the sub-processing result data packets through the UART _ Chainx _ x, stores the sub-processing result data packets in the FIFO memory, the RXC module performs secondary decoding on each sub-processing result data packet to obtain a result type, selects a communication result corresponding to the result type of the sub-processing result data packet from the SPI2_ Master and the SPI3_ Master, and sends each sub-processing result data packet to the main control chip.
It should be noted that, although the data processing apparatus shown in fig. 1 is described by taking the FPGA shown in fig. 3 as an example, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set according to personal preference and/or actual application scene.
Therefore, by externally connecting the main control chip with the auxiliary control chip with more communication interfaces, the data processing device according to the embodiment of the disclosure not only increases the number of processing chip sets connected in parallel with the main control chip, but also increases the total number of processing chips connected with the main control chip, thereby improving the parallel data processing performance of the data processing device, and simultaneously, the disclosure also gives the operation (such as the operation of data division and the operation of data format conversion) originally belonging to the main control chip to the auxiliary control chip for execution, thereby reducing the load on the main control chip and reducing the complexity of the task borne by the main control chip in the data processing process.
FIG. 4 illustrates a block diagram of a high performance computing device, according to an embodiment of the present disclosure. In which the same reference numerals as in the above figures denote similar features.
As shown in fig. 4, the energy efficient computing device 30 may be a server cluster including a plurality of servers 301 that may be provided with the data processing apparatus 10 of the present disclosure. In the running process of high-performance computing equipment, a plurality of servers provided with the data processing device can perform parallel operation, and the data processing performance is extremely high.
Fig. 5 is a flowchart illustrating a data processing method according to an embodiment of the present disclosure, which may be implemented in the data processing apparatus or the energy efficient computing device according to various embodiments, and the method is applied to an auxiliary control chip, where the auxiliary control chip is connected to a plurality of processing chipsets, and the method includes:
step 401: receiving a data packet to be processed;
step 402: executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed;
step 403: and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
According to the data processing method of the embodiment of the disclosure, the auxiliary control chip with more communication interfaces is externally connected to the main control chip, so that the number of processing chip sets connected with the main control chip in parallel is increased, the total number of processing chips connected with the main control chip is increased, and the parallel data processing performance of the data processing device is improved.
In a possible implementation manner, the to-be-processed data packet includes a group identifier of each processing chipset, and the to-be-processed intermediate data packet includes a plurality of to-be-processed intermediate sub-data packets, where in step 402: executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed, including: and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification.
In a possible implementation manner, the auxiliary control chip is provided with a first communication interface and a second communication interface, and the data format of the to-be-processed data packet is different from that of the to-be-processed intermediate data packet, where step 402: executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed, including: and converting the data format of the data packet to be processed into the data transmission format of the first communication interface from the data transmission format of the second communication interface.
Fig. 6 shows a flow diagram of a data processing method according to an embodiment of the present disclosure, wherein like reference numerals represent like features as in fig. 5. As shown in fig. 6, the method further comprises:
step 401: receiving a data packet to be processed;
step 402: executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed;
step 403: and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
Step 404: when a processing result data packet sent by a processing chipset is received, determining the result type of the processing result data packet, wherein the processing result data packet is obtained by the processing chipset based on the data packet to be processed;
step 405: and sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface.
In one possible implementation manner, the processing result data packet includes a plurality of sub-processing result data packets and chip identifiers respectively corresponding to the sub-processing result data packets, where step 405: the sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface includes: and sending a sub-processing result data packet and a chip identifier to the main control chip through a communication interface corresponding to the result type in the first communication interface, so that the main control chip determines the sub-chip used by the sub-processing result data packet according to the chip identifier.
Through the auxiliary control chip that possesses more communication interfaces at the external main control chip, the data processing apparatus according to the above-mentioned embodiment of this disclosure has not only increased the quantity of the processing chip group with main control chip parallel connection, and increased the total amount of the processing chip that is connected with main control chip, has improved data processing apparatus's parallel data processing performance, and this disclosure has still given the operation (for example the operation of data division, the operation of data format conversion) that originally belonged to main control chip to the auxiliary control chip and has carried out simultaneously, has reduced the load to main control chip, has reduced the complexity of the task that main control chip bore in the data processing process.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (13)
1. A data processing apparatus, characterized in that the apparatus comprises:
a plurality of processing chipsets, each processing chipset comprising a plurality of processing chips in cascade;
an auxiliary control chip connected to each processing chipset;
the main control chip is connected to the auxiliary control chip and used for sending a data packet to be processed to the auxiliary control chip;
wherein, the auxiliary control chip is used for:
receiving the data packet to be processed;
executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed;
and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
2. The apparatus of claim 1, wherein the packets to be processed comprise group identifiers of respective processing chipsets, wherein the intermediate packets to be processed comprise a plurality of intermediate sub-packets to be processed,
the method for obtaining the intermediate data packet to be processed by executing the preset operation on the data packet to be processed comprises the following steps:
and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification.
3. The apparatus of claim 1,
the auxiliary control chip is provided with a first communication interface and a second communication interface and is respectively connected to the first-stage processing chips of the processing chip groups through the first communication interfaces;
the main control chip is provided with a third communication interface and a fourth communication interface, and the fourth communication interface is connected to the second communication interface;
the first communication interfaces and the third communication interfaces have the same interface types, and the number of the first communication interfaces is larger than that of the third communication interfaces.
4. The apparatus of claim 3, wherein the data format of the pending data packet is different from the data format of the pending intermediate data packet,
the method for obtaining the intermediate data packet to be processed by executing the preset operation on the data packet to be processed comprises the following steps:
and converting the data format of the data packet to be processed from the data transmission format of the second communication interface into the data transmission format of the first communication interface.
5. The apparatus of claim 3, wherein the processing chipset is configured to:
processing the intermediate data packet to be processed to obtain a processing result data packet;
sending the processing result data packet to an auxiliary control chip;
wherein, the auxiliary control chip is further configured to:
receiving the processing result data packet;
determining a result type of the processing result data packet;
and sending the processing result data packet to the main control chip through a communication interface corresponding to the result type in the first communication interface.
6. The apparatus according to claim 5, wherein the processing result packet includes a plurality of sub-processing result packets and chip identifications respectively corresponding to the respective sub-processing result packets,
the main control chip can also be used for determining the sub-chip used by the sub-processing result data packet according to the chip identification.
7. The apparatus of any one of claims 3 to 6, wherein:
the auxiliary control chip comprises a field programmable gate array;
the first communication interface comprises a universal asynchronous receiver transmitter interface;
the second communication interface includes a serial peripheral interface.
8. A high performance computing device comprising a data processing apparatus as claimed in any one of claims 1 to 7.
9. A data processing method applied to an auxiliary control chip, wherein the auxiliary control chip is connected with a plurality of processing chip sets, the method comprising:
receiving a data packet to be processed;
executing preset operation on the data packet to be processed to obtain an intermediate data packet to be processed;
and distributing the intermediate data packet to be processed to each processing chipset so as to enable each processing chipset to process the intermediate data packet to be processed.
10. The method of claim 9, wherein the pending data packet includes a group identification of each processing chipset, wherein the pending intermediate data packet includes a plurality of pending intermediate sub-packets,
the method for obtaining the intermediate data packet to be processed by executing the preset operation on the data packet to be processed comprises the following steps:
and dividing the data packet to be processed into a plurality of intermediate data packets to be processed according to the group identification.
11. The method according to claim 9, characterized in that a secondary control chip is provided with a first communication interface and a second communication interface, the data format of the data packets to be processed is different from the data format of the intermediate data packets to be processed,
the method for obtaining the intermediate data packet to be processed by executing the preset operation on the data packet to be processed comprises the following steps:
and converting the data format of the data packet to be processed into the data transmission format of the first communication interface from the data transmission format of the second communication interface.
12. The method of claim 11, further comprising:
when a processing result data packet sent by a processing chipset is received, determining the result type of the processing result data packet, wherein the processing result data packet is obtained by the processing chipset based on the data packet to be processed;
and sending the processing result data packet to a main control chip through a communication interface corresponding to the result type in the first communication interface.
13. The method according to claim 12, wherein the processing result packet includes a plurality of sub-processing result packets and chip identifications respectively corresponding to the respective sub-processing result packets,
wherein the sending the processing result data packet to the main control chip through the communication interface corresponding to the result type in the first communication interface includes:
and sending a sub-processing result data packet and a chip identifier to the main control chip through a communication interface corresponding to the result type in the first communication interface, so that the main control chip determines the sub-chip used by the sub-processing result data packet according to the chip identifier.
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