CN116524973B - Address bit decoding circuit, method, electronic equipment and storage medium - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides an address bit decoding circuit, an address bit decoding method, electronic equipment and a storage medium, wherein an address holding pulse control signal is generated through a first clock pulse signal, the address decoder is controlled to finish decoding address bits within the address bit establishment time, and the latching of the address bits is finished at the moment of the high level state of the address holding pulse control signal. The delay generated by decoding and latching of the address decoder is eliminated, and the speed of ROM reading data is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to an address bit decoding circuit, an address bit decoding method, an electronic device, and a storage medium.
Background
As shown in fig. 1, which is a basic structure of a conventional ROM, the ROM is mainly composed of an address decoder, a memory array, an output control circuit, and the like, and the memory bank position to be read is selected by the address decoder, and the output control circuit operates on the corresponding memory bank position and reads the corresponding data. The data reading time of the ROM is the decoding and latching time of the address decoder and the time required by the output control circuit to execute related operations, so the output control circuit needs to wait for the address decoder to select the corresponding memory bank before operation, and therefore, the setting time of decoding and latching of the address decoder determines the data reading speed of the ROM.
The structure of the conventional address decoder is shown in fig. 2 or 3, in which in fig. 2, the address bits are latched by the D flip-flop and then decoded by the combination of the nand gate and the nor gate, and in fig. 3, the address bits are pre-decoded and then latched. Whether the address bits are latched first and then fully decoded or pre-decoded and then latched, as can be seen from the timing diagrams of fig. 4 and 5, the address bits are delayed, and the read data speed of the ROM is seriously affected by the delay time. Although the circuit structure in fig. 3 uses the setup time of the address bits to decode in advance, so as to shorten the decoding time, the circuit still generates delay, and the number of flip-flops is doubled, so that the cost is greatly increased. If the D trigger is removed, the address bits are not latched, and the address bits given by the system are changed continuously, so that the address bits are disordered when the ROM reads data, the power consumption is increased, and the data reading error is seriously caused.
Disclosure of Invention
The invention aims to provide an address bit decoding circuit, an address bit decoding method, an electronic device and a storage medium, which eliminate delay generated by decoding and latching of an address decoder and improve the speed of ROM data reading.
The invention provides an address bit decoding circuit, which comprises an address decoder;
generating a second clock pulse signal and an address holding pulse control signal based on the first clock pulse signal;
the address holding pulse control signal and the second clock pulse signal have the same frequency and different high-low level duty ratios;
the address holding pulse control signal controls the address decoder to decode the address bit within the address bit establishment time, and the address bit is latched at an instant of the high level state of the address holding pulse control signal.
Further, the address decoder includes a latch and a decoder,
when the address holding pulse control signal is in a low level state, the decoder is controlled to decode the address bits; the latch completes latching the address bit at an instant when the address hold pulse control signal is in a high state.
Further, the latch comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a fifth NOT gate;
the address holding pulse control signal is connected to the grid electrode of the first PMOS tube, and is connected to the grid electrode of the second NMOS tube through the first NOT gate; the source electrode of the first PMOS tube is connected with a reference voltage, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the gate electrode of the second PMOS tube is connected with an address bit input signal after being in common gate with the first NMOS tube, and the address bit input signal is output to the second NOT gate after passing through the drain electrode of the second PMOS tube and the source electrode of the first NMOS tube which are connected, and the address bit is output after passing through the second NOT gate and the third NOT gate in sequence; outputting an inverted address bit after passing through the second NOT gate, the third NOT gate and the fourth NOT gate; the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the drain electrode of the second NMOS tube is grounded; the fifth NOT gate is connected in parallel with the two ends of the second NOT gate, the input end of the fifth NOT gate is connected with the output end of the second NOT gate, and the output end of the fifth NOT gate is connected with the input end of the second NOT gate.
Further, the decoder comprises a first NAND gate, a second NAND gate, a first NOR gate and a buffer;
the third address bit and the enabling signal are connected to the input end of the first NAND gate, the zeroth address bit, the first address bit and the second address bit are connected to the output end of the second NAND gate, the output end of the first NAND gate and the output end of the second NAND gate are respectively connected with the input end of the first NAND gate, and after the output end of the first NAND gate is connected with the buffer, the buffer outputs a control signal.
The invention also provides an address bit decoding method, which comprises the following steps:
generating a second clock pulse signal and an address holding pulse control signal based on the first clock pulse signal;
the address holding pulse control signal and the second clock pulse signal have the same frequency and different high-low level duty ratios;
the address holding pulse control signal controls the address decoder to decode the address bit within the address bit establishment time, and the address bit is latched at an instant of the high level state of the address holding pulse control signal.
Further, when the address holding pulse control signal is in a low level state, the control decoder decodes the address bits; and when the address holding pulse control signal is in a high level state, the output control circuit performs related operation on the latched address bit storage unit and reads the content of the storage unit.
Further, when the address holding pulse control signal of low level is input and the address bit input signal of high level is input, the latch transfers the address bit to the decoder for decoding; the latch completes latching at an instant when the address hold pulse control signal is input in a high state.
Further, the decoder decodes the address bits when the enable signal is high, and stops decoding when the enable signal is low.
The present invention also provides an electronic device including: the electronic device comprises a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, when the electronic device runs, the processor and the storage medium are communicated through the bus, and the processor executes the machine-readable instructions to execute the address bit decoding method.
The present invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, performs the address bit decoding method described above.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention generates an address holding pulse control signal and a second clock pulse signal through the first clock pulse signal, and ensures that the frequency of the address holding pulse control signal is the same as that of the second clock pulse signal, the duty ratio of high and low levels is different, and the delay generated by decoding and latching of an address decoder is eliminated by the address holding pulse control signal, so that the speed of ROM reading data is improved.
Furthermore, compared with the traditional decoding circuit formed by combining a plurality of D flip-flops and logic gates, the latch and the decoder provided by the invention have the advantages that the area of the address decoder is small, and the production cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a ROM structure in the prior art;
FIG. 2 is a schematic diagram of an address decoder in the prior art;
FIG. 3 is a schematic diagram of another address decoder in the prior art;
FIG. 4 is a timing diagram of an address decoder according to the prior art;
FIG. 5 is another timing diagram of another address decoder according to the prior art;
FIG. 6 is a timing diagram of an address decoder according to a first embodiment of the present invention;
FIG. 7 is a schematic diagram of an address decoder according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a latch according to a first embodiment of the present invention;
fig. 9 is a schematic diagram of a decoder according to a first embodiment of the present invention.
Detailed Description
The following description of an address bit decoding circuit, method, electronic device and storage medium of the present invention, in conjunction with the accompanying schematic drawings, illustrates preferred embodiments of the present invention, it is to be understood that those skilled in the art may modify the invention described herein while still achieving the beneficial effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
In detail, referring to fig. 6, an address hold pulse control signal adrhold and a second clock pulse signal clki are generated based on a first clock pulse signal, decoding of address bits is completed within an address bit setup time, and latching of the address bits is completed at a moment of a high level state of the address hold pulse control signal adrhold.
And when the address holding pulse control signal adrhold is in a low level state, controlling the address decoder to decode the address bit, wherein the address decoder completes the latching of the address bit at the moment when the address holding pulse control signal adrhold is in a high level state.
In this embodiment, the first clock signal is a system clock signal, and the second clock signal clki is a pulse signal generated by the system clock signal to control decoding and latching of an address decoder in the prior art.
Specifically, referring to fig. 7, the address decoder includes a latch and a decoder, and the latch is used to perform a latching operation and the decoder is used to perform a decoding operation.
In general, the address hold pulse control signal adrhold performs a decoding operation of an address bit in a period from an nth rising edge (n is an integer greater than 1) to an n+1th rising edge, and at a low level, the latch completes latching at an instant when the address hold pulse control signal adrhold is in a high level state, and the output control circuit performs a correlation operation on the latched address bit memory cell and reads the memory cell content when the address hold pulse control signal adrhold is at a high level.
The second clock signal clki and the address holding pulse control signal adrhold are both generated from the first clock signal. The address holding pulse control signal adrhold has the same frequency as the second clock pulse signal clki, and has different high-low level duty ratios. It will be appreciated that the high and low level duty cycles of the period of the level signal may be dependent upon the particular ROM access speed, as compared to a faster ROM access speed, where the high level duty cycle may be set to be less and the low level duty cycle calculated therefrom. In a specific example, the access speed of the ROM is controlled to 20 megabytes per second, at this time, the time for which the second clock signal clki outputs the one-cycle level signal is set to 50 ns, and the address holding pulse control signal adrhold outputs the one-cycle level signal, that is, 50 ns. Assuming that the operation time required by the output control circuit is 30 nanoseconds, the high level time is set to be 30-35 nanoseconds, so that the information stored in the storage array is accurately transferred to the data port. At this time, all the other times are used as address bit decoding time, set to low level. When the address bit is decoded, and when the address hold pulse control signal adrhold is in a high level state, the latching of the address bit is completed.
Specifically, referring to fig. 8, the latch includes a first PMOS tube PM1, a second PMOS tube PM2, a first NMOS tube NM1, a second NMOS tube NM2, a first not gate N1, a second not gate N2, a third not gate N3, a fourth not gate N4, and a fifth not gate N5.
The address holding pulse control signal adrhold is connected to the gate of the first PMOS PM1 and is connected to the gate of the second NMOS NM2 through the first not gate N1; the source electrode of the first PMOS tube PM1 is connected with a reference voltage, the drain electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2, the drain electrode of the second PMOS tube PM2 is respectively connected with the source electrode of the first NMOS tube NM1 and the input end of the second NOT gate N2, the drain electrode of the first NMOS tube NM1 is connected with the source electrode of the second NMOS tube NM2, and the drain electrode of the second NMOS tube NM2 is grounded; the address bit input signal Addre is respectively input to the gate of the second PMOS PM2 and the gate of the first NMOS NM 1.
The drain electrode of the second PMOS PM2 is connected to the source electrode of the first NMOS MN1 and then connected to the input end of the second not gate N2, the output end of the second not gate N2 is connected to the input end of the third not gate N3, the output end of the third not gate N3 outputs an address bit and is connected to the input end of the fourth not gate N4, and the output end of the fourth not gate N4 outputs an inverted address bit; the fifth NOT gate N5 is connected in parallel with two ends of the second NOT gate N2, the input end of the fifth NOT gate N5 is connected with the output end of the second NOT gate N2, and the output end of the fifth NOT gate N5 is connected with the input end of the second NOT gate N2.
When the address holding pulse control signal adrhold is low and the address bit input signal Addre is high, the first PMOS tube PM1 is turned on, the second PMOS tube PM2 is turned on, the first NMOS tube NM1 is turned on, the second NMOS tube NM2 is also turned on, the output ends of the third not gate N3 and the fourth not gate N4 output an address bit and an inverted address bit (wherein the address bit is iaddr_n and the inverted address bit is IADDR), respectively, and the address bit is transferred into the decoder for decoding. When the address hold pulse control signal adrhold is in a high state, the latch latches all address bits decoded before. That is, the address bits latched in the latches will not change regardless of the change in the address bit input signal Addre.
In a specific example, the Address bit input signal Addre may be Address <3:0>, i.e. a 4-bit address bus, other bits of address bus and the values and positions of the most significant and least significant bits of the address bus can be set as desired.
Further, referring to fig. 9, the address decoder includes a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR and a Buffer.
The third address bit ADDR <3> and the enable signal CE are connected to the input end of the first NAND gate NAND1, the zeroth address bit ADDR <0>, the first address bit ADDR <1>, and the second address bit ADDR <2> are connected to the output end of the second NAND gate NAND2, the output end of the first NAND gate NAND1 and the output end of the second NAND gate NAND2 are respectively connected to the input end of the first NOR gate NOR, and after the output end of the first NOR gate NOR is connected to the Buffer, the Buffer outputs a control signal.
Specifically, before the decoding operation is required, the enable signal is controlled to be in a high level, address bits are accessed into the decoder, the decoder starts to execute the decoding operation, and the output control signal controls the memory array to select a memory cell or controls other circuits to perform subsequent operations.
The decoder decodes the 4-bit address bits into 16 control signals to control the storage array to select 16 rows or columns of storage cells.
In the prior art, n flip-flops or 2 are required n The n-bit address bit is latched by a plurality of flip-flops, so that the integration cost is high, and the latch method in the embodimentThe latch structure is simpler, and the manufacturing cost of the address decoder circuit is reduced.
Example two
The present embodiment provides an address bit decoding method, including the steps of:
generating a second clock signal clki and an address holding pulse control signal adrhold based on the first clock signal;
the address holding pulse control signal adrhold has the same frequency as the second clock pulse signal clki, and the high-low level duty ratio is different;
the address holding pulse control signal adrhold controls the address decoder to decode the address bit within the address bit establishment time, and completes the latching of the address bit at an instant of the high level state of the address holding pulse control signal adrhold.
In the prior art, the address bits are latched and decoded after the rising edge of the second clock pulse signal clki, and the next operation can be performed after waiting for the latching and decoding. Therefore, the latch-up and decoding times are both delay times. Another approach is to decode the address bits during the address setup time and latch them by flip-flops after the rising edge of the second clock signal clki. Thus, the latch time is the delay time.
In this embodiment, when the address hold pulse control signal adrhold is at a low level, the control decoder decodes, and the latch completes latching at an instant when the address bit hold line is at a high level, after which the address hold pulse control signal adrhold is kept at a high level for a period of time, the latch remains latched, and the output control circuit performs a related operation, and the latch is turned on until the next low level. In this embodiment, decoding of the address bits is completed before the rising edge of the second clock signal clki and latching of the address bits is completed at an instant when the address hold pulse control signal adrhold is in a high state, eliminating the delay time.
Further, when the address holding pulse control signal adrhold is at low level and the address bit input signal Addre is at high level, the decoder decodes; the latch completes latching the address bit at an instant when the address hold pulse control signal adrhold is in a high state. When the address hold pulse control signal adrhold is at a high level, the output control circuit performs a correlation operation on the latch address bit memory cell and reads the memory cell contents.
In addition, when the enable signal is at a high level, the decoder decodes the address bits, and when the enable signal is at a low level, the decoder stops decoding and outputs all "0" address bits.
In summary, the present invention generates an address hold pulse control signal adrhold and a second clock pulse signal clki through the first clock pulse signal, and makes the frequencies of the address hold pulse control signal adrhold and the second clock pulse signal clki be the same, the duty ratios of high and low levels are different, the address hold pulse control signal adrhold controls the address decoder to decode the address bits within the time of establishing the address bits, and to latch the address bits at a moment of the high level state of the address hold pulse control signal adrhold. The delay generated by decoding and latching of the address decoder is eliminated, and the speed of ROM reading data is improved.
In addition, compared with the traditional decoding circuit formed by combining a plurality of D flip-flops and logic gates, the latch and the decoder provided by the invention have the advantages that the area of the address decoder is small, and the production cost is reduced.
Example III
The embodiment also provides an electronic device, which may be a server, a computer, or the like.
The electronic device may include: the device comprises a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of the address bit decoding method as described in the second embodiment. The specific implementation manner and the technical effect are similar, and are not repeated here.
For ease of illustration, only one processor is depicted in the above-described electronic device. It should be noted, however, that in some embodiments, the electronic device of the present invention may also include multiple processors, and thus, steps performed by one processor described in the present invention may also be performed jointly by multiple processors or separately. For example, if the processor of the electronic device performs step a and step B, it should be understood that step a and step B may also be performed by two different processors together or performed separately in one processor. For example, the first processor performs step a, the second processor performs step B, or the first processor and the second processor collectively perform steps a and B, etc.
In some embodiments, a processor may include one or more processing cores (e.g., a single core processor (S) or a multi-core processor (S)). By way of example only, the Processor may include a central processing unit (Central Processing Unit, CPU), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), special instruction set Processor (Application Specific Instruction-set Processor, ASIP), graphics processing unit (Graphics Processing Unit, GPU), physical processing unit (Physics Processing Unit, PPU), digital signal Processor (Digital Signal Processor, DSP), field programmable gate array (Field Programmable Gate Array, FPGA), programmable logic device (Programmable Logic Device, PLD), controller, microcontroller unit, reduced instruction set computer (Reduced Instruction Set Computing, RISC), microprocessor, or the like, or any combination thereof.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. An address bit decoding circuit, comprising an address decoder;
generating a second clock pulse signal and an address holding pulse control signal based on the first clock pulse signal;
the address holding pulse control signal and the second clock pulse signal have the same frequency and different high-low level duty ratios;
the address holding pulse control signal controls the address decoder to decode the address bit within the address bit establishment time, and the address bit is latched at an instant of the high level state of the address holding pulse control signal.
2. An address bit decoding circuit according to claim 1, wherein the address decoder comprises a latch and a decoder,
when the address holding pulse control signal is in a low level state, the decoder is controlled to decode the address bits; the latch completes latching the address bit at an instant when the address hold pulse control signal is in a high state.
3. An address bit decoding circuit according to claim 2, wherein,
the latch comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a fifth NOT gate;
the address holding pulse control signal is connected to the grid electrode of the first PMOS tube, and is connected to the grid electrode of the second NMOS tube through the first NOT gate; the source electrode of the first PMOS tube is connected with a reference voltage, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the gate electrode of the second PMOS tube is connected with an address bit input signal after being in common gate with the first NMOS tube, and the address bit input signal is output to the second NOT gate after passing through the drain electrode of the second PMOS tube and the source electrode of the first NMOS tube which are connected, and the address bit is output after passing through the second NOT gate and the third NOT gate in sequence; outputting an inverted address bit after passing through the second NOT gate, the third NOT gate and the fourth NOT gate; the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the drain electrode of the second NMOS tube is grounded; the fifth NOT gate is connected in parallel with the two ends of the second NOT gate, the input end of the fifth NOT gate is connected with the output end of the second NOT gate, and the output end of the fifth NOT gate is connected with the input end of the second NOT gate.
4. An address bit decoding circuit according to claim 3, wherein,
the decoder comprises a first NAND gate, a second NAND gate, a first NOR gate and a buffer;
the third address bit and the enabling signal are connected to the input end of the first NAND gate, the zeroth address bit, the first address bit and the second address bit are connected to the output end of the second NAND gate, the output end of the first NAND gate and the output end of the second NAND gate are respectively connected with the input end of the first NAND gate, and after the output end of the first NAND gate is connected with the buffer, the buffer outputs a control signal.
5. A method of address bit decoding employing the address bit decoding circuit of any one of claims 1-4, the method comprising:
generating a second clock pulse signal and an address holding pulse control signal based on the first clock pulse signal;
the address holding pulse control signal and the second clock pulse signal have the same frequency and different high-low level duty ratios;
the address holding pulse control signal controls the address decoder to decode the address bit within the address bit establishment time, and the address bit is latched at an instant of the high level state of the address holding pulse control signal.
6. The method of claim 5, wherein,
decoding the address bits when the address holding pulse control signal is in a low level state; when the address holding pulse control signal is in a high level state at one moment, the address bit is latched; and when the address holding pulse control signal is at a high level, performing related operation on the latch address bit memory cell and reading the content of the memory cell.
7. The method of claim 5, wherein,
when the address holding pulse control signal with low level is input and the address bit input signal with high level is input, the latch transfers the address bit to the decoder for decoding; the latch completes latching at an instant when the address hold pulse control signal is input in a high state.
8. The method of claim 5, wherein,
the decoder decodes the address bits when the enable signal is high, and stops decoding when the enable signal is low.
9. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the steps of the method of any one of claims 5 to 8.
10. A storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method according to any of claims 5 to 8.
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| KR20070071466A (en) * | 2005-12-30 | 2007-07-04 | 주식회사 하이닉스반도체 | Command decoding circuit of semiconductor memory device |
| CN103093805A (en) * | 2011-11-08 | 2013-05-08 | 海力士半导体有限公司 | Address decoding method and semiconductor memory device using the same |
| US8923090B1 (en) * | 2013-09-24 | 2014-12-30 | Lsi Corporation | Address decoding circuits for reducing address and memory enable setup time |
| CN105976856A (en) * | 2016-06-29 | 2016-09-28 | 安徽大学 | Latch-type flow line structure high-speed address decoder applied in static random access memory |
| WO2023103148A1 (en) * | 2021-12-06 | 2023-06-15 | 长鑫存储技术有限公司 | Address refresh circuit, method, memory, and electronic device |
| CN115905096A (en) * | 2022-11-17 | 2023-04-04 | 常州星宇车灯股份有限公司 | SPI-based data communication system and method |
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