CN115033515A - Master-slave SPI communication method - Google Patents
Master-slave SPI communication method Download PDFInfo
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- CN115033515A CN115033515A CN202210579427.6A CN202210579427A CN115033515A CN 115033515 A CN115033515 A CN 115033515A CN 202210579427 A CN202210579427 A CN 202210579427A CN 115033515 A CN115033515 A CN 115033515A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A master-slave SPI communication method comprises the following steps: step 1, each slave computer is in a waiting state, and a master computer chip selection signal end sends out a chip selection starting signal; step 2, each slave computer receives a chip selection starting signal and enters an address comparison state; step 3, each slave compares the address information received from the MOSI signal line with the self address information in the address comparison state; step 4, the host continuously sends data information after sending address information from the MOSI signal line, and the slave which enters a data receiving state continuously receives the data information sent by the MOSI signal line; and 5, after the slave in the data receiving state receives the chip selection end signal, ending data receiving and entering a waiting state. Compared with the prior art, the invention can complete normal SPI multi-slave communication by only 4 interfaces through combining the IIC framework under the condition of having a plurality of slaves, and reduces the interface bus of the master and the internal data connecting line of the system.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a master-slave SPI communication method.
Background
The SPI is an abbreviation of a Serial Peripheral Interface (Serial Peripheral Interface), is a high-speed, full-duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, saving the pins of the chip, and providing convenience for saving space on the layout of the PCB, and due to the simple and easy-to-use characteristic, more and more chips integrate the communication protocol.
As shown in fig. 2, when a plurality of slaves are provided under the SPI protocol, each slave needs to receive a chip select () signal line from the master as a chip select signal, which results in a large number of interface lines of the master and a large number of occupied resources. Miso (master Input Slave output) in fig. 2 represents master device data Input and Slave device data output; mosi (master Output Slave input) indicating data Output of the master device and data input of the Slave device; SCK (Serial clock) is a clock terminal; SS is the chip select signal terminal.
Conventional I 2 The protocol C architecture is shown in fig. 3, each slave device has only two interfaces, and uses a half-duplex working mode, and data transmission is slow, in fig. 3, SDA represents a data transmission line under the IIC protocol, and SCL is a clock signal line.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention discloses a master-slave SPI communication method.
The master-slave SPI communication method comprises the following steps:
step 2, each slave machine receives a chip selection starting signal and enters an address comparison state; after sending out a chip selection starting signal, the host sends out address information from an MOSI signal line;
step 3, each slave compares the address information received from the MOSI signal line with the self address information in the address comparison state, the slave which is matched with the slave is switched into a data receiving state, and the slave which is not matched with the slave is switched into a waiting state;
step 4, the host continuously sends data information after sending address information from the MOSI signal line, and the slave in the state of receiving data continuously receives the data information sent by the MOSI signal line until the master chip selection signal end sends a chip selection end signal;
and 5, after the slave in the data receiving state receives the chip selection end signal, ending data receiving and entering a waiting state.
Preferably, the chip selection start signal and the chip selection end signal are respectively a falling edge and a rising edge.
Preferably, the state switching between the master and the slave is controlled by a clock signal transmitted from the master.
Preferably, the host sends the address information and the data information at least 1 clock cycle apart.
The master-slave SPI communication method has the following technical advantages that:
compared with the prior art, under the condition that a plurality of slave machines are provided, by combining the IIC framework, a single SPI host machine can complete normal SPI multi-slave machine communication by only needing 4 interfaces, and interface buses and system internal data connecting lines of the host machine are reduced.
And each slave machine can send data to the host machine while receiving the data, so that a full-duplex working mode is realized, and the data transmission interaction speed is accelerated.
The existing SPI master-slave structure can be completely compatible, only one chip selection signal interface of a host is used, connection relations of other hardware do not need to be changed, and the existing system is favorably modified.
Drawings
Fig. 1 is a schematic diagram of a host-slave architecture according to an embodiment of the master-slave SPI communication method of the present invention;
FIG. 2 is a block diagram of a conventional master-slave SPI communication method;
FIG. 3 shows a conventional I 2 A schematic diagram of an embodiment of the communication method;
fig. 4 is a timing diagram of partial signals and slave status in an embodiment of the master-slave SPI communication method according to the present invention.
Detailed Description
The following provides a more detailed description of the present invention.
The master-slave SPI communication method is based on an SPI communication bus protocol and adopts 1 SPI host to communicate a plurality of slave machines.
In the present invention, a specific connection relationship between a Master and a Slave is shown in fig. 1, and the Master and a plurality of slaves respectively pass through MISO signal lines (Master Input Slave Output represents Master device data Input and Slave device data Output) in an SPI bus; MOSI signal lines (Master Output Slave Input, which indicate Master device data Output and Slave device data Input); the SCK signal line (Clock signal) and the chip select signal line are connected correspondingly.
In one embodiment shown in fig. 1, there are 3 slaves, and as shown in fig. 1, the chip select signal terminal SS of the master is connected to the chip select signal terminals SS1, SS2, and SS3 of 3 different slaves at the same time, and the master and the slave respectively have MISO terminal, MOSI terminal, and SCK terminal, and are connected to the MISO signal line, MOSI signal line, and SCK signal line, respectively
The master-slave SPI communication method specifically comprises the following steps:
step 2, each slave computer receives a chip selection starting signal and enters an address comparison state; after sending out a chip selection starting signal, the host sends out address information from an MOSI signal line;
step 3, each slave compares the address information received from the MOSI signal line with the self address information in the address comparison state, the slave which is matched with the slave is switched into a data receiving state, and the slave which is not matched with the slave is switched into a waiting state;
step 4, the host continues to send data information after sending address information from the MOSI signal line, and the slave which enters a data receiving state continuously receives the data information sent by the MOSI signal line until the chip selection signal end of the host sends a chip selection end signal;
and 5, after the slave in the data receiving state receives the chip selection end signal, ending data receiving and entering a waiting state.
Fig. 4 is a timing diagram illustrating a transmission signal on the MOSI signal line, a transmission signal on the chip select signal line SS, an operating state of the slave 1, and an operating state of the slave 2, respectively, from top to bottom in fig. 4.
As shown in fig. 4, in the initial state, each slave is in the standby state, and for the master, a chip select start signal should be sent first, and each slave is transferred to the address comparison state, and the chip select start signal is sent from the chip select terminal. In the specific embodiment shown in fig. 4, a chip select signal takes a falling edge as a chip select start signal, the chip select signal is high level in an initial state, the chip select signal is converted into low level through a falling edge, and each slave enters an address comparison state in a low level state of the chip select signal.
After the master sends out a chip selection starting signal, address information is sent out from the MOSI end, each slave receives the address information and compares whether the address information is consistent with the self address in the address comparison state, the slave with the consistent address enters a data receiving state, and the slave with the inconsistent address automatically switches back to a waiting state to wait for the next chip selection starting signal.
After the host sends the address information, the data information is sent, and one or more idle clock cycles can be set between the address information and the data information to wait for the slave to receive the address information for consistency judgment.
In the specific implementation shown in fig. 4, a rising edge of the chip selection signal is used as the chip selection end signal, and after the rising edge, the chip selection signal is restored to the initial high level state before the chip selection.
And after the slave in the data receiving state receives the chip selection end signal, the slave finishes data receiving and returns to the initial waiting state again.
In the above process, the clock signal line SCK connected between the master and the slave continuously transmits a clock signal, and the transmission timing of each signal transmitted from the master and the state switching of the slave are performed depending on the clock signal line SCK.
In the above process, the MISO signal line is not used in the whole process, and each slave can still transmit data or a response signal to the master using the MISO signal line while receiving data.
In the above embodiments, the chip selection start signal and the chip selection end signal sent by the chip selection signal respectively adopt a falling edge and a rising edge, and those skilled in the art know that the other signal determination methods may be adopted instead or in other manners.
The address information and the data information sent by the MOSI signal line can adopt any format conforming to an SPI communication protocol, simultaneously switch the working states of the host and the slave, and also can adopt a mode of combining chip selection signals, MOSI signal lines and MISO signal lines for signal transmission, and the mode of judging by only using the chip selection signals is the simplest specific implementation mode.
The master-slave SPI communication method has the following technical advantages that:
in contrast to the prior art, in the case of multiple slaves, by combining I 2 C structure, single SPI host computer only needs 4 interfaces just can accomplish normal many slaves of SPI communication, reduces the interface bus and the inside data link of system of host computer.
And each slave machine can send data to the host machine while receiving the data, so that a full-duplex working mode is realized, and the data transmission interaction speed is accelerated.
The existing SPI master-slave structure can be completely compatible, only one chip selection signal interface of a host is used, connection relations of other hardware do not need to be changed, and the existing system is favorably modified.
In the embodiments provided in the present application, the functions described above are implemented in the form of software functional units and may be stored in a non-volatile computer-readable storage medium executable by a processor when the functions are sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention, where the storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The foregoing is directed to preferred embodiments of the present invention, wherein the preferred embodiments are not obviously contradictory or subject to any particular embodiment, and any combination of the preferred embodiments may be combined in any overlapping manner, and the specific parameters in the embodiments and examples are only for the purpose of clearly illustrating the inventor's invention verification process and are not intended to limit the scope of the invention, which is defined by the claims and the equivalent structural changes made by the description and drawings of the present invention are also intended to be included in the scope of the present invention.
Claims (4)
1. A master-slave SPI communication method is characterized by comprising the following steps:
step 1, each slave is in a waiting state, and a master chip selection signal end sends a chip selection starting signal;
step 2, each slave machine receives a chip selection starting signal and enters an address comparison state; after sending out a chip selection starting signal, the host sends out address information from an MOSI signal line;
step 3, each slave compares the address information received from the MOSI signal line with the self address information in the address comparison state, the slave which is matched with the slave is switched into a data receiving state, and the slave which is not matched with the slave is switched into a waiting state;
step 4, the host continuously sends data information after sending address information from the MOSI signal line, and the slave in the state of receiving data continuously receives the data information sent by the MOSI signal line until the master chip selection signal end sends a chip selection end signal;
and 5, after the slave in the data receiving state receives the chip selection end signal, ending data receiving and entering a waiting state.
2. The master-slave SPI communication method of claim 1, wherein said chip select start signal and chip select end signal are a falling edge and a rising edge, respectively.
3. The master-slave SPI communication method of claim 1, wherein the master-slave state switching is controlled by a clock signal issued by the master.
4. The master-slave SPI communication method of claim 1, wherein the host transmits the address information and the data information at least 1 clock cycle apart.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210579427.6A CN115033515A (en) | 2022-05-26 | 2022-05-26 | Master-slave SPI communication method |
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| CN202210579427.6A CN115033515A (en) | 2022-05-26 | 2022-05-26 | Master-slave SPI communication method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155861A (en) * | 2023-04-20 | 2023-05-23 | 杭州视芯科技股份有限公司 | Wired communication system and configuration method of device ID thereof |
| CN117076373A (en) * | 2023-10-16 | 2023-11-17 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
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| CN2710264Y (en) * | 2004-03-09 | 2005-07-13 | 国电南京自动化股份有限公司 | Time-division multiple real-time communication bus |
| CN102088386A (en) * | 2011-01-20 | 2011-06-08 | 中北大学 | Universal serial bus (USB) for master-slave interconnection module of circuit system |
| CN105446930A (en) * | 2015-12-25 | 2016-03-30 | 吉林大学 | Single selection end SPI (Serial Peripheral Interface) master-slave multi-machine bidirectional communication method |
| CN113132198A (en) * | 2021-03-26 | 2021-07-16 | 东信和平科技股份有限公司 | SPI (Serial peripheral interface) safety communication device and communication method for multiple masters and one slave |
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- 2022-05-26 CN CN202210579427.6A patent/CN115033515A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2710264Y (en) * | 2004-03-09 | 2005-07-13 | 国电南京自动化股份有限公司 | Time-division multiple real-time communication bus |
| CN102088386A (en) * | 2011-01-20 | 2011-06-08 | 中北大学 | Universal serial bus (USB) for master-slave interconnection module of circuit system |
| CN105446930A (en) * | 2015-12-25 | 2016-03-30 | 吉林大学 | Single selection end SPI (Serial Peripheral Interface) master-slave multi-machine bidirectional communication method |
| CN113132198A (en) * | 2021-03-26 | 2021-07-16 | 东信和平科技股份有限公司 | SPI (Serial peripheral interface) safety communication device and communication method for multiple masters and one slave |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155861A (en) * | 2023-04-20 | 2023-05-23 | 杭州视芯科技股份有限公司 | Wired communication system and configuration method of device ID thereof |
| CN116155861B (en) * | 2023-04-20 | 2023-07-11 | 杭州视芯科技股份有限公司 | Wired communication system and configuration method of device ID thereof |
| CN117076373A (en) * | 2023-10-16 | 2023-11-17 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
| CN117076373B (en) * | 2023-10-16 | 2024-02-27 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
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