CN113132198B - Multi-master-slave SPI (Serial peripheral interface) safety communication device and communication method - Google Patents

Abstract

The invention relates to the technical field of communication, and discloses a multi-master-slave SPI (serial peripheral interface) safety communication device and a communication method, wherein the multi-master-slave SPI safety communication device comprises: an SPI bus switching circuit; the SPI slave device is in bidirectional connection with the SPI bus switching circuit; the SPI bus switching circuit is used for isolating the SPI master device from the SPI bus; SPI bus competition circuit, SPI bus competition circuit respectively with SPI slave unit and a plurality of SPI master device both way junction for control SPI master device is to the permission of SPI bus. The invention has at least the following beneficial effects: in an embedded system adopting SPI communication, when a plurality of SPI hosts need to access the same SPI slave device, the communication purpose can be realized without increasing the number of SPI interfaces of the SPI slave device.

Description

Multi-master-slave SPI (Serial peripheral interface) safety communication device and communication method

Technical Field

The invention relates to the technical field of communication, in particular to a multi-master-slave SPI (serial peripheral interface) safety communication device and a communication method.

Background

The SPI communication protocol specification specifies: the topological structure of the system is in a mode of one host and multiple slaves, and in the communication process, the host actively initiates communication to interact with the selected slaves. In practical applications there is a case: in the SPI communication topology, there are multiple masters and a slave, and the masters need to communicate with the slaves, and in the prior art, in an embedded system, the system uses SPI communication interfaces, and when two devices as masters need to access the slaves, the slaves need to have two slave SPI interfaces, otherwise, communication cannot be performed, so to speak, there is no better way to implement a communication mode of multiple masters and one slave.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a SPI safety communication device with multiple masters and one slave, which can realize a communication method of multiple masters and one slave in an SPI communication mode.

The invention also provides a multi-master-slave SPI communication method of the multi-master-slave SPI safety communication device.

A multi-master-slave SPI secure communication device according to an embodiment of a first aspect of the present invention comprises: an SPI bus switching circuit; the SPI slave device is connected with the SPI bus switching circuit in a bidirectional mode; the SPI bus switching circuit is used for isolating the SPI bus from an SPI bus; and the SPI bus competition circuit is in bidirectional connection with the SPI slave device and the SPI master devices respectively and is used for controlling the use permission of the SPI master device to the SPI bus.

According to some embodiments of the present invention, the SPI bus switching circuit includes a plurality of first chips having chip selection terminals, the first chips can control their input pins and output pins to be in a through state or a high impedance state according to an enable state of a chip selection terminal signal, and the number of the first chips is equal to the number of the SPI master devices.

According to some embodiments of the present invention, the first chip includes four pairs of input and output pins, and a first input pin, a second input pin, a third input pin, and a fourth output pin of the input and output pins are respectively connected to an SSN pin, a CLK pin, an MOSI pin, and an MISO pin of the SPI master device; and a first output pin, a second output pin, a third output pin and a fourth input pin of the input/output pins are respectively connected with an SSN pin, a CLK pin, an MOSI pin and an MISO pin of the SPI slave device through SPI buses.

According to some embodiments of the present invention, the chip select terminal is connected to an IO port of the SPI master device, and the enable state of the first chip is controlled through the IO port of the SPI master device.

According to some embodiments of the invention, the first chip comprises a 74HC125 chip.

According to some embodiments of the invention, the SPI bus contention circuit comprises a pull-up resistor connected at one end to a circuit power supply and at the other end to an IO port of the plurality of SPI master devices.

According to some embodiments of the present invention, the input/output mode of the IO port of the SPI master device is configured to be an open-drain mode, and is used for determining an SPI bus occupation state.

According to a second aspect of the invention, the method for SPI communication of multiple masters and one slave comprises the following steps: the SPI main equipment receives a data transmission command and judges whether an SPI bus is available or not according to the data transmission command; and if the SPI bus state is available, switching the SPI master device to monopolize the SPI bus for data transmission.

According to some embodiments of the invention, the determining whether the SPI bus is available according to the data transmission instruction comprises: reading the level of the IO port of the SPI main equipment; and if the level is high level, setting the level of the IO port as low level.

According to some embodiments of the present invention, the switching the SPI master device exclusively occupies the SPI bus for data transmission comprises: controlling a chip selection end of a first chip to be in an enabling state through an IO port of the SPI main equipment; the SPI master device carries out data transmission with the SPI slave device through the first chip; if the data transmission is finished, controlling a chip selection end of the first chip to be in a failure state through an IO port of the SPI main equipment; and setting the IO port level as a high level.

The SPI safety communication device with the plurality of masters and the slave according to the embodiment of the invention at least has the following beneficial effects: in an embedded system adopting SPI communication, when a plurality of SPI hosts access the same SPI slave equipment, the communication purpose can be realized without increasing the number of SPI interfaces of the SPI slave.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of module connections of an SPI bus switching circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram of an SPI bus contention circuit according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of a method according to a first embodiment of the present invention;

FIG. 5 is a flowchart illustrating a method according to a second embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

It should be understood that, the sequence numbers of the steps in the embodiments of the present invention do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the inherent logic of the process, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

In the description of the present invention, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and larger, smaller, larger, etc. are understood as excluding the present numbers, and larger, smaller, inner, etc. are understood as including the present numbers. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

Interpretation of terms:

SPI: the Peripheral interface is an abbreviation of a Serial Peripheral interface, is a Serial Peripheral Interface (SPI), is a high-speed, full-duplex and Synchronous communication bus, adopts a Master-Slave mode (Master-Slave) control mode, and adopts a Synchronous mode (Synchronous) to transmit data;

and (3) SSN: a slave enable signal controlled by the master device;

CLK: a Serial Clock, generated by the master device;

MOSI: master Output Slave Input, master device data Output, slave device data Input;

MISO: master Input Slave Output, master device data Input, slave device data Output;

IO: and an input/output port.

Referring to fig. 1, fig. 1 is a schematic block diagram of an apparatus according to an embodiment of the present invention, including:

an SPI bus switching circuit;

the SPI slave device is in bidirectional connection with the SPI bus switching circuit;

the SPI bus switching circuit is used for isolating the SPI bus from the SPI bus;

SPI bus competition circuit, SPI bus competition circuit respectively with SPI slave unit and a plurality of SPI main equipment both way junction for control SPI main equipment is to the permission of use of SPI bus.

It should be noted that, by using the SPI bus switching circuit and the SPI bus contention circuit, a plurality of SPI masters can select one SPI master to communicate with the SPI slave through the SPI bus contention circuit, and the technical problem that only one SPI master can communicate with a plurality of SPI slaves in the prior art is solved.

As shown in fig. 1, when the SPI master device accesses the SPI slave device, the use permission of the SPI bus is acquired from the SPI bus contention circuit, the SPI bus is occupied by the SPI bus switching circuit, the SPI bus is isolated from other devices, the SPI bus is used for data transmission, and after the data transmission is completed, the SPI bus is released for isolation, and the SPI bus contention state is released.

In some embodiments of the present invention, the SPI bus switching circuit includes a plurality of first chips having chip selection terminals, the first chips can control their input pins and output pins to be in a through state or a high impedance state according to an enable state of a chip selection terminal signal, and the number of the first chips is equal to the number of the SPI master devices.

Fig. 2 shows a module connection schematic diagram of an SPI bus switching circuit according to a specific embodiment of the present invention, as shown in fig. 2, the first chip is 74H125D, wherein the number of 74H125D is equal to the number of SPI master devices, it is to be understood that the number here is not limited, and may be any number greater than 11, wherein 74H125D has a chip select end OE, and when OE is in an enable state, 74H125D is selected, through which the SPI master device can communicate with the SPI slave device, it is understood that the number of pins of 74H125D can completely satisfy the communication requirement of the SPI master device and the SPI slave device.

In some embodiments of the present invention, the first chip includes four pairs of input/output pins, and a first input pin, a second input pin, a third input pin, and a fourth output pin of the input/output pins are respectively connected to an SSN pin, a CLK pin, an MOSI pin, and an MISO pin of the SPI master device;

and a first output pin, a second output pin, a third output pin and a fourth input pin of the input and output pins are respectively connected with an SSN pin, a CLK pin, an MOSI pin and an MISO pin of the SPI slave device through SPI buses.

In a specific embodiment, the first chip is a 74H125D chip, and the chip has 4 pairs of input/output ports, wherein the first pair of input/output ports is 1A/1Y, and is connected to the SSN port of the SPI master device and the SSN port of the SPI slave device; the second pair of input/output ports is 2A/2Y and is connected with the CLK port of the SPI master device and the CLK port of the SPI slave device; the third pair of input and output ports is 3A/3Y and is connected with the MOSI port of the SPI master device and the MOSI port of the SPI slave device; and the fourth pair of input/output ports is 4A/4Y, is connected with the MISO port of the SPI master device and the MISO port of the SPI slave device, and is used for realizing the communication between the SPI slave device and the SPI master device through a 74H125D chip.

In some specific embodiments of the present invention, the chip select terminal is connected to an IO port of the SPI master device, and the enable state of the first chip is controlled through the IO port of the SPI master device.

In a specific embodiment, the first chip is a 74H125D chip, the 74H125D chip has a chip selection end OE, the chip selection end OE is connected to the SPI master device, and the enable state of the 74H125D chip can be controlled through an IO port of the SPI master device, where an OE port of each 74H125D chip is connected to an I/O port of the SPI master device connected to the OE port.

In some embodiments of the invention, the first chip comprises a 74HC125 chip.

In a specific embodiment, referring to fig. 2, the SPI bus switching circuit is designed by using a bus isolation chip, where the bus isolation chip is a 74H125D chip, when an OE pin of the bus isolation chip is in an enabled state, an input pin (a pin) and an output pin (Y) are in a through state, and when the OE pin is in a disabled state, the input pin (a pin) and the output pin (Y pin) are in a high-impedance state, a corresponding SPI master device is isolated from the SPI bus, thereby avoiding interference with the SPI bus.

Fig. 3 is a schematic diagram illustrating module connection of an SPI bus contention circuit according to an embodiment of the present invention, where, as shown in fig. 3, the SPI bus contention circuit includes a pull-up resistor, one end of the pull-up resistor is connected to a circuit power supply, and the other end of the pull-up resistor is connected to IO ports of a plurality of SPI master devices.

In some embodiments of the present invention, the input/output mode of the IO port of the SPI master device is configured to be an open drain mode, and is used for determining the SPI bus occupation state. It can be understood that when a plurality of open-drain output pins are connected to a line, through a pull-up resistor, without adding any device, a logical and relationship can be formed, I/O of a plurality of single-chip microcomputers and other devices is in an open-drain form, or can be configured in an open-drain output form, for example, a P0 port of 51 single-chip microcomputers is in an open-drain output form, in the scheme, pins of the open-drain outputs of a plurality of IO ports are connected to a line, a logical and line relationship is formed, through connecting a pull-up resistor, when any one of the pins is changed into a logical 0, the logical on the open-drain line is 0, and the occupation state of the SPI bus is judged through the method.

In a specific embodiment of the present invention, as shown in fig. 3, an input/output mode of an IO port of each SPI master device is configured to be an open-drain mode, and when the SPI master device does not need to use an SPI bus, the IO port outputs a logic high level, and when the SPI master device acquires a transmission right of the SPI bus, the IO port outputs a logic low level. When SPI bus transmission authority competition is being carried out to master equipment, need judge SPI bus state earlier, indicate that the SPI bus is in idle state for logic high level when SPI bus state, can be with IO mouth output as logic low level, indicate that the SPI bus has occupied, other SPI master equipment must wait until obtaining SPI bus use authority.

Referring to fig. 4, fig. 4 is a schematic flow chart of a method according to a first embodiment of the present invention, the method includes the following steps:

the SPI master device receives the data transmission command and judges whether the SPI bus is available according to the data transmission command;

and if the SPI bus state is available, switching the SPI master device to monopolize the SPI bus for data transmission.

In some embodiments of the present invention, determining whether the SPI bus is available according to the data transmission command includes:

reading the level of an IO port of the SPI main equipment;

if the electrical level is high level, it indicates that the SPI bus is idle at this time, and is in an available state, the electrical level of the IO port is set to low level, and the SPI bus is occupied by the SPI master device at this time.

Switching the SPI main equipment to monopolize the SPI bus for data transmission comprises the following steps:

controlling a chip selection end of the first chip to be in an enabling state through an IO port of the SPI main device;

the SPI master device carries out data transmission with the SPI slave device through the first chip;

if the data transmission is finished, controlling a chip selection end of the first chip to be in a failure state through an IO port of the SPI main equipment;

and setting the IO port level as a high level, and recovering the SPI bus to be in an idle state.

Fig. 5 is a schematic flow chart of a method according to a second embodiment of the present invention, where the flow chart includes an SPI bus contention flow and an SPI bus switching and using flow, and when in use, the usage right of the SPI bus must be acquired first, and then other master devices are isolated to perform data communication. According to the aforesaid, can be for enabling state through the chip select end of the first chip of IO mouth control of SPI main equipment to this step that realizes switching the SPI bus can be through setting up the bus competition flow that the IO mouth level monopolizes the SPI bus for the low level, need judge whether the IO mouth is the high level at present before setting up the IO mouth level for the low level, if for the high level explanation present SPI bus is idle state, can set up the IO mouth level as the low level and occupy and realize the transmission data flow.

The scheme designs a communication mode which can enable a plurality of hosts to access the same slave in an SPI bus topological structure, and has the characteristics of simple realization, high communication efficiency and low cost.

Although specific embodiments have been described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are equally within the scope of this disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various illustrative implementations and architectures have been described in accordance with embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications of the illustrative implementations and architectures herein are also within the scope of the present disclosure.

Certain aspects of the present disclosure are described above with reference to block diagrams and flowchart illustrations of systems, methods, systems, and/or computer program products according to example embodiments. It will be understood that one or more blocks of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by executing computer-executable program instructions. Also, according to some embodiments, some blocks of the block diagrams and flow diagrams may not necessarily be performed in the order shown, or may not necessarily be performed in their entirety. In addition, additional components and/or operations beyond those shown in block diagrams and flow diagrams may be present in certain embodiments.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special purpose hardware and computer instructions.

A program module, application, etc., herein can comprise one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality herein (e.g., one or more operations of the illustrative methods herein) to be performed.

The software components may be encoded in any of a variety of programming languages. An illustrative programming language may be a low-level programming language, such as assembly language associated with a particular hardware architecture and/or operating system platform. Software components that include assembly language instructions may need to be converted by an assembler program into executable machine code prior to execution by a hardware architecture and/or platform. Another exemplary programming language may be a higher level programming language, which may be portable across multiple architectures. Software components that include higher level programming languages may need to be converted to an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages include, but are not limited to, a macro language, a shell or command language, a job control language, a scripting language, a database query or search language, or a report writing language. In one or more exemplary embodiments, a software component containing instructions of one of the above programming language examples may be executed directly by an operating system or other software component without first being converted to another form.

The software components may be stored as files or other data storage constructs. Software components of similar types or related functionality may be stored together, such as in a particular directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (8)

1. A multi-master-slave SPI secure communications device, comprising:

an SPI bus switching circuit;

the SPI slave device is bidirectionally connected with the SPI bus switching circuit;

the SPI bus switching circuit is used for isolating the SPI master device from an SPI bus;

the SPI bus competition circuit is respectively connected with the SPI slave device and the SPI master devices in a bidirectional mode and is used for controlling the use permission of the SPI master devices to the SPI buses;

the SPI bus switching circuit comprises a plurality of first chips with chip selection ends, the first chips can control input pins and output pins of the first chips to be in a through state or a high-resistance state according to the enabling state of signals of the chip selection ends, and the number of the first chips is equal to that of the SPI main equipment;

the SPI bus competition circuit comprises a pull-up resistor, one end of the pull-up resistor is connected with a circuit power supply, and the other end of the pull-up resistor is connected with IO ports of the SPI main devices.

2. The SPI secure communication apparatus according to claim 1, wherein the first chip comprises four pairs of input/output pins, and wherein a first input pin, a second input pin, a third input pin, and a fourth output pin of the input/output pins are connected to an SSN pin, a CLK pin, an MOSI pin, and a MISO pin of the SPI master, respectively;

and a first output pin, a second output pin, a third output pin and a fourth input pin of the input and output pins are respectively connected with an SSN pin, a CLK pin, an MOSI pin and an MISO pin of the SPI slave device through SPI buses.

3. The SPI safety communication device of claim 1, wherein the chip select terminal is connected to an IO port of the SPI master device, and the enable state of the first chip is controlled through the IO port of the SPI master device.

4. A multi-master-slave SPI secure communications device according to claim 1 and wherein said first chip comprises a 74HC125 chip.

5. The SPI safety communication device of claim 1, wherein the input/output mode of the IO port of the SPI master device is configured as an open-drain mode for determining the status of an SPI bus.

6. A multi-master-slave SPI communication method based on the multi-master-slave SPI secure communication device according to any one of claims 1 to 5, comprising the steps of:

the SPI master device receives a data transmission instruction and judges whether an SPI bus is available according to the data transmission instruction;

and if the SPI bus state is available, switching the SPI master device to monopolize the SPI bus for data transmission.

7. The SPI communication method of claim 6, wherein the determining whether an SPI bus is available according to the data transmission command comprises:

reading the level of the IO port of the SPI main equipment;

and if the level is high level, setting the level of the IO port as low level.

8. The SPI communication method of claim 6, wherein the switching the SPI master device exclusively uses the SPI bus for data transmission comprises:

controlling a chip selection end of the first chip to be in an enabling state through an IO port of the SPI main device;

the SPI master device carries out data transmission with the SPI slave device through the first chip;

if the data transmission is finished, controlling a chip selection end of the first chip to be in a failure state through an IO port of the SPI main equipment;

and setting the IO port level as a high level.

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