CN212324117U

CN212324117U - RS485 bus multi-host competition switching system

Info

Publication number: CN212324117U
Application number: CN202021392186.7U
Authority: CN
Inventors: 张浩彬; 谭东超; 刘跃武
Original assignee: Shenzhen Tianci Technology Co ltd
Current assignee: Shenzhen Tianci Technology Co ltd
Priority date: 2020-07-15
Filing date: 2020-07-15
Publication date: 2021-01-08
Anticipated expiration: 2030-07-15

Abstract

The utility model discloses a many host computers of RS485 bus compete switched systems, including a host computer, a plurality of unit controller and a plurality of slave computer equipment, the host computer all is connected with a plurality of slave computer equipment on every single chip microcomputer controller through a RS485 bus connection a plurality of single chip microcomputer controllers, and all slave computer equipment all link together through RS485 circuit, the beneficial effects of the utility model are that: (1) whether a host exists on the bus is confirmed by detecting data on the bus, and accurate judgment can be completed without intervention of an external controller. (2) The parallel single-machine equipment can be ensured to be used as the host machine after being electrified every time, and additional arrangement is not needed.

Description

RS485 bus multi-host competition switching system

Technical Field

The utility model relates to the field of communication technology, specifically a RS485 bus multi-host competition switching system.

Background

The existing RS485 bus generally has only one host, and a superior controller is often used for controlling and switching master-slave modes under the condition that two hosts conflict possibly. By switching the master-slave mode of the RS485 by the superior controller, once the superior controller is separated from the controller, the two hosts always compete for the control right of the bus, so that the whole bus can not be normally used.

The prior art has the following two defects:

less than 1: additional controller intervention is required to achieve master-slave switching.

And less than 2: when the superior controller is not in use, once two hosts always compete for the bus control right, the whole bus is paralyzed and cannot be recovered.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a many host computers of RS485 bus compete switched systems to solve the problem of proposing among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

the RS485 bus multi-host competition switching system comprises an upper computer, a plurality of single-chip controllers and a plurality of slave devices, wherein the upper computer is connected with the single-chip controllers through an RS485 bus, each single-chip controller is connected with the slave devices, and all the slave devices are connected together through RS485 lines.

As a further technical solution of the present invention: the number of the slave devices connected to each single-machine controller is more than or equal to 2.

As a further technical solution of the present invention: the slave devices on each single machine controller are connected in parallel with each other.

As a further technical solution of the present invention: the single-machine controller sets different priorities of the single-machine equipment through the dial switch.

As a further technical solution of the present invention: the upper computer is a computer.

Compared with the prior art, the beneficial effects of the utility model are that: (1) whether a host exists on the bus is confirmed by detecting data on the bus, and accurate judgment can be completed without intervention of an external controller. (2) The parallel single-machine equipment can be ensured to be used as the host machine after being electrified every time, and additional arrangement is not needed.

Drawings

FIG. 1 is a schematic diagram of a stand-alone apparatus.

FIG. 2 is a schematic diagram of a single unit plant used in parallel.

FIG. 3 is a software process flow diagram.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-3, example 1: the RS485 bus multi-host competition switching system comprises an upper computer, a plurality of single-chip controllers and a plurality of slave devices, wherein the upper computer is connected with the single-chip controllers through an RS485 bus, each single-chip controller is connected with the slave devices, and all the slave devices are connected together through RS485 lines.

The number of the slave devices connected to each single-machine controller is more than or equal to 2. The slave devices on each single machine controller are connected in parallel with each other. The single-machine controller sets different priorities of the single-machine equipment through the dial switch. The upper computer is a computer,

the working process is as follows: taking two stand-alone devices connected in parallel as an example, the dial switch is used to set different priorities of the stand-alone devices, then the stand-alone devices determine the time from power-on to communication starting according to the priorities,

the following two cases are distinguished:

1. if RS485_1 and RS485_2 of the two devices are connected together and then powered on, after the single-machine controller is powered on, the RS485_1 and the RS485_2 are initialized to be slave machines, the overtime waiting time is determined according to the priority set by the dial switch, the overtime waiting time with high priority is short, the overtime waiting time with low priority is longer, during the overtime waiting period, if the RS485_2 detects that data flows on the RS485 bus II, the state of the slave machines of the RS485_2 is maintained, if the data on the bus II is not detected in the whole overtime waiting time, the RS485_2 is proved to have no host machine device on the RS485 bus II, and at the moment, the RS485_2 is switched from the slave machine mode to the host machine mode.

2. If the two devices are respectively electrified and then the RS485_1 and the RS485_2 are connected together, the two single-machine devices are respectively electrified, and the RS485 bus I and the RS485 bus II are disconnected, therefore, after the timeout waiting time is exceeded, the two single-machine controllers are switched from the slave mode to the host mode to respectively control the respective RS485 buses II, when the RS485 buses of the two single-machine devices are connected together, the two hosts are arranged on the RS485 bus II, and the two hosts always send commands, and at this time, bus collision inevitably occurs. When the single-machine controller detects that the RS485 bus II has bus collision, the host mode is immediately exited, the slave mode is switched to, a delay waiting mechanism during power-on is executed, the two devices exit the main mode together and enter an overtime waiting state, the waiting time of the device with high priority is short, the device with low priority is firstly switched to the host mode, the device with low priority detects data sent by the device with high priority during the overtime waiting period, and the slave mode is continuously kept.

Therefore, whether the bus is connected first and then powered on or first and then connected, the device with high priority can be ensured to be the master, and the device with low priority is ensured to be the slave. The software processing flow after the two cases are integrated is shown in figure 3.

Embodiment 2 is based on embodiment 1, in the parallel operation state, the single-machine controller needs to query information of the lower slave device, and also needs to query other single-machine controllers in the slave state through the RS485 bus to acquire the state of another single-machine device.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. The RS485 bus multi-host competition switching system comprises an upper computer, a plurality of single-chip controllers and a plurality of slave devices, and is characterized in that the upper computer is connected with the single-chip controllers through an RS485 bus, each single-chip controller is connected with a plurality of slave devices, and all the slave devices are connected together through RS485 lines.

2. The RS485 bus multi-master competition switching system as claimed in claim 1, wherein the number of slave devices connected to each single-master controller is greater than or equal to 2.

3. The RS485 bus multi-master competition switching system of claim 2, wherein the slave devices on each single-master controller are connected in parallel with each other.

4. The RS485 bus multi-host competition switching system of claim 3, wherein the stand-alone controller sets different priorities of stand-alone devices through dial switches.

5. The RS485 bus multi-host competition switching system according to claim 1, wherein the host computer is a computer.