CN115344105A

CN115344105A - Chip with multiplexed interfaces and debugging system of chip

Info

Publication number: CN115344105A
Application number: CN202110529581.8A
Authority: CN
Inventors: 张志仓; 孙永琪; 仲雨
Original assignee: Shanghai Panchip Microelectronics Co ltd
Current assignee: Shanghai Panchip Microelectronics Co ltd
Priority date: 2021-05-14
Filing date: 2021-05-14
Publication date: 2022-11-15
Also published as: WO2022237486A1

Abstract

A chip with multiplexed interfaces and a debugging system of the chip are disclosed, wherein the chip comprises a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module and a universal interface, the universal interface is used for being connected with a debugger, and the instruction receiving unit is connected with the universal interface; the reset signal generating unit is used for generating effective first reset signals and second reset signals, and the release time of the first reset signals is earlier than that of the second reset signals; the instruction receiving unit is used for detecting whether an instruction sent by a debugger is received or not after the first reset signal is released and before the second reset signal is released; when receiving the instruction, the instruction receiving unit controls the interface multiplexing unit to gate the universal interface and the debugging module; when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to gate the universal interface and the functional module. According to the scheme of the invention, an additional multiplexing control pin is not needed, and the flexible multiplexing of the debugging interface and the functional interface is realized.

Description

Chip with multiplexed interfaces and debugging system of chip

Technical Field

The invention relates to the field of chip design, in particular to a chip with multiplexed interfaces and a debugging system of the chip.

Background

Debugging is an essential step for ensuring the correct operation of the program in the chip, and a debugger can download the program through a debugging interface and test and modify the program in the chip. Commonly used debugging interfaces include Joint Test Action Group (JTAG) interface, C2 interface, and the like. Generally, a chip may be reserved with a dedicated pin for programming and debugging, for example, a JTAG interface requires four-pin debugging, a C2 interface requires two-pin debugging, and for a chip with a small total number of pins, the design of the debugging pin causes waste of pin resources. In addition, many mass-produced circuit boards do not retain a debug interface, and the debug interface needs to be connected out through a rewiring when debugging a chip program. In order to save pin resources of the chip and reserve a debugging interface on the circuit board, the debugging interface and the functional interface can be multiplexed. When the debug interface and the functional interface are multiplexed, the debug interface or the functional interface can be selected and used by the multiplexer, however, after the functional interface is selected by the multiplexer, the external debugger cannot control the multiplexer to select the debug interface, which may cause the problem that the debugger cannot be connected with the debug interface and cannot debug.

In order to solve the problem, in the prior art, a method determines whether a signal multiplexing unit selects a functional interface signal or a debug interface signal to select a functional interface or a debug interface by multiplexing a level signal of a control pin and whether a multiplexing control register receives a trigger instruction of a debug mode, wherein the trigger instruction of the debug mode is sent by a user through a key, a toggle switch, a menu selection or the like. However, this approach requires additional multiplexing control pins.

Another method is to multiplex a Serial Interface and a debug Interface, and identify a Serial communication signal as an emulated debug signal when the Serial Interface receives an emulated debug switch instruction in a special instruction format, where the Serial Interface may be a Serial Peripheral Interface (SPI) or an Asynchronous Receiver Transmitter/Transmitter (UART). However, the debugging interface in the method can only be multiplexed with the interface of a specific functional module, and has certain limitation in application.

To sum up, when the debugging interface and the functional interface are multiplexed in the prior art, the following problems exist: (1) extra multiplexing control pins are required; (2) Can only be multiplexed with a specific functional module, and is relatively limited in application.

Disclosure of Invention

The invention solves the technical problem of how to flexibly multiplex a debugging interface and a functional interface on the premise of not additionally arranging a multiplexing control pin.

In order to solve the above problem, an embodiment of the present invention provides an interface multiplexing chip, where the chip includes a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module, and a general interface, where the general interface is used to connect to a debugger, and the instruction receiving unit is connected to the general interface to receive an instruction sent by the debugger; the reset signal generating unit is used for generating a first reset signal and a second reset signal which are valid, the release time of the first reset signal is earlier than that of the second reset signal, and the release refers to the change of the signals from valid to invalid; the instruction receiving unit is used for detecting the first reset signal and the second reset signal and detecting whether an instruction sent by the debugger is received after the first reset signal is released and before the second reset signal is released; the control end of the interface multiplexing unit is respectively connected with the instruction receiving unit and the controller, and the interface multiplexing unit gates the universal interface and the debugging module or the functional module under the control of the instruction receiving unit or the controller; when the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to gate the universal interface and the debugging module; and when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to gate the general interface and the functional module.

Optionally, when controlling the interface multiplexing unit, the priority of the instruction receiving unit is higher than the priority of the controller.

Optionally, the instruction receiving unit is further configured to detect whether a valid first reset signal is received, and the instruction receiving unit resets when detecting that a valid first reset signal is received.

Optionally, the valid second reset signal is used to reset at least one of the other circuit units in the chip except for the instruction receiving unit.

Optionally, when the first reset signal and/or the second reset signal is a low-level signal, it indicates that the first reset signal and/or the second reset signal is valid.

Optionally, the reset signal generating unit is configured to generate an active first reset signal and an active second reset signal after the chip is powered on.

Optionally, after the chip is powered on, the interface multiplexing unit gates the universal interface and the debugging module.

Optionally, the instruction receiving unit is further configured to return a response signal to the debugger after detecting that the instruction is received.

Optionally, the debugging module interface includes a JTAG interface and/or a C2 interface.

The embodiment of the invention also provides a chip debugging system, which comprises the chip with the multiplexed interface and a debugger.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the interface multiplexing chip provided by the invention receives an instruction sent by a debugger during a reset period (specifically, a time interval between the release of a first reset signal and the release of a second reset signal) through an instruction receiving unit, and if the instruction receiving unit does not receive the instruction during the reset period, a controller controls the interface multiplexing unit to select an interface of a debugging module or an interface of a functional module; if the instruction receiving unit receives the instruction during the reset period, the instruction receiving unit controls the interface multiplexing unit to select the interface of the debugging module. The debugger does not send the instruction, or the sent instruction format is incorrect, or the instruction content is not matched, which belongs to the situation that the instruction receiving unit does not receive the instruction, and the instruction receiving unit is not triggered to control the interface multiplexing unit to select the interface of the debugging module. The invention does not limit the functional module and the interface of the functional module, because no matter which functional module interface is selected by the controller control interface multiplexing unit, the interface multiplexing unit can reselect the interface of the debugging module by the way that the debugger sends the instruction during the resetting period until resetting again. That is, when the debugging interface and the functional interface are multiplexed, the debugging module can be used for interface multiplexing with any functional module, and the limitation in the traditional interface multiplexing is broken. In addition, the instruction is received through a universal interface during resetting, an additional multiplexing control pin is not needed, the universal interface can be any available interface of a chip, and the purpose of saving pin resources is achieved.

Drawings

Fig. 1 is a schematic structural diagram of a first interface multiplexing chip according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a reset signal according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating data transmission between a debugger and an instruction receiving unit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a debugging system of a chip according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another debugging system of a chip according to an embodiment of the present invention.

Detailed Description

Those skilled in the art will appreciate that the JTAG interface employs a four-wire serial communication protocol. Four signal lines of the JTAG interface include a Test Mode Selection (TMS) signal, a Test Clock (TCK) Input signal, a Test Data Input (TDI) signal, and a Test Data Output (TDO) signal. The chip with the JTAG interface is internally provided with a Test Access Port (TAP) controller. And the state machine of the TAP controller changes the state through the TCK and the TMS to realize the input of data and instructions. Data is saved in a data register, and instructions are saved in an instruction register.

The C2 interface employs a two-wire serial communication protocol. The communication device of the C2 interface includes an interface master (also called debugger) and an interface slave (also called device to be debugged). The C2 interface protocol includes two lines, which are a Data (Data) line, denoted as C2D and a Clock (Clock) line, denoted as C2CK. The operation of the C2 interface is similar to JTAG, with three JTAG data signals (i.e., TDI, TDO, and TMS) mapped onto one bi-directional C2 data line (C2D), the signal direction of the C2D being tightly controlled by the instruction protocol. The debugger performs online programming and debugging functions through a set of data registers in the C2 interface. The address register defines which data register (similar to the JTAG instruction register) the debugger can access.

As described in the background, when the debugging interfaces (such as the above-mentioned JTAG interface and C2 interface) are multiplexed with the functional interfaces in the prior art, there are the following problems: (1) additional multiplexing control pins are required; (2) Can only be multiplexed with a specific functional module, and is relatively limited in application.

In order to solve the above problem, an embodiment of the present invention provides an interface multiplexing chip, where the chip includes a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module, and a general interface, where the general interface is used to connect to a debugger, and the instruction receiving unit is connected to the general interface to receive an instruction sent by the debugger; the reset signal generating unit is used for generating a first reset signal and a second reset signal which are valid, the release time of the first reset signal is earlier than that of the second reset signal, and the release refers to the change of the signals from valid to invalid; the instruction receiving unit is used for receiving the first reset signal and the second reset signal and detecting whether an instruction sent by the debugger is received or not after the first reset signal is received and before the second reset signal is received; the control end of the interface multiplexing unit is respectively connected with the instruction receiving unit and the controller, and the interface multiplexing unit gates the universal interface and the debugging module or the functional module under the control of the instruction receiving unit or the controller; when the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to gate the universal interface and the debugging module; and when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to gate the general interface and the functional module. Therefore, any functional module interface and a debugging module interface can be multiplexed when the chip is designed, and a control pin does not need to be added, so that the pin resource is saved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first interface multiplexing chip according to an embodiment of the present invention. Specifically, the chip 10 includes a controller 101, a reset signal generating unit 102, an instruction receiving unit 103, an interface multiplexing unit 104, a debugging module 105, a functional module 106, and a general interface 107, where the general interface 107 is used to connect with the debugger 20, and the instruction receiving unit 103 is connected with the general interface 107 to receive an instruction sent by the debugger 20.

The general interface 107 is an interface for multiplexing the debugging module 105 and the functional module 106.

The functional module 106 may be a module for implementing various functions, for example, the functional module 106 may be a Universal Serial Bus (USB) module or a Pulse Width Modulation (PWM) module or any other module. In the present embodiment, the USB module is used for connecting and communicating with a host such as a computer, and the USB module includes two signal lines, i.e., a signal line USB _ DP for transmitting a positive signal of USB data and a signal line USB _ DM for transmitting a negative signal of USB data. The PWM module is used to output square waves with fixed period and adjustable width, and the PWM module has two signal lines of PWM0 and PWM1 in this scheme as an example.

The interface of the debug module 105 includes, but is not limited to, a JTAG interface and/or a C2 interface.

The debugger 20 is a debugging device outside the chip 10, that is, the debugger 20 and the chip 10 are two independent devices, and if the chip needs to be programmed and debugged, the debugger 20 may be connected to the general-purpose interface 107 of the chip 10. The debugger 20 may transmit an instruction to the instruction receiving unit 103 through the general interface 107.

The controller 101 may be various processors or processor cores, such as a Central Processing Unit (CPU) and the like, and may execute corresponding operations by executing instructions, output various appropriate signals, and the like.

The reset signal generation unit 102 is configured to generate a first reset signal and a second reset signal that are active, and a release time of the first reset signal is earlier than a release time of the second reset signal, where the release refers to a transition of a signal from active to inactive. The instruction receiving unit 103 is configured to detect the first reset signal and the second reset signal, and detect whether an instruction issued by the debugger 20 is received after the first reset signal is released and before the second reset signal is released. In other words, the instruction receiving unit 103 detects whether an instruction issued by the debugger 20 is received in a time window defined between the release time of the first reset signal and the release time of the second reset signal. The release time of the first reset signal refers to the time when the first reset signal is changed from active to inactive, and the release time of the second reset signal refers to the time when the second reset signal is changed from active to inactive.

Optionally, referring to fig. 2, fig. 2 is a schematic diagram of a reset signal, when the chip 10 is powered on, the voltage of the power supply port VDD gradually rises to the working voltage, and the reset signal generating unit 102 generates an effective first reset signal (i.e., the reset signal 1 in fig. 2) and an effective second reset signal (i.e., the reset signal 2 in fig. 2), and successively releases the first reset signal and the second reset signal.

The time interval between the release times of the first reset signal and the second reset signal is t. the value of t may be predetermined as required, and it is required to ensure that the command receiving unit 103 can successfully receive the command within the time interval t. During the time interval t, the debugger 20 may send an instruction to the instruction receiving unit 103 to control the general purpose interface 107 and the debugging module 105 to be gated, i.e. a path is formed between the general purpose interface 107 and the debugging module 105.

Optionally, the generation and release timings of the first reset signal and the second reset signal may be other timings besides after the chip 10 is powered on, for example, after the chip 10 detects that the debugger 20 is connected to the universal interface 107, the reset signal generation unit 102 may be controlled to generate the valid first reset signal and the valid second reset signal, and then release the first reset signal and the second reset signal, and the release time of the first reset signal is earlier than the release time of the second reset signal.

Optionally, the instruction receiving unit 103 is further configured to detect whether the first reset signal is valid, and the instruction receiving unit 103 resets when detecting the valid first reset signal. That is, the first reset signal is used to reset the instruction receiving unit 103.

Optionally, the second reset signal that is enabled is used to reset at least one of the other circuit units in the chip 10 except for the instruction receiving unit 103. That is, the second reset signal is used to reset other circuit units in the chip.

Optionally, when the first reset signal and/or the second reset signal is a low-level signal, it indicates that the first reset signal and/or the second reset signal is valid. With continued reference to fig. 2, when the first reset signal/the second reset signal is a low level signal, it indicates that the first reset signal/the second reset signal is active, and when the first reset signal/the second reset signal is changed from a low level signal to a high level signal, it indicates that the first reset signal/the second reset signal is released. It should be noted that the relationship between the high/low level and whether the first reset signal/the second reset signal is active includes, but is not limited to, the definition of fig. 2.

Further, the instruction receiving unit 103 is reset when detecting that the first reset signal is valid, and the other circuit units of the chip 10 are reset when detecting that the second reset signal is valid. Further, the instruction receiving unit 103 does not operate after detecting the release of the second reset signal, that is, does not detect whether an instruction is received.

The control terminal 1041 of the interface multiplexing unit 104 is connected to the instruction receiving unit 103 and the controller 101, respectively, and under the control of the instruction receiving unit 103 or the controller 101, the interface multiplexing unit 104 gates the universal interface 107 and the debugging module 105 or the functional module 106. Gating refers to selecting one of the debug module 105 and the functional module 106 to communicate with the general purpose interface 107. When the instruction receiving unit 103 receives the instruction, the instruction receiving unit 103 controls the interface multiplexing unit 104 to gate the universal interface 107 and the debugging module 105; when the instruction receiving unit 103 does not receive the instruction, the controller 101 controls the interface multiplexing unit 104 to gate the universal interface 107 and the functional module 106. As a non-limiting example, the interface multiplexing unit 104 may include a multiplexer.

The interface multiplexing unit 104 controls which module among the general-purpose interface 107, the debugging module 105, and the functional module 106 is gated, when one module is gated, the general-purpose interface 107 is used as an input/output interface of the gated module, and when the instruction receiving unit 103 does not receive an instruction sent by the debugger 20 within the time interval t, the chip 10 may control which module the interface multiplexing unit 104 is gated with through the controller 101 according to software or other control signals stored in a memory (flash) of the chip. That is, the control signal sources of the control terminal 1041 of the interface multiplexing unit 104 may include two groups: the first set of control signal sources are commands issued by the debugger 20 through the command receiving unit 103, and the second set of control signal sources are signals issued by the controller 101 of the chip 10.

Optionally, the instruction receiving unit 103 and the controller 101 may be connected to the interface multiplexing unit 104 through an arbitration module, where the arbitration module is configured to process the two sets of control signals to determine which set of control signals is selected to control the interface multiplexing unit 104.

Optionally, when controlling the interface multiplexing unit 104, the priority of the instruction receiving unit 103 is higher than the priority of the controller 101. That is, the priority of the first set of control signals is higher than the priority of the second set of control signals. That is, if the first set of control signals and the second set of control signals exist at the same time, the first set of control signals is preferably selected to control the interface multiplexing unit 104.

In one embodiment, the instruction issued by the debugger 20 for controlling the interface multiplexing unit 104 to gate the universal interface 107 and the debug module 105 has a preset information structure, and only when the instruction receiving unit 103 receives an instruction satisfying this information structure, it indicates that the instruction receiving unit 103 receives the instruction. Further, the information structure of the instruction includes: start command + instruction content. After receiving the start command, the instruction receiving unit 103 starts to receive and analyze the instruction content, and if the analysis result is correct, it indicates that the instruction receiving unit 103 receives the instruction.

Optionally, the instruction receiving unit 103 is further configured to return a response signal to the debugger 20 after detecting that the instruction is received; if the instruction receiving unit 103 receives the wrong instruction content, it does not return a response signal. That is, the instruction receiving unit 103 informs the debugger 20 that the general purpose interface 107 and the debugging module 105 have been controlled to be gated through the response signal, and the debugger 20 can debug the chip 10 through the debugging module 105.

Further, referring to fig. 3, fig. 3 is a schematic diagram of data transmission between a debugger and an instruction receiving unit, where an instruction transmitted in a connection path between the debugger and the instruction receiving unit includes "start command + instruction content + response signal". The signal lines of the instruction receiving unit 103 may include a data line and a clock line, and the two lines may be connected to any one signal line of the general interface 107, that is, the general interface 107 includes at least two signal lines.

The instruction receiving unit 103 receives an instruction using at least two signal lines in the universal interface 107 during the period when the first reset signal is released and the second reset signal is not released. During this time, the universal interface 107 is not occupied by any functional module until the second reset signal is released. After the second reset signal is released, the instruction receiving unit 103 no longer receives the instruction and no longer occupies the universal interface 107, which can be used by other functional modules.

A start command (taking a low level of four clock cycles as an example) and instruction contents (taking 0Xa5 as an example) are output to the instruction receiving unit 103 by the debugger 20; the response signal (0X 55 for example) is output to the debugger 20 by the instruction receiving unit 103 after receiving the start command and the instruction content. The signal transmission between the two is transmitted through a data line and a clock line, and for the chip 10, the clock line is an input signal, the data line is an input signal during the transmission of the start command and the instruction content by the debugger 20, and is an output signal during the return of the response signal by the instruction receiving unit 103.

Therefore, the instruction of the invention is sent through the data line and the clock line during the reset period, no additional multiplexing control pin is needed, the data line and the clock line can use any available interface of the chip, and the purpose of saving pin resources is achieved.

In one embodiment, the interface multiplexing unit 104 gates the generic interface 107 with the debug module 105 by default. That is, after the chip 10 is powered on, the interface multiplexing unit 104 gates the universal interface 107 and the debugging module 105.

The chip 10 in fig. 1 receives an instruction sent by the debugger 20 through the instruction receiving unit 103 during a reset period (i.e., a period when the first reset signal and the second reset signal are released), and if the instruction receiving unit 103 does not receive the instruction during the reset period, the controller 101 controls the interface multiplexing unit 104 to select an interface of the debugging module 105 or an interface of the functional module 106; if the instruction receiving unit 103 receives an instruction during reset, the interface multiplexing unit 104 can only select an interface of the debug module 105. The debugger 20 does not send an instruction, or the sent instruction format is incorrect, or the instruction content is not matched, which belongs to the situation that the instruction receiving unit 103 does not receive an instruction, and does not trigger the instruction receiving unit 103 to control the interface multiplexing unit 104 to select the interface of the debug module 105. The present invention does not limit the function module 106 and the interface of the function module 106, because no matter which function module interface is selected by the interface multiplexing unit 104 under the control of the controller 101, the interface multiplexing unit 104 can reselect the interface of the debugging module 105 by sending an instruction from the debugger 20 during the reset period until resetting again. That is, when the debugging interface and the functional interface are multiplexed, the debugging module can be used for interface multiplexing with any functional module, and the limitation in the traditional interface multiplexing is broken.

The embodiment of the present invention further provides a debugging system of a chip, which is characterized in that the debugging system includes a chip 10 and a debugger 20, which are multiplexed by the interface as shown in fig. 1 to fig. 3. The invention is explained in further detail below by means of two embodiments.

Referring to fig. 1 and 4, fig. 4 is a schematic diagram of a specific structure of a debugging system of a chip, in which the functional module 106 includes a USB module 1061 and a PWM module 1062, an interface of the debugging module 105 is a C2 interface (the debugging module 105 may also be referred to as a C2 debugging module), and the general interface 107 includes pins P40 and P41. The USB module 1061 is connected to the interface multiplexing unit 104 through the

signal lines

408 and 409, the PWM module 1062 is connected to the interface multiplexing unit 104 through the

signal lines

406 and 407, the C2 debug module 105 is connected to the interface multiplexing unit 104 through the

signal lines

404 and 405, and the interface multiplexing unit 104 gates one of the USB module 1061, the PWM module 1062, and the C2 debug module 105 and the universal interface 107. The signal line 401 is used for transmitting a first reset signal output by the reset signal generating unit 102; the signal line 402 is used to transmit the second reset signal output by the reset signal generation unit 102. The signal line 403 is used for transmitting a control signal instructing the receiving unit 103 to interface multiplexing unit 104; the signal line 404 is a data line C2D of the C2 debug module 105; the signal line 405 is a clock line C2CK of the C2 debug module 105; the signal line 406 is a signal line PWM0 of the PWM module 1062; the signal line 407 is a signal line PWM1 of the PWM module 1062; the signal line 408 is a signal line USB _ DP of the USB module 1061; the signal line 409 is a signal line USB _ DM of the USB module 1061. The signal line 410 is a clock line of the instruction receiving unit 103, that is, the instruction receiving unit 103 receives a clock signal sent by the debugger 20 through the signal line 410; the signal line 411 is a data line of the instruction receiving unit 103, that is, the instruction receiving unit 103 receives a data signal sent by the debugger 20 through the signal line 411. In this embodiment, the interface multiplexing unit 104 selects the signal line of the C2 debug module 105 by default.

In this embodiment, the debugger first downloads the software program 1 executed by the USB module 1061 into the chip 10, and runs the software program 1. The software program 2 executed by the PWM module 1062 is then downloaded into the chip 10 and the program 2 is run. Program 1 controls the interface multiplexing unit 104 to gate the interfaces of the pins P40 and P41 and the USB module 1061 (i.e., the signal lines 408 and 409) through the controller 101 (not shown in fig. 4). That is, the interface multiplexing unit 104 selects the interface of the USB module 1061 to communicate with the pins P40 and P41, and starts the operation of the USB module. The program 2 controls the interface multiplexing unit 104 through the controller 101 to gate the interfaces of the pins P40 and P41 and the PWM module 1062 (i.e., the signal lines 406 and 407), and start the PWM module to operate.

The embodiment of fig. 4 is used in the following specific manner:

the first use method is as follows: pins P40 and P41 are multiplexed into the interface of USB module 1061. The specific using process comprises the following actions: (1) connecting a debugger to pins P40 and P41 of chip 10; (2) powering on and resetting the chip 10; when downloading for the first time, there is no software program in the chip 10, and the interface multiplexing unit 104 selects the interface of the debugging module 105 by default after the reset is released, so that no instruction needs to be sent during the power-on reset process. (3) After the second reset signal is released, the debugger 20 downloads the program 1 into the chip 10 through the pins P40 and P41. (4) After downloading, disconnecting the debugger 20 from the pins P40, P41; (5) The chip 10 runs the program 1, the controller 101 controls the interface multiplexing unit 104 to select an interface of the USB module 1061, and starts the USB module 1061 to operate.

The second use method is as follows: pins P40 and P41 are multiplexed into the interface of C2 debug module 105. After the program 1 runs, the P40 and P41 are occupied by the USB module 1061, and the debugger 20 cannot be directly connected to the C2 debug module 105 after connecting to the pins P40 and P41. Even if the program 1 is re-run after the power-on reset, there will be a short time for the pins P40 and P41 to interface with the debug module 105 before the program 1 controls the interface multiplexing unit 104 to select the interface of the USB module 1061. If this time is long, debugger 20 will have sufficient time to occupy pins P40 and P41 to begin debugging operations. If the time is short, the debugger 20 cannot start the debugging work. Therefore, the following steps need to be performed to keep debugger 20 busy with pins P40 and P41: (1) connecting debugger 20 to chip pins P40 and P41; and (2) powering on and resetting the chip 10. During a power-on reset (i.e., after the first reset signal is released and before the second reset signal is released), debugger 20 sends an instruction (e.g., 0xa 5) until the debugger receives an acknowledge signal (e.g., 0x 55). After the instruction receiving unit 103 receives 0xa5, the control interface multiplexing unit 104 selects an interface of the debug module. (3) After the power-on reset is completed, since the priority level controlled by the instruction receiving unit 103 to the interface multiplexing unit 104 is greater than the priority level controlled by the controller 101, the pins P40 and P41 are still occupied by the interface of the debug module.

The use method is as follows: pins P40 and P41 are multiplexed into the interface of PWM module 1062. After the second usage mode, the debugger 20 has connected with the debugging module 105 through P40 and P41. The specific using process comprises the following actions: (1) Debugger 20 downloads program 2 into chip 10 through pins P40 and P41. (2) After the downloading is completed, the debugger 20 is disconnected from the pins P40 and P41; (3) The chip 10 runs the program 2, controls the interface multiplexing unit 104 to select an interface of the PWM module 1062, and starts the PWM module 1062 to operate.

Referring to fig. 1 and 5, fig. 5 is a schematic diagram of a specific structure of another chip debugging system, which includes a JTAG debugging module and an SPI module (i.e., the Interface of the JTAG debugging module is a Serial Peripheral Interface (SPI for short)). An instruction receiving unit, an interface of the debugging module 105 is a C2 interface and is a JTAG interface (the debugging module 105 may also be referred to as a JTAG debugging module), the functional module 106 includes an SPI module, the general interface 107 includes multiplexing pins P50, P51, P52, and P53, and the debugger 20 can be connected to at least two pins of the pins P50, P51, P52, and P53 (fig. 5 illustrates the connection to the pins P50 and P51). The SPI is a high-speed full-duplex, synchronous communication bus.

The signal line 501 is used for transmitting a first reset signal output by the reset signal generating unit 102; the signal line 502 is used for transmitting a second reset signal output by the reset signal generation unit 102; the signal line 503 is used for transmitting a control signal instructing the receiving unit 103 to interface multiplexing unit 104. The signal line 504 is a TMS signal line of the JTAG debugging module 105; the signal line 505 is a clock line TCK of the JTAG debug module 105; the signal line 506 is an input signal line TDI of the JTAG debug module 105; the signal line 507 is the output signal line TDO of the JTAG debug module 105. Signal line 508 is a slave enable signal line SSN of SPI module 106; the signal line 509 is a clock signal line SCK of the SPI module 106; the signal line 510 is a signal line MOSI for master device input and slave device data input of the SPI module 106; the signal line 511 is a signal line MISO for master device data input and slave device data output of the SPI module 106; the signal line 512 is a clock line of the instruction receiving unit 103, and the instruction receiving unit 103 receives a clock signal sent by the debugger 20 through the signal line 512; the signal line 513 is a data line of the instruction receiving unit, and the instruction receiving unit 103 receives the clock signal transmitted by the debugger 20 through the signal line 512.

Alternatively, the program in chip 10 has multiplexed pins P50, P51, P52, and P53 into the interface of SPI module 106. A new piece of program needs to be downloaded into the chip 10 and debug work is performed, and the new program does not control the interface multiplexing unit 104. The method comprises the following specific steps:

(1) Connecting debugger 20 to pins P50 and P51; and (2) powering on and resetting the chip 10. During power-on reset, the debugger 20 connects to the instruction receiving unit 103 through P50 and P51, and the debugger 20 sends the instruction 0xa5 until the debugger 20 receives the answer signal 0x55. After the instruction receiving unit 103 receives 0xa5, the control interface multiplexing unit 104 selects an interface of the JTAG debug module 105. After the power-on reset is completed, since the priority level controlled by the instruction receiving unit 103 to the interface multiplexing unit 104 is higher than the priority level controlled by the controller 101, the pins P50, P51, P52, and P53 are still occupied by the interface of the JTAG debug module 105. (3) After the reset is released, the debugger 20 connects to the interface of the JTAG debug module 105 through pins P50, P51, P52, and P53, and downloads a new program into the chip 10; (4) After the new program is downloaded, the debugger 20 sends a debug instruction to the JTAG debug module 105 to perform the debugging operation.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.

The "plurality" appearing in the embodiments of the present application means two or more.

The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for the purpose of illustrating and differentiating the description objects, and do not represent any particular limitation to the number of devices in the embodiments of the present application, and cannot constitute any limitation to the embodiments of the present application.

The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application. The arrows of the signal lines in the respective drawings may indicate the flow of the signals.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. The chip for multiplexing the interfaces is characterized by comprising a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module and a universal interface, wherein the universal interface is used for being connected with a debugger;

the reset signal generating unit is used for generating a first reset signal and a second reset signal which are valid, the release time of the first reset signal is earlier than that of the second reset signal, and the release refers to the change of the signals from valid to invalid;

the instruction receiving unit is used for detecting the first reset signal and the second reset signal and detecting whether an instruction sent by the debugger is received or not after the first reset signal is released and before the second reset signal is released;

the control end of the interface multiplexing unit is respectively connected with the instruction receiving unit and the controller, and the interface multiplexing unit gates the universal interface and the debugging module or the functional module under the control of the instruction receiving unit or the controller;

when the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to gate the universal interface and the debugging module;

and when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to gate the general interface and the functional module.

2. The chip according to claim 1, wherein the priority of the instruction receiving unit is higher than the priority of the controller in controlling the interface multiplexing unit.

3. The chip of claim 1, wherein the instruction receiving unit is further configured to detect whether a valid first reset signal is received, and wherein the instruction receiving unit is reset upon detecting receipt of a valid first reset signal.

4. The chip according to claim 3, wherein the second reset signal that is active is used to reset at least one of the other circuit units in the chip except the instruction receiving unit.

5. The chip of claim 1, wherein the first reset signal and/or the second reset signal is a low level signal indicating that the first reset signal and/or the second reset signal is valid.

6. The chip according to any one of claims 1 to 5, wherein the reset signal generation unit is configured to generate the first reset signal and the second reset signal that are active after the chip is powered on.

7. The chip according to any one of claims 1 to 5, wherein after the chip is powered on, the interface multiplexing unit gates the universal interface and the debugging module.

8. The chip of claim 1, wherein the instruction receiving unit is further configured to return an acknowledgement signal to the debugger after detecting receipt of the instruction.

9. The chip of claim 1, wherein the debug module interface comprises a JTAG interface and/or a C2 interface.

10. A debugging system of a chip, characterized in that the debugging system comprises a chip with an interface multiplex according to any one of claims 1 to 9, and a debugger.