CN101169774B - Multiprocessor system, sharing control device and method for starting slave processor - Google Patents
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Abstract
The invention discloses a multiprocessor sharing control device, a multiprocessor system adopting the device and a method for starting a slave processor. The device comprises a sharing control module and at least one sharing device, wherein the sharing control module is used for controlling addresses, data and other buses and controlling the starting slave processor, and the sharing device is used for storing programs and data required by the starting slave processor. The system comprises a main system, at least one slave system and at least one multiprocessor sharing control device, wherein the slave system is connected with the main system through the multiprocessor sharing control device and is also connected through a master-slave communication interface. The invention realizes the purpose that the main processor and the plurality of auxiliary processors share equipment to the maximum extent by sharing the control device, repeatedly utilizes hardware resources, reduces the complexity of hardware design, simplifies the starting flow of the auxiliary processors and simplifies the difficulty of controlling the system software design.
Description
Technical Field
The invention belongs to the technical field of embedded systems, and particularly relates to a shared control device for a multiprocessor system, a processor system comprising the device, and a slave processor starting method based on the device.
Background
With the continuous development of embedded systems, the functional integration level of a single processor is higher and higher, but it is still difficult for a single embedded processor to meet the requirements of system control, service management, data processing and the like. As a result, more and more designers are beginning to employ multiple processors for decentralized management of control, traffic, and functions. Currently, the most common approach is to use two processors, one biased towards control management and the other biased towards business processing. Of course, there are also cases where more processors are used to meet different demands.
The increase in the number of processors makes the system architecture clearer, but at the same time brings new problems. With the increase of the number of processors in the system, the number of peripheral devices required by the minimum system is increased, the cost of a hardware circuit is increased, and the complexity of hardware design is increased; meanwhile, the starting process of the system is very complex due to the cooperative relationship among the processors, so that the difficulty of system control is greatly increased, and the complexity of software design is indirectly improved.
In the prior art, a designer isolates the minimum system of each processor, each processor has an independent ROM (Read Only Memory) and RAM (Random-Access Memory), and then interconnects a plurality of systems through serial, parallel or more complex communication interfaces, so as to greatly increase the complexity of hardware design and software design along with the increase of the number of processors in the system, which cannot effectively utilize hardware resources and cannot optimize software flow.
On the basis of ensuring the system function integrity and the system structure layering, if more peripheral devices can be shared, the control method of the processor can be simplified, so that hardware resources are repeatedly utilized, the complexity of a hardware design scheme can be greatly reduced, the flow of system control can be greatly simplified, and the complexity of software design can be reduced.
Disclosure of Invention
The invention aims to overcome the defects that the hardware resources of the existing multiprocessor system cannot be effectively shared, the control method is complex and the like, and provides a multiprocessor sharing control device. Meanwhile, the invention also provides a multiprocessor system adopting the device and a starting method of the slave processor.
In order to solve the technical problems, the multiprocessor sharing control device provided by the invention comprises a sharing control module and at least one sharing device. The shared control module is connected with the configuration of the main processor, realizes that programs and data required by the starting of the auxiliary processor are written into the shared equipment, and switches addresses, data and other buses required by the shared equipment onto the auxiliary processor, and then starts the auxiliary processor; the shared device is used to store a number of programs and data needed to boot the slave processor, and may be a ROM, RAM or other storage device.
The sharing control module is connected with the sharing device through an address, a data bus and a control signal, and is connected with the master processor and the slave processor through the address, the data bus and the control signal.
The multiprocessor system comprises a master system, a plurality of slave systems and at least one multiprocessor sharing control device. The main system comprises a main processor, a ROM, a RAM, a master-slave communication interface and an external communication interface, wherein the ROM is used for storing programs and data required by the starting of the main processor, the main processor is connected with the ROM, the RAM, the master-slave communication interface and the external communication interface through address, data buses and control signals, and the external communication interface can be connected with other devices to serve as an auxiliary source for starting the programs and the data of the slave processor. The slave system comprises a slave processor, a RAM and a master-slave communication interface, wherein the slave processor is connected with the RAM, the master-slave communication interface and the multiprocessor sharing control device through an address, a data bus and a control signal.
The master-slave communication interface of the slave system is connected with the master-slave communication interface of the master system; the master-slave communication interface is not limited to a particular serial or parallel communication interface.
The multiprocessor sharing control device comprises a sharing control module and at least one sharing device. The shared control module is connected with the configuration of the main processor, and realizes the control of addresses, data and other buses and the control of starting the auxiliary processor; the sharing device is used for storing programs and data required for starting the slave processor, and can be ROM, RAM or other storage devices; the sharing control module is respectively connected with the sharing device, the master processor and the slave processor through address, data buses and control signals.
Under the condition that a plurality of slave systems are symmetrical, the multiprocessor system only needs one multiprocessor sharing control device, and after the master system starts a selected slave system according to a certain sequence, the next slave system can be started according to the same steps, and the processes are sequentially carried out until all the slave systems are started. By "symmetric slave system" is meant any slave system that the master system carries along with it is the same as the other slave systems. Since each slave system is identical, the start-up sequence may be arbitrary.
Under the asymmetric condition of a plurality of slave systems, the multiprocessor system can be additionally provided with one or a plurality of multiprocessor sharing control devices according to the requirement, and hardware resources are utilized to the maximum extent under the condition of ensuring the functional integrity of the system. Multiple multiprocessor shared control devices may be distinguished by address, data bus, other bus, or specific signals. By "asymmetric slave systems" it is meant that the slave systems carried by the master system are not all the same, but there are different slave systems.
The invention provides a method for starting a slave processor in a multiprocessor system, which comprises a master system, a slave system and a multiprocessor sharing control device, wherein a sharing device in the multiprocessor sharing control device is a ROM, a RAM or other storage devices, and the method comprises the following steps:
firstly, after the main processor is started, a program and data required by the starting of the slave processor are written into the sharing equipment through the sharing control module;
the second step, the main processor gives up the address, data and other buses required for accessing the shared device;
thirdly, the master processor switches the address, data and other buses required by the shared equipment to the slave processor through the configuration of the shared control module, and then starts the slave processor;
fourthly, after the slave processor is started, a communication link is established with the master processor through a master-slave communication interface;
and fifthly, the main processor performs final configuration on the multiprocessor sharing control device according to the requirement so as to set final attribution right of the sharing equipment.
Wherein the first step further comprises the steps of:
(a) The main processor configures the sharing control module to obtain the control right of the sharing equipment;
(b) The sharing control module processes the address, the data and the control signal according to the configuration, gives access control rights of the sharing equipment to the main processor, and receives the control of the access control rights;
(c) The method comprises the steps that a master processor obtains information of programs and data required by starting a slave processor stored in a sharing device; if the required program or data is incomplete when the slave processor starts, the required program or data is acquired from an external communication interface of the main system and stored in the sharing device.
The present invention also proposes a method of starting up a slave processor in a multiprocessor system, the multiprocessor system comprising a master system, a plurality of slave systems, and when the slave systems are symmetrical, the multiprocessor system further comprising a multiprocessor shared control apparatus, the shared device in the multiprocessor shared control apparatus being one or more ROM, RAM or other storage devices, or when the slave systems are asymmetrical, the multiprocessor system further comprising two or more multiprocessor shared control apparatuses, the shared device in the multiprocessor shared control apparatus being one or more ROM, RAM or other storage devices; the method comprises the following steps:
firstly, after the main processor is started, writing programs and data required by the starting of the auxiliary processor into selected sharing equipment through a sharing control module;
the second step, the main processor gives up the address, data and other buses required for accessing the selected shared device;
thirdly, the master processor switches the address, data and other buses required by the selected shared device to the selected slave processor through the configuration shared control module, and then starts the selected slave processor;
fourthly, after the selected slave processor is started, a communication link is established with the master processor through a master-slave communication interface;
fifthly, the master processor prepares to start other slave processors according to a set sequence;
sixthly, repeating the second step to the fifth step until all slave processors are started;
and seventhly, the main processor carries out final configuration on the multiprocessor sharing control device according to the requirement so as to set the final attribution right of the sharing equipment and ensure the normal operation of the system.
Wherein the first step further comprises the steps of:
(a) The main processor configures the corresponding sharing control module to obtain the control right of the selected sharing equipment;
(b) The sharing control module processes the address, the data and the control signal according to the configuration, gives the access control right of the selected sharing equipment to the main processor, and receives the control of the main processor;
(c) The master processor obtains the information of programs and data which are stored in the selected shared equipment and are required by the starting of the slave processor; if the slave processor starts the required program or data incompleteness, the required program or data is obtained from the external communication interface of the host system and stored in the selected sharing device.
The sharing control module can control multiple paths of addresses, data and other buses, and is connected with one or more sharing devices through the addresses, the data and the other buses; while the master processor may configure the shared control module to enable control of addresses, data, and other buses and control of the slave processor's start-up.
The sharing device in the multiprocessor sharing control device can be used by a plurality of slave systems, so that the slave systems can be provided with no ROM device, the hardware resources are repeatedly utilized, the number and the cost of components are reduced, and the complexity of hardware design is reduced. Meanwhile, the main processor can control the state of the slave processor through the shared control module, so that the starting control flow of the slave system is greatly simplified, and the design difficulty of system control software is reduced. All programs and data required by the starting of the slave system are stored into the sharing equipment by the master system through the sharing control module, and are not transmitted through a master-slave communication interface between the master processor and the slave processor, so that the software development difficulty of the slave system is reduced. Meanwhile, all programs and data required by the starting of the slave system and the starting flow of the slave system are controlled by the master system, so that the reuse rate of the code of the master system can be greatly increased, and the software development difficulty of the master system is also reduced.
Drawings
FIG. 1 is a schematic diagram of a hardware implementation of a multiprocessor system of the present invention;
FIG. 2 is a slave boot flow chart in accordance with the present invention;
FIG. 3 is a schematic diagram of a multiprocessor system of the present invention that is symmetrical from the system;
FIG. 4 is a schematic diagram of a multiprocessor system of the present invention that is asymmetric from the system.
Detailed Description
The multiprocessor system of the present invention and the specific implementation of the slave processor boot method are described in further detail below with reference to an engineering example and accompanying drawings.
FIG. 1 is a schematic diagram of a multiprocessor system implemented in accordance with the present invention. As shown in fig. 1, the multiprocessor system includes a master system 100, a slave system 200, and a multiprocessor sharing control device 300, and although only one master system 100 and slave system 200 are provided in the present embodiment, more slave systems 200 may exist in the multiprocessor system of the present invention.
The host system 100 includes a processor CPU110, a ROM120, a RAM 130, a master-slave communication interface 140, and an external communication interface 150. The CPU110 is connected to the ROM120, RAM 130, master-slave communication interface 140, and external communication interface 150 through address, data buses, and control signals. The ROM120 is used only to store programs and data necessary for the start-up of the master system 100, and does not contain the start-up program and data of the slave system 200. External communication interface 150 may connect other devices as a source of slave system start-up programs and data.
The slave system 200 includes a processor CPU210, RAM 230, and a master-slave communication interface 240. The CPU210 is connected to the RAM 230 and the master-slave communication interface 240 through address, data buses and control signals. The master-slave communication interface 240 of the slave system 200 is also connected to the master-slave communication interface 140 in the master system 100, and the master-slave communication interface 240 of the slave system 200 and the master-slave communication interface 140 of the master system 100 are not limited to a specific serial or parallel communication interface.
The multiprocessor shared control apparatus 300 includes a shared control module 310 and a ROM320, and the shared control module 310 is connected to the ROM320, the CPU110 of the master system 100, and the CPU210 of the slave system 200 via an address, a data bus, and a control signal, respectively.
In the present embodiment, the sharing device of the multiprocessor sharing control apparatus 300 only includes the ROM320, but the sharing device of the multiprocessor sharing control apparatus of the present invention is not limited to the ROM device, and other sharing devices such as a RAM, an SRAM, or an ethernet controller may be used, and these sharing devices are all connected to the sharing control module 310.
The main flow of the method for starting up the slave processor in this embodiment will be further described with reference to the flow chart shown in fig. 2 on the basis of the apparatus of the present invention.
The flow chart is preceded by the master system 100 having been started and the slave system 200 has been in a reset state. Next, the start-up procedure of the slave system 200 includes the steps of:
step S110, the CPU110 of the host system 100 configures the shared control module 310 to obtain the control right of the ROM320, where the configuration mainly refers to setting the logic of the shared control module 310, including setting a register, or setting the logic state of a specific pin, etc.;
step S120, the shared control module 310 processes the address, data and control signal according to the configuration, and gives the access control right of the ROM320 to the CPU110 of the main system 100 to receive the control thereof, where the process includes switching the address, data and control signal to the main system 100, if there is a clock signal in the control signal to eliminate the jitter occurring in the clock switching, so that the main system 100 can access the ROM320 sharing device in the multiprocessor shared control apparatus 300;
step S130, the CPU110 of the master system 100 obtains the information of the programs and data necessary for the start-up of the slave system 200 stored in the ROM 320; if the required program or data is not complete for the start-up from the system 200, the required program or data is acquired from the external communication interface 150 of the main system 100 and stored in the ROM 320;
step S140, the ROM320 has already stored information of programs and data required for starting from the system 200 at this time;
step S150, the CPU110 of the master system configures the shared control module 310 to relinquish control of the ROM320 and to communicate with the slave system 200;
step S160, the shared control module 310 processes the address, data and control signals according to the configuration, and receives control from the CPU210 of the system 200;
step S170, the CPU110 of the master system 100 configures the shared control module 310 to start the CPU210 of the slave system 200;
step S180, the shared control module 310 processes the address, data and control signals according to the configuration, and starts the CPU210 of the slave system 200;
step S190, the slave system 200 is started up by the CPU210, the starting program and data are read from the ROM320, and after initialization, a link establishment request is sent to the CPU110 of the master system 100 through the master-slave communication interface 240;
in step S200, the master-slave communication interface 140 of the master system 100 responds to the link establishment request received from the CPU210 of the slave system to establish a communication connection.
As described above, the slave system 200 does not include the ROM but is provided in the multiprocessor shared control apparatus 300, and the ROM320 in the multiprocessor shared control apparatus 300 is also available for other slave systems 200, thereby reducing the number of components and the cost. Meanwhile, the master system 100 can control the state of the CPU210 in the slave system 200 through the shared control module, so that the starting control flow of the slave system 200 is greatly simplified, and the design difficulty of system control software is reduced.
All programs and data required for the start-up of the slave system 200 are stored in the ROM320 by the master system 100 through the shared control module, rather than being transferred between the master-slave communication interface 140 and the master-slave communication interface 240, reducing the difficulty of software development of the slave system 200. Meanwhile, all programs and data required by the starting of the slave system 200 and the starting flow of the slave system 200 are controlled by the master system 100, so that the reuse rate of the code of the master system can be greatly increased, and the software development difficulty of the master system is also reduced.
In the above embodiment, only one slave system exists, but the multiprocessor system of the present invention may further include a plurality of slave systems:
FIG. 3 is a schematic diagram of a multiprocessor system of the present invention that is symmetrical from the system. As shown, the master system 100 has a first slave system 2001 and a second slave system 2002 or even more slave systems, and each slave system has the same structure. In this case, the multiprocessor system may employ only one multiprocessor shared control apparatus 300, and the master system 100 is connected to each slave system via the multiprocessor shared control apparatus 300, and is also connected via a master-slave communication interface. The shared devices in the multiprocessor shared control apparatus 300 may be one or more, as required, and may be of the ROM, RAM or other storage device type. After the master system 100 starts the selected slave system according to the foregoing steps, the next slave system may be started according to the same steps, and the process may be sequentially performed until all the slave systems are started.
FIG. 4 is a schematic diagram of a multiprocessor system of the present invention that is asymmetric from the system. As shown, the master system 100 is provided with a first slave system 2001, a second slave system 2002, an nth slave system 200n, an mth slave system 200m and more slave systems, wherein the first slave system 2001 and the second slave system 2002 have the same structure and form a class of slave systems; the nth slave system 200n and the mth slave system 200m have the same structure and form another class of slave systems. However, these two types of slave systems are not identical in structure, and thus constitute a multiprocessor system in which the slave systems are asymmetric. In this case, two multiprocessor sharing control devices, the first multiprocessor sharing control device 3001 and the second multiprocessor sharing control device 3002, respectively, may be provided for the multiprocessor system so as to share hardware resources to the maximum extent while ensuring the functional integrity of the system. Such a slave system including a first slave system 2001 and a second slave system 2002 is connected to the master system 100 through a first multiprocessor shared control device 3001, and is also connected through a master-slave communication interface. All programs and data required for starting the class of slave systems are stored in the shared device of the first multiprocessor shared control apparatus 3001, which may be one or more as needed, and may be of the ROM, RAM or other storage device type; such slave systems, including the nth slave system 200n and the mth slave system 200m, are connected to the master system 100 through the second multiprocessor shared control apparatus 3002, and are also connected through the master-slave communication interface. All programs and data necessary for starting the class of slave systems are stored in the shared device of the second multiprocessor shared control apparatus 3002, which may be one or more, as required, of the type ROM, RAM or other storage device. After the master system 100 is started, the corresponding slave system is started through the first multiprocessor sharing control device 3001 and the second multiprocessor sharing control device 3002, respectively, according to the foregoing steps. If one slave system depends on the starting of the other slave system, the corresponding sequence requirement should be complied in the starting process, and the starting can be started from the slave system with the least dependence at present; i.e. starting from the slave processor that is least dependent on currently.
In the multiprocessor system described above, the first multiprocessor shared control device 3001 and the second multiprocessor shared control device 3002 may be distinguished by addresses, data buses, other buses, or specific signals. For example, two multiprocessor shared control devices may be mapped into different address spaces by address mapping. Once the multi-processor sharing control device is distinguished, each slave system sharing the sharing device can be distinguished naturally, and corresponding processing is further completed.
It is apparent that the present invention is not limited to the above-described embodiments, and modifications and variations may be made according to actual needs without departing from the scope and gist of the present invention.
Claims (9)
1. A multiprocessor sharing control device is characterized by comprising a sharing control module and at least one sharing device;
the sharing control module is connected with the master processor and the slave processor through an address, a data bus and a control signal, receives the configuration of the master processor, realizes that programs and data required by the starting of the slave processor are written into the sharing equipment, switches the address, the data and other buses required by the sharing equipment onto the slave processor, and then starts the slave processor;
the sharing device is used for storing programs and data required by starting the plurality of slave processors and is connected with the sharing control module through an address, a data bus and control signals.
2. A multiprocessor system comprising the apparatus of claim 1, comprising a master system, a plurality of slave systems, and at least one of said multiprocessor shared control means;
the main system comprises a main processor, a read-only memory ROM, a random access memory RAM, a master-slave communication interface and an external communication interface, wherein the ROM is used for storing programs and data required by the starting of the main processor, the main processor is connected with the ROM, the RAM, the master-slave communication interface and the external communication interface through address, data buses and control signals, and the external communication interface is connected with other devices to serve as an auxiliary source for starting the programs and the data of the slave processor;
the slave system comprises a slave processor, a RAM and a master-slave communication interface, wherein the slave processor is connected with the RAM of the slave system, the master-slave communication interface of the slave system and the multiprocessor sharing control device through an address, a data bus and control signals, and the master-slave communication interface of the slave system is connected with the master-slave communication interface of the master system.
3. The multiprocessor system of claim 2, wherein said slave system has only one; only one multiprocessor sharing control device is provided;
the shared device in the multiprocessor shared control apparatus is a ROM, RAM or other storage device.
4. The multiprocessor system of claim 2, wherein the slave system is a plurality of slave systems that are symmetrical; only one multiprocessor sharing control device is provided;
the shared devices in the multiprocessor shared control apparatus are one or more of the types of ROM, RAM or other storage devices.
5. The multiprocessor system of claim 2, wherein the slave system is a plurality of non-symmetrical slave systems; the multiprocessor sharing control device is two or more;
the shared devices in the multiprocessor shared control apparatus are one or more of the types of ROM, RAM or other storage devices.
6. A method of starting up a slave processor in a multiprocessor system as claimed in claim 3, comprising the steps of:
firstly, after the main processor is started, a program and data required by the starting of the slave processor are written into the sharing equipment through the sharing control module;
the second step, the main processor gives up the address, data and other buses required for accessing the shared device;
thirdly, the master processor switches the address, data and other buses required by the shared equipment to the slave processor through the configuration of the shared control module, and then starts the slave processor;
fourthly, after the slave processor is started, a communication link is established with the master processor through a master-slave communication interface;
and fifthly, the main processor performs final configuration on the multiprocessor sharing control device according to the requirement so as to set final attribution right of the sharing equipment.
7. The method of starting up a slave processor of claim 6, wherein the first step further comprises the steps of:
(a) The main processor configures the sharing control module to obtain the control right of the sharing equipment;
(b) The sharing control module processes the address, the data and the control signal according to the configuration, gives access control rights of the sharing equipment to the main processor, and receives the control of the access control rights;
(c) The method comprises the steps that a master processor obtains information of programs and data required by starting a slave processor stored in a sharing device; if the required program or data is incomplete when the slave processor starts, the required program or data is acquired from an external communication interface of the main system and stored in the sharing device.
8. A method of starting up a slave processor in a multiprocessor system as claimed in claim 4 or 5, comprising the steps of:
firstly, after the main processor is started, writing programs and data required by the starting of the auxiliary processor into selected sharing equipment through a sharing control module;
the second step, the main processor gives up the address, data and other buses required for accessing the selected shared device;
thirdly, the master processor switches the address, data and other buses required by the selected shared device to the selected slave processor through the configuration shared control module, and then starts the selected slave processor;
fourthly, after the selected slave processor is started, a communication link is established with the master processor through a master-slave communication interface;
fifthly, the master processor prepares to start other slave processors according to a set sequence;
sixthly, repeating the second step to the fifth step until all slave processors are started;
and seventhly, the main processor carries out final configuration on the multiprocessor sharing control device according to the requirement so as to set the final attribution right of the sharing equipment.
9. The method of starting up a slave processor of claim 8, wherein the first step further comprises the steps of:
(a) The main processor configures the corresponding sharing control module to obtain the control right of the selected sharing equipment;
(b) The sharing control module processes the address, the data and the control signal according to the configuration, gives the access control right of the selected sharing equipment to the main processor, and receives the control of the main processor;
(c) The master processor obtains the information of programs and data which are stored in the selected shared equipment and are required by the starting of the slave processor; if the slave processor starts the required program or data incompleteness, the required program or data is obtained from the external communication interface of the host system and stored in the selected sharing device.
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| JP2017188072A (en) * | 2016-04-05 | 2017-10-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device and access management method |
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| CN107807615A (en) * | 2017-10-26 | 2018-03-16 | 东莞市乔锋机械有限公司 | A kind of machining center complex control system |
| CN111381882B (en) * | 2018-12-28 | 2022-12-02 | 上海寒武纪信息科技有限公司 | Data processing device and related product |
| CN112328315B (en) * | 2021-01-04 | 2021-08-31 | 江苏华创微系统有限公司 | Storage sharing type multi-chip processor system based on bridge chip and starting method thereof |
| CN113778538A (en) * | 2021-09-13 | 2021-12-10 | 讯牧信息科技(上海)有限公司 | Multiprocessor system and starting method thereof |
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