JP2008210183A - Redundant control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a redundant control system that shortens the time for controllers to start a redundant operation. <P>SOLUTION: The redundant control system implements a redundant operation of a plurality of controllers. Each controller is connected by first and second redundant inter-card communication buses, and has a processor for executing control operations and access to the other controllers, a high order memory and a low order memory for storing high order bit data and low order bit data of data, respectively, a memory access controller connected to the high order memory and low order memory by a high order memory bus and a low order memory bus respectively to control access, a bus selector for selecting inter-card communication buses for use from the first and second inter-card communication buses, and first and second inter-card communication bus controllers for controlling access to the first and second inter-card communication buses, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a redundant control system that redundantly operates a plurality of controllers in order to improve reliability, and more particularly to a redundant control system that improves an equalization process between redundant controllers.

  Communication between redundant controllers is carried out via inter-card communication buses that are further duplicated. If communication via one bus is abnormal, switching to the other bus increases communication reliability. It has a configuration.

FIG. 3 is a diagram for explaining the operation of the conventional redundant control system.
The redundant control system is made redundant by the controllers 1a and 1b, and is further connected by the duplexed first and second inter-card communication buses 2 and 3, and accesses each other to equalize data. Synchronize processing. The redundant controllers 1a and 1b always execute the same processing, and even when one controller stops due to a failure or the like, the processing can be continued by switching to the other controller instantaneously. .

Each controller 1a, 1b comprises processors 10a, 10b, interface controllers 20a, 20b, main memories 40a, 40b, and inter-card communication bus controllers 31a, 31b, 32a, 32b.
The processors 10a and 10b execute control calculation and access with each controller.

The interface controllers 20a and 20b include bus selectors 21a and 21b and memory access controllers 22a and 22b.
The bus selectors 21a and 21b select whether to communicate with other controllers using the first inter-card communication bus 2 or to communicate with other controllers using the second inter-card communication bus 3.
The memory access controllers 22a and 22b arbitrate the access right to the main memories 40a and 40b for the access from the first and second inter-card communication buses 2 and 3, and execute the access.

The first inter-card communication bus controllers 31a and 31b control access to the first inter-card communication bus, and the second inter-card communication bus controllers 32a and 32b control access to the second inter-card communication bus. To do.
The main memories 40a and 40b are composed of three memory units, upper bit data 41a and 41b, lower bit data 42a and 42b, and check bit 43a and 43b.

When the controller 1b is added while the controller 1a is operating, in order to realize a redundant operation as a redundant control system, the contents of the main memory 40b of the controller 1b are changed to the controller 1a before the controller 1b is activated. The contents of the main memory 40a must be the same. Therefore, the data in the main memory 40a of the controller 1a is copied (equalization process) to the main memory 40b of the controller 1b.
In order to perform the copy operation, the controller 1a performs a data read access (A) from the main memory 40a and performs a write access (B) to the main memory 40b of the controller 1b.

  In the write access (B), the bus selector 21a that receives the request from the processor 10a selects which of the first and second inter-card communication buses 2 and 3 is used. When the bus selector 21a selects to use the first inter-card communication bus 2, an access request is made to the first inter-card communication bus controller 31a. The first inter-card communication bus controller 31a starts access after acquiring the bus right of the first inter-card communication bus 2. After acquiring the memory access right of the main memory 40b by the memory access controller 22b via the first inter-card communication bus controller 31b of the controller 1b, the main memory 40b is written.

  By repeating this operation to make the contents of the main memory 40b of the controller 1b the same as the contents of the main memory 40a of the controller 1a, the operation of the controller 1b is started, whereby the controllers 1a and 1b can be made redundant.

  During the redundancy operation, the controllers 1a and 1b have duplexed access (B) and (b) for synchronization processing of the redundancy operation in addition to the accesses (A) and (a) to the main memories 40a and 40b. The first and second inter-card communication buses 2 and 3 are used periodically. When one side of the first and second inter-card communication buses 2 and 3 fails, the synchronization process is continued by using the other bus while sharing the other.

JP 2001-256070 A

  When the controller is redundant, the memory copy operation to another controller is performed using only one of the duplex inter-card communication buses, and the speed of the access itself is small because the bandwidth of the inter-card communication bus is small. However, there is a problem that it takes a long time to complete the copying operation of the large-capacity memory, and the start of the redundancy operation is delayed.

  The present invention has been made in order to solve the above-described problems, and performs a memory copy operation to another controller at a high speed, thereby reducing the time until the controller can start the redundancy operation. The purpose is to realize a control system.

In order to achieve such a subject, the present invention is configured as follows.
(1) In a redundant control system that redundantly operates a plurality of controllers,
Each controller is connected by a duplexed first and second inter-card communication bus,
A processor that executes control computation and access to each controller;
An upper memory for storing upper bit data and a lower memory for storing lower bit data,
A memory access controller connected to the upper memory and the lower memory by an upper memory bus and a lower memory bus, respectively, for controlling access;
A bus selector for selecting an inter-card communication bus to be used from among the first and second inter-card communication buses;
First and second inter-card communication bus controllers that respectively control access to the first and second inter-card communication buses;
A redundant control system comprising:

(2) The bus selector issues an access request to one of the first and second inter-card communication bus controllers at the time of normal access between the controllers, and the first and second at the time of high speed access. The redundancy control system according to (1), wherein an access request is issued to both inter-card communication bus controllers, and one is used for upper bit data and the other is used for lower bit data.

(3) The redundancy control system according to (2), wherein the high-speed access is an equalization process for making the contents of the memory the same among the controllers.

(4) Each of the upper memory and the lower memory includes an upper check bit memory and a lower check bit memory, respectively, and diagnoses the upper bit data and the lower bit data separately. The redundant control system according to the above.

The present invention has the following effects.
By using both duplexed inter-card communication buses only during the copying operation for the redundant operation of the controller, it is possible to shorten the time until the controller can start the redundant operation.

Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention. The same parts as those in the previous figure are given the same reference numerals, and the description of the same parts as those in the prior art is omitted.
The redundancy control system is made redundant by the controllers 100a and 100b, and is connected by the inter-card communication buses 2 and 3 that are further duplicated, and can access each other to perform data equalization, process synchronization, and the like. Do. The redundant controllers 100a and 100b always execute the same process, and even when one controller stops due to a failure or the like, the process can be continued by switching to the other controller instantaneously. .

The memories of the controllers 100a and 100b are divided into upper memories 50a and 50b and lower memories 60a and 60b, and upper memory buses 250a and 250b and lower memory buses 260a and 260b so that they can be independently accessed. Separate buses are available.
The upper memories 50a and 50b are composed of upper bit data memories 51a and 51b and check bit memories 52a and 52b. The lower memories 60a and 60b are composed of lower bit data memories 61a and 61b and check bit memories 62a and 62b.

  Thus, the upper bit data and the lower bit data are stored separately. Each check bit is also stored separately, and whether or not data transmission / reception is performed correctly is also diagnosed for each upper bit and lower bit.

  When the controller 100b is added while the controller 100a is operating, in order to realize a redundant operation as a redundant control system, before the controller 100b is activated, the upper memory 50b and the lower memory 60b of the controller 100b The contents must be the same as the contents of the upper memory 50a and the lower memory 60a of the controller 100a. For this reason, it is necessary to copy the data of the upper memory 50a and the lower memory 60a of the controller 100a to the upper memory 50b and the lower memory 60b of the controller 100b.

  For the write access (C) issued by the processor 10a, the bus selector 210a, if both the first and second inter-card communication buses 2 and 3 are normal, the first and second inter-card communication bus controllers. An access request is made to both 31a and 32a. At this time, the bus selector 210a passes only the lower bit (or upper bit) of the write data to the first inter-card communication bus controller 31a, and the upper bit of the write data to the second inter-card communication bus controller 32a. A write request is made by passing only bits (or lower bits).

  The first inter-card communication bus controller 31a acquires the bus right of the first inter-card communication bus 2, and then performs write access to the memory access controller 220b via the first inter-card communication bus controller 31b of the controller 100b. Make a request (D1). The memory accelerator controller 220b does not perform the arbitration between the first and second inter-card communication bus controllers 31b and 32b that is normally performed, and performs the write access only to the lower memory 60b (or the upper memory 50b) as it is (E1). ).

  Similarly, the second inter-card communication bus controller 32a acquires the bus right of the second inter-card communication bus 3, and then the memory access controller 220b via the second inter-card communication bus controller 32b of the controller 100b. A write access request is made (D2). The memory access controller 220b does not perform arbitration between the first and second inter-card communication bus controllers 31b and 32b that is normally performed, and performs write access only to the upper memory 50b (or the lower memory 60b) as it is (E2). ). At this time, the memory access controller 220b operates independently in response to requests from the first and second inter-card communication bus controllers 31b and 32b.

  This is repeated to make the contents of the upper memory 50b and the lower memory 60b of the controller 100b the same as the contents of the upper memory 50a and the lower memory 60a of the controller 100a, and then start the operation of the controller 100b, thereby making the controllers 100a and 100b redundant. Can be realized.

  During the redundancy operation (normal operation), access between the controllers 100a and 100b is performed using one of the first and second inter-card communication buses 2 and 3. The memory access controllers 220a and 220b use the upper memory buses 250a and 250b and the lower memory buses 260a and 260b, which are separated separately, to simultaneously access the upper memory 50a and 50b and the lower memory 60a and 60b. .

  If one of the first and second inter-card communication buses 2 and 3 has failed during the equalization process, the bus selectors 210a and 210b are connected to the first inter-card communication bus controllers 31a and 31b and the first inter-card communication bus controllers 31a and 31b. The request between the two inter-card communication bus controllers 32a and 32b is stopped, and the normal equalization processing is performed using the normal one-side bus.

  In the present invention, the time for the controller equalization processing is obtained by performing the data copy operation using both the inter-card communication bus duplexed so as to be switched and used in the event of a failure only during the controller equalization processing. Can be shortened. Further, even if the bandwidth of the inter-card communication bus is small, a large amount of data copy operation can be executed.

FIG. 2 is an explanatory diagram of another embodiment of the present invention.
The controllers 100a, 100b, and 100c are made redundant, and each of them is further duplicated and connected by the first and second inter-card communication buses 2 and 3, thereby forming a multi-master configuration.
In normal times, each of the controllers 100a, 100b, and 100c executes access using one of the first and second inter-card communication buses 2 and 3. The other inter-card communication bus may be used as a main bus alternately with one inter-card communication bus, or may be used only at the time of failure or diagnosis.

The controller 100a confirms that both of the duplexed first and second inter-card communication buses 2 and 3 can be used, and the controller 100b communicates the first and second inter-card communication buses 2 and 3 with each other. Use both to perform fast write access.
At this time, for example, even when the first inter-card communication bus 2 is used for the controller 100c, the controller 100a accesses the lower bit data using the empty second inter-card communication bus 3. Since it continues, useless waiting time can be eliminated.

  Further, the upper bit data and the lower bit data are duplicated in the duplex inter-card communication bus, such that the upper bit data is allocated to the first inter-card communication bus 2 and the lower bit data is allocated to the second inter-card communication bus 3. Are transmitted separately, so even if one inter-card communication bus is used and the other write is delayed, the order of the data to be finally written is not changed, There is no need to worry about overwriting data. Thereby, efficient and safe data access can be performed.

  In addition, when both of the duplexed first and second inter-card communication buses 2 and 3 are normal, by using both inter-card communication buses, the high-speed access is not limited to the equalization processing. You can improve performance when you want to.

It is a block diagram which shows one Example of this invention. It is explanatory drawing of other embodiment of this invention. It is operation | movement explanatory drawing of the conventional redundant control system.

Explanation of symbols

2 First inter-card communication bus 3 Second inter-card communication bus 10a, 10b Processor 31a, 31b First inter-card communication bus controller 32a, 32b Second inter-card communication bus controller 50a, 50b Upper memory 52a, 52b Upper check bit memory 60a, 60b Lower memory 62a, 62b Lower check bit memory 100a, 100b, 100c Controller 210a, 210b Bus selector 220a, 220b Memory access controller 250a, 250b Upper memory bus 260a, 260b Lower memory bus

Claims (4)

In a redundant control system that redundantly operates multiple controllers,
Each controller is connected by a duplexed first and second inter-card communication bus,
A processor that executes control computation and access to each controller;
An upper memory for storing upper bit data and a lower memory for storing lower bit data,
A memory access controller connected to the upper memory and the lower memory by an upper memory bus and a lower memory bus, respectively, for controlling access;
A bus selector for selecting an inter-card communication bus to be used from among the first and second inter-card communication buses;
First and second inter-card communication bus controllers that respectively control access to the first and second inter-card communication buses;
A redundant control system comprising:   The bus selector issues an access request to one of the first and second inter-card communication bus controllers during normal access between the controllers, and communicates between the first and second cards during high-speed access. 2. The redundancy control system according to claim 1, wherein an access request is issued to both of the bus controllers, and one is used for upper bit data and the other is used for lower bit data.   3. The redundancy control system according to claim 2, wherein the high-speed access is an equalization process for making the contents of the memory identical among the controllers.   4. The redundancy according to claim 1, wherein each of the upper memory and the lower memory includes an upper check bit memory and a lower check bit memory, and diagnoses the upper bit data and the lower bit data separately. Control system.

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