JP2006114064A - Storage subsystem - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage subsystem having controllers in which exclusive control of caches between a plurality of controllers sharing the caches is eliminated. <P>SOLUTION: In the caches 33, 43 to which mutual multiplex writing is performed, cache areas are divided by each processor, each of the controllers 30, 40 accesses only to the self-controller control area. By fixing the cache areas used by each controller, the exclusive control between processors is made unnecessary and performance deterioration accompanying increase of the processors is prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a storage subsystem having a control device that controls information input / output requests from a host device, and more particularly to a storage subsystem having a controller and a cache memory in the control device as a redundant configuration.

  As a storage subsystem in which storage devices such as a controller and a disk are made redundant, there is a storage subsystem configured by a double system in which one system is used as a working system and the other system is used as a standby system.

  The storage subsystem described in Japanese Patent Laid-Open No. 4-215142 copies the storage information of the active disk device to the standby disk device via a shared disk device accessible from both systems, or the active system In the event of a controller failure, the storage information of the active disk device can be extracted by the standby controller, thereby improving data integrity when the controller and the disk device fail.

JP-A-4-215142

  As recent market trends, demands for higher performance, larger capacity, and lower price of storage devices are increasing, and RAID technology is emphasized. In a storage subsystem to which RAID technology is applied, a plurality of disk devices are configured in an array. When data is written, redundant data is written to a disk device different from the disk device storing the write data in addition to the write data. For the failure of any disk unit in the array configuration, the data integrity of the disk unit is improved by making it possible to recover the data on the failed disk unit from the data of other disk units and the redundant data. ing.

  However, in the storage subsystem to which the RAID technology is applied, the data integrity is improved, but the processing time increases due to the above-mentioned redundant data generation / writing, so that it is synchronized with the I / O processing from the host. If redundant data is generated / written, the write performance from the host is greatly degraded. Therefore, a write cache is indispensable for a controller of a storage subsystem to which RAID technology is applied.

  The write cache is a cache that is mounted in the controller and temporarily writes data. In a write request from the host, an end report is returned to the host when the cache is written. Then, generation of redundant data and storage of write data and redundant data in a disk device are performed asynchronously with host I / O processing, thereby preventing performance degradation during write processing. However, when the write cache is used, since the end report is sent to the host when the data is written on the cache, there is host data that is not reflected in the disk device on the cache. Therefore, if there is no redundancy in the cache, user data is lost when the cache fails. Therefore, in particular, in a control device used in a storage subsystem in which high reliability of data is strongly required, in addition to the conventional redundant configuration of the controller and storage device, the cache is generally made redundant. .

  In a storage subsystem with multiple controllers, if the cache is simply multiplexed, exclusive control from multiple controllers during cache access to prevent data consistency inconsistency due to simultaneous access of data on the cache from multiple controllers Is required. In the storage subsystem in which the controllers are multiplexed, the performance is lowered by this exclusive control as compared with the storage subsystem of the single controller.

  An object of the present invention is to eliminate the exclusive control of the cache between the processors accompanying the multiplexing of the controller and the multiplexing of the cache, and to improve the reliability without degrading the performance.

  In order to achieve the above object, in the storage subsystem according to the present invention, the means for exclusively determining the logical volume in charge of processing for each processor and the request from the host computer received by a certain processor are out of charge. In this case, the means for communicating the processing request to the processor in charge, the processor receiving the communication has means for communicating the processing result to the requesting processor, and each processor has a cache component such as a directory / data segment. Means for dynamically changing the state of the component according to the load of the processor, means for multiple writing of write data from the host computer to caches on a plurality of controllers, and a processor in the fault controller in the event of a controller failure The right to control the cache components of Means for switching to the processor in the controller, means for returning the control right to the restoration processor when the controller is restored, and if a cache memory failure occurs when writing to the disk device, the disk device from other caches that have been overwritten And means for writing.

  By the means described above, multiple writes can be performed to caches on a plurality of controllers without exclusive control of the caches between a plurality of processors, preventing the occurrence of performance degradation due to the use of multiple processors, and without reducing the performance. Reliability can be improved.

Further, by the above-described means, when the cache memory fails, the data can be prevented from being lost by writing to the disk device from another cache in which multiple writing is performed.
Furthermore, by the above means, when the controller fails, it is possible to automatically switch to the normal system and continue the process, and when the controller is restored, the process can be automatically returned to the recovery system. Stop operation can be realized.

  According to the present invention, in the storage subsystem in which the controller and the cache memory are duplicated, by allocating a part of the cache memory and the logical volume to each controller, the exclusive control between the processors in the controller with respect to the cache memory is eliminated. It is possible to prevent response performance deterioration due to the use of multiple processors.

  Further, by performing multiple writing to a plurality of caches, data can be prevented from being lost because, in the event of a cache failure, data can be written to the disk from another cache in which multiple writing is performed. Furthermore, by providing means for switching the cache memory control to a normal controller in the event of a controller failure and means for recovering from the controller failure, the system can be operated without interruption.

  FIG. 1 is a conceptual diagram of the present invention.

  In FIG. 1, 10 and 11 are host computers, 20 is a control device having a dual controller configuration, 50 is a disk device, and the disk device 50 is divided into two logical volumes, logical volume 0 and logical volume 1. .

  The host A 10 performs processing for the logical volume 0 via the controller A 30 in the control device 20, and the host B 11 performs processing for the logical volume 1 via the controller B 40 in the control device 20.

  Here, the logical volume 0 is assigned to the controller A30, and the logical volume 1 is assigned to the controller B40 as the processing logical volume. Further, the cache area in the controller is divided into two parts, ie, controller A caches 31 and 41 and controller B caches 32 and 42, respectively. Then, double writing is performed between the controller A caches 31 and 41, and double writing is performed between the controller B caches 32 and 42.

  The controller A 30 normally performs I / O processing using the controller A caches 31 and 41, and similarly, the controller B 40 performs I / O processing using the controller B caches 32 and 42. In this way, by individually allocating the cache area to be used for each controller, exclusive control between controllers can be eliminated, and performance deterioration due to an increase in the number of controllers can be prevented.

  Further, when the controller B40 fails, the controller A30 uses the controller B caches 32 and 42 to continue the processing from the host A10 to the logical volume 1 that was in charge of the processing of the controller B40 via the controller A30. Can do.

  Hereinafter, an embodiment of a control device having a multi-controller configuration according to the present invention will be described with reference to the drawings.

  FIG. 2 is a configuration diagram when the present invention is applied to a magnetic disk array subsystem having a multi-controller configuration.

In FIG. 2, reference numerals 1000, 1100, 1200, and 1300 denote host computers that are central processing units for performing data processing, 2000 denotes a control unit that controls a disk unit in a multi-controller configuration, and 7000 and 7100 store data of the host computers. Disk device to be Here, the control device 2000 may be inserted into a slot directly connected to the host bus and incorporated into the host housing, or may be incorporated into an independent housing as the control device, or realized as a housing incorporating a disk device. In some cases. The disk device groups 7000 and 7100 include a parity group including a data disk and a parity disk. Further, the disk device group 7000 is divided into logical volume 0 and logical volume 1, and the disk device group 7100 is divided into logical volume 2 and logical volume 3.

  The control device 2000 includes controllers 3000 and 4000 that control data transfer between the host computers 1000 and 1100 and the disk device 7000, and controllers 5000 and 6000 that control data transfer between the host computers 1200 and 1300 and the disk device 7100. .

  The controller 3000 includes a host I / F control unit 3100 that performs protocol control with the host computer 1000, a microprocessor (hereinafter referred to as “processor”) 3200 that controls the entire controller, a data transfer control unit 3300 that executes data transfer, A cache 3400 used for data transfer between the host computer 1000 and the disk device 7000 and communication between processors, and a DRVI / F control unit 3500 that performs protocol control with each disk device 7000 are configured. The controllers 4000, 5000, and 6000 have the same configuration as the controller 3000.

  The processor 3200 performs processing of the assigned logical volume that has been exclusively assigned to each processor in advance by means described later. The designation of the assigned logical volume for each processor can be set dynamically by receiving the assigned processor designation command for each logical volume from the host computer. The correspondence information between the processor and the assigned logical volume is stored in common memory areas 3410 and 4410 on the cache described later.

  The data transfer control unit 3300 has a function of multiplex writing write data from the host computer 1000 to the designated cache in response to an instruction from the processor 3200. In the configuration of this embodiment, double writing is performed between the cache 3400 and the cache 4400, and double writing is performed between the cache 5400 and the cache 6400. Hereinafter, a method of dual writing on two surfaces of the cache 3400 and the cache 4400 will be described.

  The contents of the cache 3400 and the cache 4400 will be described with reference to FIG. Since the cache 3400 and the cache 4400 have the same internal configuration, the cache 3400 will be described as an example. The cache 3400 includes a common memory area 3410 that stores control information used for inter-processor communication, a processor 3200 area 3480, and a processor 4200 area 3490.

  The processor 3200 area 3480 includes a data storage area 3482 for temporarily storing data during data transfer between the host computer and the disk device, and data management information 3481 for managing the data storage area 3482. The data storage area 3482 The write data stored in and the management information of the write data are written twice in the processor 3200 area 4480 in the cache 4400. Similarly, in the processor 4200 area 3490, the write data and the write data management information of the processor 4200 area 4490 in the cache 4400 are written twice by the processor 4200.

  The common memory area 3410 includes logical volume responsible processor information 3420, processor load information 3430, multiplex write information 3450, and interprocessor communication memory 3460. These pieces of information are all stored in the cache 3400 by the data transfer control units 3300 and 4300. It is written twice in 4400.

  FIG. 3C shows the configuration of the interprocessor communication memory. The inter-processor communication memory 3460 includes write memories 3461, 3462, 3463, and 3464 for each of the processors 3200, 4200, 5200, and 6200. FIG. 3D shows the configuration of the processor writing memory. The processor 3200 write memory 3461 includes areas 3471, 3472, and 3473 for requesting processors 4200, 5200, and 6200 other than its own processor, and areas 3474 and 3475 for responding to requests from processors 4200, 5200, and 6200 other than its own processor. 3476. The internal configuration of the processors 4200, 5200, 6200 write memory 3462, 3463, 3464 is the same as the processor 3200 write memory 3461.

  Duplication is performed between the cache 5400 and the cache 6400 as well as between the cache 3400 and the cache 4400 except for the common memory area. The common memory area does not exist in the caches 5400 and 6400 because the information written in the caches 3400 and 4400 is shared by all the processors in the control device.

  In the control apparatus embodying the present invention, the number of controllers is increased in units of two controllers, and the dual writing is performed only between the caches of the paired controllers, and each disk device is also used for the data bus on the drive side. By connecting only to the paired controllers, the hardware configuration can be simplified, and contention on the drive-side data bus can be avoided.

Next, I / O processing from the host computer 1000 in the magnetic disk subsystem in this embodiment will be described with reference to FIGS. 4, 5, and 6. FIG. First, I / O processing to the logical volume in charge of the processor 3200 will be described.
FIG. 4 is a flowchart showing I / O processing from the host. At the time of a write request from the host computer 1000, the processor 3200 first acquires the processor information in charge of the processing request logical volume from the logical volume processor information 3420 in the common memory area 3410, and transfers it to its own processing logical volume (LUN). (Step 902), it is recognized that the processing is for the logical volume in charge of its own processor processing. Next, the process type is determined (step 903), and it is recognized that the process is a write process. The host I / F control unit 3100 receives the write logical data, and the data transfer control unit 3300 stores it in the controller 3000 area 3480 of the cache 3400 and the controller 3000 area 4480 of the cache 4400 together with the management information in a double manner. (Step 904). At this time, the end is reported to the host computer 1000 (step 905).

  FIG. 5 is a flowchart showing processing for storing data in the cache in the disk device. The processor 3200 stores the write data on the processor 3200 area 3480 in the disk device group 7000 by the data transfer control unit 3300 and the DRV I / F control unit 3500 asynchronously with the I / O processing from the host computer 1000 (step S3). 922). At this time, if a read error occurs due to a memory failure in the cache (step 923), data is prevented from being lost by storing the data from the redundant processor 3200 area 4480 into the disk device 7000 (step 924). it can.

  At the time of a read request from the host computer 1000, the processor 3200 recognizes that the processing is to the own processor processing logical volume (LUN) (step 902) and then determines the processing type as in the above writing processing (step 902). Step 903). When recognizing that the I / O process is a read process, the data transfer control unit 3300 and the DRV I / F control unit 3500 store the data from the disk device group 7000 into the controller 3000 area 3480 of the cache 3400 (step 906). The data is transferred to the host computer (step 907).

  Next, I / O processing from the host computer 1000 to the logical volume in charge of the controller 4000 will be described.

  At the time of a write request from the host computer 1000, the processor 3200 first acquires the processor information in charge of the processing request logical volume from the logical volume manager information 3420 in the common memory area 3410, (Step 902), and recognizes that the process is to a logical volume not in charge of processing. Next, the process type is determined (step 908), and it is recognized that the process is a write process. Then, the write logical data from the host computer 1000 is stored in the controller 3000 area 3480 of the cache memory, and a write process is requested to the controller 4000 in charge of this logical volume (step 909).

  In order to request the processor 4200 to perform a write process, the processor 3200 uses the data transfer control unit 3300 to store the write data logical address, the write data cache storage address, the data length, and the processing type information in the common memory areas 3410 and 4410. The processor 3200 is stored twice in an area for requesting the processor 4200 in the memory for writing. Here, the process type information is information for determining whether the process is a writing process or a reading process. The processor 4200 refers to a request area for the own processor in the common memory areas 3410 and 4410 in a certain time such as 10 ms, and recognizes a request from another processor.

  FIG. 6 is a flowchart showing processing of the processor 4200 when a processing request from the processor 3200 is received. The processor 4200 that has recognized the request from the processor 3200 by the above-described method (step 931) refers to the processing type in the request area to the processor 4200 in the processor 3200 write memory, and determines that the request is a write processing request. Recognize (step 932). Then, the processor 4200 acquires the write logical address, the storage address of the write data in the cache, and the data length in the area for request to the processor 4200 in the processor 3200 write memory (step 933), and Write data corresponding to the data length from the storage address is stored twice in the processor 4200 areas 3490 and 4490 together with the write logical address and the data length, which are the management information (step 934). Then, the end information is set in a response area to the request from the processor 3200 in the memory for writing to the processor 4200 in the common memory areas 3410 and 4410, thereby communicating the end of processing to the processor 3200 (step 935).

  After the processing request to the processor 4200, the processor 3200 monitors the end of the processing of the processor 4200 by referring to the response area for the request from the processor 3200 in the processor 4200 write memory (step 910) (step 910). In response to this processing end communication, the end is reported to the host computer 1000 (step 905). Thereafter, the processor 4200 performs a write process of the write data to the disk device 7000 asynchronously with the host I / O process according to FIG.

  In FIG. 4, when there is a read request from the host computer 1000, the processor 3200 recognizes that the process is to a non-processing logical volume (LUN) as in the case of receiving the write request (step 902). The processing type is determined (step 908). When recognizing that it is a read process, the processor 3200 displays the read request logical address, the storage permission address of the read data in the cache, the data length, and the processing type information in the processor 3200 write memory in the common memory areas 3410 and 4410. By storing in the request area to 4200, the read request is communicated to the processor 4200 in charge of the LUN processing (step 911).

  In FIG. 6, the processor 4200 that has recognized the request from the processor 3200 (step 931) recognizes that it is a read process based on the information in the common memory area (step 932). Then, the read request logical address, the storage permission address of the read data in the cache, and the data length are obtained from the common memory area (step 936). Next, the data is stored from the disk device 7000 into the processor 4200 area 4490, and this data is stored in the storage permission address on the cache 3400 (step 937). Furthermore, by setting end information in an area for responding to a request from the processor 3200 in the memory for writing to the processor 4200 in the common memory areas 3410 and 4410, the end of reading is communicated to the processor 3200 (step 935).

  In FIG. 4, the processor 3200 monitoring the processing end of the processor 4200 (step 912) receives this read end report and transfers the data to the host computer (step 913).

  As described above, the processor 3200 normally performs I / O processing using the areas 3480 and 4480 for the processor 3200. Similarly, the processor 4200 normally performs I / O processing using the areas 4490 and 4490 for the processor 4200.

  In this way, by fixing the cache area to be used for each processor, it is possible to eliminate exclusive control between processors and prevent performance deterioration due to an increase in the number of processors. Especially in a system that does not share files (logical volumes) between host computers, this logical volume is assigned to the processor in the connected controller, eliminating communication control between processors during I / O processing. And further performance improvement is possible.

  Next, an automatic switching / restoring method at the time of failure of the controller 4000 will be described with reference to FIGS. During the execution of the I / O process, the processor that has detected the failure of the controller 4000 uses the common memory area 3410 to communicate the failure of the controller 4000 to all the remaining processors. At this time, a processing takeover request is also communicated to the processor 3200 in the controller 3000 in which the controller 4000 and the cache are double-written. In this embodiment, a case where the processor 3200 detects a failure will be described.

  FIG. 7 is a flowchart showing processing of the processor 3200 when the processor 3200 detects a failure of the controller 4000. When the processor 3200 is executing the I / O process (step 950) and detects the failure of the controller 4000 (step 951), the processor 3200 communicates the failure of the controller 4000 to the processors 5200 and 6200 by the method described above. Then, in order to disconnect the fault controller from the system, the data transfer that the write data from the host computer and the data in the common memory area that are double-written to the caches 3400 and 4400 are changed to the single-write to the cache 3400 The control unit 3300 is instructed (step 952). Further, the processors 5200 and 6200 that have recognized the request from the processor 3200 change the common memory area to single writing to the cache 3400. Next, the processor 3200 switches the control right of the area for the processor 4200 to the processor 3200 in order to take over the processing of the processor 4200 (step 953). With these processes, the switching of the control right is completed, and the processor 3200 resumes the normal I / O process (step 954).

  FIG. 8 is a flowchart showing a recovery process of the controller 4000 in which a failure has occurred. When the faulty part of the controller 4000 is replaced (step 971), the processor 4200 transmits a recovery start to all the processors using the common memory area 3410 (step 972). The processors 3200, 5200, and 6200 receive this recovery start notification (step 955), and instruct the data transfer control unit of each controller to perform double writing to the caches 3400 and 4400, and the common memory areas 3410, 4410. Is used to communicate the processing end response to the processor 4200 (step 956). The processor 4200 that has received the completion report from all the processors (step 973) performs data recovery of the cache 4400 (step 974). When the data recovery is completed, the recovery completion is transmitted to the processor 3200 using the common memory areas 3410 and 4410 (step 975).

  In FIG. 7, upon receiving this completion notification (step 958), the processor 3200 restores the control right of the area for the processor 4200 to the processor 4200 (step 959), and uses the common memory area to restore the control right to the processor 4200. (Step 960). In FIG. 8, the processor 4200 that has received this notification (step 976) restarts the I / O processing (step 977).

  In the above embodiment, an example in which each controller has one processor and one host I / F control unit is shown. However, the processor that receives the command from the host computer is in charge of any number of these controllers. The same can be realized by transmitting a processing request to the processor.

  Further, the cache division method is not uniform for each processor, and can be set / changed by user designation. In particular, when a specific processor is operated in hot standby, the cache can be used effectively by not allocating the cache area to the hot standby processor. It is also possible to change dynamically according to the load of the processor. In this embodiment, an instruction to perform division according to user designation or change according to the processor load is performed by a host command. However, a device such as a panel may be connected and input from there. Of course good.

  Next, a method for realizing dynamic allocation of the controller cache will be described below.

First, a cache management method will be described with reference to FIG.
The data storage area for each processor is divided into management units called segments 983. Each segment has a segment management block 981 (hereinafter referred to as SGCB) in the data management information for each segment, and stores segment management information and a segment address. Also, these SGCBs are connected by being divided into two queues, a dirty queue 980 and a clean queue 982, depending on the attribute of the segment. The dirty queue 980 is connected to the SGCB of the segment storing the write data not reflected on the disk, and the other SGCBs are connected to the clean queue 982.

  In order to realize dynamic cache allocation, load information for each processor is stored in a common memory area. As the load information, for example, the amount of clean SGCB in the cache is used. Each processor updates this information in response to the queue transition between SGCB clean and dirty. The processor refers to this information at regular intervals such as 1 minute, and the load is the same from the clean queue of the processor with the lowest load to the clean queue of the processor with the highest load among the processors sharing the cache. SGCB and management segment are migrated until. At this time, the SGCB in use is not subject to migration. At the time of migration, the SGCB storage data information is cleared. During this transition, I / O processing of the processor performing the transition is stopped using processor communication.

  In the above embodiment, the cache is shared between the two controllers, and each of them is written twice in the cache of the controller. However, if the cache area is divided for each processor, The cache sharing method and the multiple writing method can be similarly realized by any method.

  An example of cache multiple writing is shown in FIG.

  (1) is a method in which the cache is shared by the entire apparatus and is written twice. That is, the processor 3200 uses the caches 3400 and 4400, the processor 4200 uses the caches 4400 and 5400, the processor 5200 uses the caches 5400 and 6400, and the processor 6200 uses the caches 6400 and 3400. ing.

  (2) is a system in which the cache is shared by the entire apparatus, and multiple writing is performed in all caches. That is, the processors 3200, 4200, 5200, and 6200 perform multiple writing using the caches 3400, 4400, 5400, and 6400, respectively. In this case, if the controller fails, the processor with the lowest load among the processors sharing the cache takes over the processing of the failed controller responsible logical volume. In these cases, the data bus on the disk side is connected to a common bus for all disk devices and all controllers in the device so that an arbitrary processor can take over the processing of the logical volume in charge of the fault controller. Of course, these multiple writing systems can be mixed in the apparatus. The designation of these multiple write methods has multiple write information in the common memory areas 3410 and 4410, and each processor 3200, 4200, 5200 and 6200 determines the transfer method of write data based on this information as a data transfer control unit. This can be realized by instructing 3300, 4300, 5300, 6300.

It is a block diagram showing the outline | summary of this invention. It is a block diagram of the control apparatus which is an Example of this invention. It is a figure which shows the structure of the cache of the controller which is an Example of this invention. It is a flowchart which shows operation | movement of the I / O process from the host of the controller by the Example of this invention. 4 is a flowchart illustrating an operation of storing data in a cache of a controller in a disk device according to an embodiment of the present invention. It is a flowchart which shows operation | movement of the control apparatus of the controller which received the process request from the other controller by the Example of this invention. It is a flowchart which shows operation | movement of the controller which detected the failure of the other controller by the Example of this invention. It is a flowchart which shows the operation | movement of a recovery process of the controller in which the failure generate | occur | produced by the Example of this invention. It is a figure which shows the management system of the cache used in the controller by the Example of this invention. It is a figure which shows the structure of the cache of another Example 2 night controller of this invention.

Explanation of symbols

10/11: Host computer 20: Controller 30/40: Controller 31/41: Controller A cache memory 32/42: Controller B cache memory 33/43: Cache memory 50: Disk device 1000/1100/1200/1300 : Host computer 2000: Control device 3000/4000/5000/6000: Controller 3100/4100/5100/6100: Host I / F control unit 3200/4200/5200/6200: Microprocessor 3300/4300/5300/6300: Data transfer Control unit 3400/4400/5400/6400: Cache 3500/4500/5500/6500: DRVI / F control unit 7000/7100: Disk device group

Claims (19)

A storage device for storing data of the host computer and having a plurality of storage areas;
The storage device is controlled based on an instruction from the host computer, data transfer between the host computer and the disk device is controlled, and data transferred between the host computer and the storage device is temporarily stored. A storage subsystem comprising a controller having a plurality of cache memory having a plurality of areas to be held and a controller comprising a path connecting the plurality of controllers,
The controller includes at least one of a plurality of storage areas of the storage device and at least one of a plurality of areas of the cache memory of the controller and a plurality of areas of a cache memory of another controller connected by the path A storage subsystem characterized in that at least one is allocated.   2. The storage subsystem according to claim 1, wherein the controller writes data transferred from the host computer into a plurality of the cache memories assigned to the controller.   3. The storage subsystem according to claim 2, wherein when a failure occurs in the controller, the other controller performs processing of a storage area of the storage device that was in charge of the failure controller. system.   4. The storage subsystem according to claim 3, wherein the other controller is a hot standby controller, and a storage area of a cache memory is not allocated to the hot standby controller. .   2. The storage subsystem according to claim 1, wherein the control device has a path connecting the plurality of controllers, and the controller issues a processing request for a storage area of the storage device allocated to another controller from a host computer. When received, the controller communicates the processing request to the other controller.   The storage subsystem according to claim 1, wherein the division of the cache area is changed according to a load on the controller. A magnetic disk having a plurality of logical volumes for storing host computer data;
A cache memory having a plurality of areas for temporarily holding data transferred between the host computer and the disk device, and a data transfer control unit for connecting the cache memory and controlling data transfer of the data A storage subsystem having a controller for controlling the magnetic disk device based on an instruction from the host computer, and a controller for controlling the magnetic disk device based on an instruction from the host computer.
The controller includes at least one of a plurality of logical volumes of the magnetic disk device, at least one of a plurality of areas of a cache memory of the controller, and at least one of a plurality of areas of a cache memory of another controller. A storage subsystem characterized by being assigned.   8. The storage subsystem according to claim 7, wherein the controller includes a cache memory area of the controller assigned to the controller for data transferred from the host computer, and another controller assigned to the controller. A storage subsystem for writing to a cache memory area.   9. The storage subsystem according to claim 8, wherein when a failure occurs in the controller, the other controller performs processing of the logical volume for which the failure controller was responsible.   10. The storage subsystem according to claim 9, wherein the other controller is a hot standby controller, and a storage area of a cache memory is not allocated to the hot standby controller. system.   8. The storage subsystem according to claim 7, wherein when the controller receives a processing request for a logical volume assigned to another controller from a host computer, the data transfer control unit of the controller sends the request to the other controller. A storage subsystem, wherein a processing request is transferred through one path, the other controller that has received the processing request performs processing on the logical volume, and transfers a processing result to the controller.   8. The storage subsystem according to claim 7, wherein the division of the cache area is changed according to a load on the controller.   8. The storage subsystem according to claim 7, wherein the path between the controllers includes a first path that connects the two controllers and a second path that connects the set of the two controllers. Storage subsystem.   14. The storage subsystem according to claim 13, wherein when a controller is added to the control device, the controller is added in units of two of the controllers. A storage device for storing data of the host computer and having a plurality of storage areas;
The storage device is controlled based on an instruction from the host computer, data transfer between the host computer and the storage device is controlled, and data transferred between the host computer and the storage device is temporarily stored. A storage subsystem comprising a controller having a plurality of cache memory having a plurality of areas to be held and a controller comprising a path connecting the plurality of controllers,
The controller includes at least one of a plurality of storage areas of the storage device and at least one of a plurality of areas of the cache memory of the controller and a plurality of areas of a cache memory of another controller connected by the path At least one is assigned,
The data transferred from the host computer is written in the cache memory area of the controller allocated to the controller and the cache memory area of another controller allocated to the controller. Storage subsystem.   16. The storage subsystem according to claim 15, wherein, when a failure occurs in the controller, the other controller performs processing of a storage area of the storage device that was in charge of the failure controller. system.   16. The storage subsystem according to claim 15, wherein the other controller is a hot standby controller, and the storage area of the cache memory is not allocated to the hot standby controller. .   16. The storage subsystem according to claim 15, wherein the control device has a path connecting the plurality of controllers, and the controller issues a processing request for a storage area of the storage device allocated to another controller from a host computer. When received, the controller communicates the processing request to the other controller. 16. The storage subsystem according to claim 15, wherein the division of the cache area is changed according to a load on the controller.

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