JP4679178B2 - Communication device and memory device - Google Patents

Description

  The present invention relates to a communication device and a memory device, and more particularly to a communication device having a redundant memory structure of an active system and a standby system, and a memory device that has both functions of an active system and a standby system and performs data storage processing.

  In recent years, communication networks represented by the Internet have been greatly increased in capacity and widened, and services have been diversified. In such a situation, an exchange system that constitutes a backbone network and is managed by a business operator has an increased amount of data to be handled, and further higher functionality and reliability are required.

  In the exchange system, if a failure occurs and the recovery is delayed, the damage to the service becomes serious. Therefore, a redundant configuration such as duplication of various packages and paths is adopted in the device. Immediate switching to the redundant side improves fault tolerance.

  In particular, in a switching system, call control (control related to a call) must be normally continued when a failure occurs in the system for some reason or when a unit is replaced by maintenance. For this reason, the memory for storing data related to call control and the like is also prepared for the occurrence of a failure by adopting a duplex configuration of active / standby systems.

  Also, when switching from the active memory to the standby memory, the data in the active memory must be copied to the standby memory in advance during system operation so that the standby memory can operate normally immediately. There is.

  FIG. 9 is a diagram showing the configuration of the exchange system. The switching system 100 includes CPUs 101 to 104, an operation system memory 105, a standby system memory 106, a bus arbitration unit 107, and a common bus 108. The switching system 100 has a distributed system configuration in which processing load is distributed by a plurality of CPUs to perform switching control. ing.

  During normal operation of the system, the CPUs 101 to 104 access the operational memory 105 and perform data R / W (read / write). In this case, since the CPUs 101 to 104 and the operation system memory 105 are connected via the common bus 108, only one CPU can use the common bus 108 at a certain moment.

  For this reason, the bus arbitration unit 107 performs arbitration, sequentially assigns the right to use the common bus 108 to each of the CPUs 101 to 104, and the CPU that has obtained the right to use accesses the operational memory 105.

  Here, a data copy operation from the active memory 105 to the standby memory 106 will be described. Consider a case where the standby memory 106 is mounted on the system while the system is operating with the data stored in the active memory 105.

  When the standby memory 106 is connected to the common bus 108, copy control for copying data in the active memory 105 to the standby memory 106 is started. At the time of copy control, a certain CPU (referred to as CPU 101) performs read access to the operational memory 105 via the common bus 108 to read all data one by one.

  The standby system memory 106 monitors data appearing on the common bus 108 (referred to as snoop), and writes the read access contents from the CPU 101 to the operation system memory 105 in its own memory area.

  By performing such copy control, the data a stored in the address A of the active memory 105 is also stored in the address A of the standby memory 106, and is exactly the same as the active memory 105. The standby memory 106 that stores the data in the same storage area generates the data. As a result, the memory can be switched at the time of transition from the active system to the standby system.

As a conventional memory redundancy technique, a technique has been proposed in which a data copy dedicated bus is provided between an active memory and a standby memory to perform data transfer (for example, Patent Document 1).
JP-A-5-265789 (paragraph numbers [0014] to [0020], FIG. 1)

  In the conventional copy control in which the access to the active memory 105 from an arbitrary CPU as described above is monitored and written to the standby memory 106, the standby memory must be accessed unless the CPU accesses the active memory 105. Since copying to 106 is not performed, it is necessary for the CPU to repeatedly access the active memory 105. For this reason, it takes a very long time to copy all the contents of the active memory 105 to the standby memory 106.

  In addition, since one CPU occupies a process for performing a copy, a reduction in processing capacity as an exchange control occurs. Furthermore, during the access from the CPU to the operational memory 105, the common bus 108 is occupied, and therefore (a huge) access for the entire area of the operational memory occurs repeatedly. Access to the active memory 105 is restricted.

  From the above, in the conventional copy control, when the standby memory 106 is newly incorporated, it takes time until the consistency between the active memory 105 and the standby memory 106 can be guaranteed, and the replacement during operation is also performed. There was a problem of reducing the capacity of the entire system.

  On the other hand, in the above prior art (Japanese Patent Laid-Open No. 5-265789), since a dedicated bus is provided between the active memory and the standby memory to perform data transfer, a common bus between the CPU and the memory is not used. Therefore, a decrease in replacement processing performance can be avoided.

  However, if data is copied from the active memory to the standby memory device on the dedicated bus, if the original operating CPU accesses the active memory, how is the content stored in the standby memory device? Whether it can be reflected also becomes a problem.

  In general, during a memory copy operation, access from the CPU is temporarily suppressed, and when copying is performed or when there is write access from the CPU in an area that has already passed as a copy area, There is a method of copying the area to the standby system memory again.

  However, these methods cannot affect the performance of the system and reflect real-time data on the standby memory. In addition, when the CPU repeatedly accesses the area after completion of copying, the data reflection to the standby memory cannot be completed indefinitely.

  The present invention has been made in view of the above points, and without affecting the system operation, the data stored in the operation system memory is copied to the standby system memory at a high speed, so that the operation system and the redundancy system can be copied. An object of the present invention is to provide a communication device that enables a quick switching to a network.

  Another object of the present invention is to copy data stored in the active memory to the standby memory at high speed without affecting the system operation, and to quickly switch from the active system to the redundant system. It is to provide a memory device that is made possible.

  In the present invention, in order to solve the above problem, in the communication apparatus 10 having the active and standby memory redundancy structures as shown in FIG. A plurality of communication units 11-1 to 11-n that perform distributed processing of communication control are connected to the system side memory unit 13, and the active system side memory unit 12 and the standby system side memory unit 13 are connected. When recognizing that the memory copy bus 15, the active memory 12a for storing data, and the memory unit 13 on the standby side are mounted, the data stored in the active memory 12a is read and the memory copy bus 15, the data transfer unit 12 b that transfers to the standby-side memory unit 13 via 15, the access from the communication units 11-1 to 11-n to the active memory 12 a, and the data transfer Via an access arbitration unit 12c that arbitrates access to the active memory 12a from the unit 12b, a standby memory 13a that stores data, and a memory copy bus 15 The data transferred from the active system memory control unit 12 is written into the standby system memory 13a, and the memory copy unit 13b for performing memory copy, and the communication system 11-1 to 11-n to the active system memory control unit 12 When the write access is monitored and the memory copy to the standby memory 13a is being performed and there is a write to the area where the copy has already been completed, the write address and the write data appearing on the common bus 14 Is temporarily stored, and after the memory copy is completed, the write control unit 13c writes the temporarily stored write content to the standby memory 13a. , The communication apparatus 10, wherein is provided to have a, and standby memory controller 13 consists.

  Here, the communication units 11-1 to 11-n are connected to the memory unit 12 on the active system side and the memory unit 13 on the standby system side via the common bus 14, and perform communication control distributed processing. The memory copy bus 15 connects the memory unit 12 on the active side and the memory unit 13 on the standby side. The operational memory 12a stores data. When the data transfer unit 12b recognizes that the memory unit 13 on the standby system side is mounted, the data transfer unit 12b reads the data stored in the active memory 12a and passes through the memory copy bus 15 to the memory unit on the standby system side. 13 to transfer. The access arbitration unit 12c arbitrates between access from the communication units 11-1 to 11-n to the active memory 12a and access from the data transfer unit 12b to the active memory 12a. The standby memory 13a stores data. The memory copy unit 13b writes the data transferred from the active memory control unit 12 via the memory copy bus 15 to the standby system memory 13a and performs memory copy. The write control unit 13c monitors the write access to the active memory control unit 12 from the communication units 11-1 to 11-n, and already performs the memory copy to the standby memory 13a. When there is a write to the area where the copy has been completed, the write address and write data appearing on the common bus 14 are temporarily stored, and after the memory copy is completed, the temporarily stored write content is written to the standby memory 13a.

  In the communication device of the present invention, the active memory control unit reads data stored in the active memory and transfers the data to the standby memory via the memory copy bus. The standby system memory controller writes the transferred data to the standby system memory, performs memory copy, and writes to the area where copying has already been completed while performing memory copy to the standby system memory. In the case where there is, the configuration is such that after the memory copy is completed, the temporarily stored writing content is written to the standby memory. As a result, the data stored in the active memory can be copied to the standby memory at high speed without affecting the system operation, and a quick switch from the active system to the redundant system becomes possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a principle diagram of a communication apparatus. The communication device 10 is a device having an active and standby memory redundancy structure composed of communication units 11-1 to 11-n, an active memory control unit 12, and a standby memory control unit 13, such as an exchange system. Applies to

  The communication units 11-1 to 11-n, the active memory control unit 12 and the standby memory control unit 13 are connected to each other via a common bus 14, and the active memory control unit 12 and the standby memory control unit 13 The buses 15 are connected to each other.

The communication units 11-1 to 11-n access the active memory control unit 12, perform data R / W, and perform distributed processing of communication control such as call control.
The active memory control unit 12 includes an active memory 12a, a data transfer unit 12b, and an access arbitration unit 12c. The operational memory 12a stores data. When the data transfer unit 12b recognizes that the standby system memory control unit 13, which is a memory unit on the standby system side, is mounted, the data transfer unit 12b autonomously reads the data stored in the active system memory 12a, and reads the memory copy bus The data is transferred to the standby memory control unit 13 via 15.

The access arbitration unit 12c arbitrates between access from the communication units 11-1 to 11-n to the active memory 12a and access from the data transfer unit 12b to the active memory 12a.
The standby system memory control unit 13 includes a standby system memory 13a, a memory copy unit 13b, and a write control unit 13c. The standby memory 13a stores data. When the memory copy unit 13b receives the data transferred from the active system memory control unit 12 via the memory copy bus 15, the memory copy unit 13b autonomously writes the data to the standby system memory 13a and performs memory copy.

  The write control unit 13c includes a temporary storage unit 13c-1, and monitors the write access to the active memory control unit 12 from the communication units 11-1 to 11-n and performs memory copy to the standby memory 13a. During the execution, when there is a write to the area where the copy has already been completed, the write address and the write data appearing on the common bus 14 are stored in the temporary storage unit 13c-1. Then, after the memory copy is completed, the temporarily stored writing content is written into the standby memory 13a.

  Note that each component of the active memory control unit 12 and the standby memory control unit 13 is mounted on the substrate as substantially the same single memory device, and the functions are shown separately in the figure for easy understanding. It was.

  Next, a specific configuration of the communication device 10 will be described. FIG. 2 is a diagram illustrating the configuration of the communication apparatus. The communication device 10 a includes CPUs 11-1 to 11-4, an active memory control unit 12, a standby memory control unit 13, and a bus arbitration unit 16.

  The CPUs 11-1 to 11-4 perform call control with load distribution. The operational memory control unit 12 is an operational memory unit that stores data shared and used by the CPUs 11-1 to 11-4. The standby system memory control unit 13 is a standby system memory unit that is provided in case the active system memory control unit 12 fails. The bus arbitration unit 16 performs arbitration control for the CPUs 11-1 to 11-4 to use the common bus 14.

  In normal operation, the CPUs 11-1 to 11-4 perform R / W of data stored in the active memory 12 a in the active memory control unit 12. By this access, the latest data shared by the plurality of CPUs 11-1 to 11-4 is always stored in the active memory 12a, and each CPU uses the latest data in the active memory 12a to perform call control. .

  On the other hand, similar data is also stored in the standby system memory 13a in the standby system memory control unit 13, and when the operation system memory 12a is abnormal, the system immediately switches to the standby system memory 13a and continues to the plurality of CPUs 11-1 to 11-4. Continues the call control based on the latest data stored in the standby memory 13a.

  Next, a description will be given in detail with reference to FIG. 3 to FIG. 5 of an operation in which the standby memory control unit 13 is newly incorporated in the system and the memory is copied during normal operation using the active memory 12a.

  3 to 5 are diagrams showing the flow of the memory copy operation of the communication device 10a. 3 shows step S1 to step S6, FIG. 4 shows step S7, and FIG. 5 shows step S8.

  [S1] The standby memory control unit 13 is mounted. At this time, the standby system memory control unit 13 is connected to the common bus 14 and further connected to the active system memory control unit 12 through the memory copy bus 15.

  [S2] When the data transfer unit 12b in the active memory control unit 12 receives the memory copy start instruction from the standby memory control unit 13, the data stored in the active memory 12a is transferred from the first address to the last address. The data is sequentially transferred to the memory copy unit 13b in the standby system memory control unit 13 via the memory copy bus 15 (since no data exists in the standby system memory 13a, the data stored in the active system memory 12a is transferred to the memory copy unit 13b. All need to be copied to the standby memory 13a).

  [S3] The memory copy unit 13b receives the transferred data and copies it to the standby memory 13a. At this time, the same data is stored and copied to the same address stored in the active memory 12a.

[S4] Even during the active-to-standby memory copy, the CPUs 11-1 to 11-4 arbitrarily perform R / W access to the active memory 12a via the common bus 14.
[S5] The write control unit 13c monitors write access from the CPUs 11-1 to 11-4 to the active memory control unit 12 (performs snoop). If there is a write to the area of the operational memory 12a that has already been copied during the memory copy to the standby memory 13a, the write address and write data that appear on the common bus 14 are temporarily stored. Store in the storage unit 13c-1.

  [S6] The access arbitration unit 12c performs access arbitration for the same address with respect to the active memory 12a. For example, when the access to the address A to the operational memory 12a for the CPU 11-1 and the access to the address A from the data transfer unit 12b to the operational memory 12a occur simultaneously, the access on the CPU side is given priority. Select to prevent mutual conflict.

  [S7] Assume that all data in the active memory 12a is copied to the standby memory 13a. After the memory copy is completed, the write control unit 13c writes the write contents stored in the temporary storage unit 13c-1 to the standby system memory 13a (if the data a is written at the address A of the operation system memory 12a, the write control unit 13c Data a is also stored at address A of the system memory 13a). At this time, the same data is stored at the same address in the active memory 12a and the standby memory 13a.

  [S8] When the data storage update processing for the standby memory 13a in the write control unit 13c is completed (when all the data stored in the temporary storage unit 13c-1 is written in the standby memory 13a), the CPUs 11-1 to 11-11 -4 performs memory read access, it accesses the operational memory 12a to read data. When performing memory write access, both the active memory 12a and the standby memory 13a are accessed and data is written and reflected.

  Note that the write control unit 13c provides a threshold for the temporarily stored write content, and when the temporarily stored content is written from the temporary storage unit 13c-1 to the standby memory 13a, When the storage amount of the temporary storage unit 13c-1 is equal to or less than the threshold value, the new temporary storage process is stopped (that is, when the CPU 11-1 to 11-4 is operated when the threshold value is equal to or less than the threshold value). Even if a write access is made to the system memory 12a, the access contents are not taken into the temporary storage unit 13c-1.

  When all the contents currently stored in the temporary storage unit 13c-1 are written to the standby system memory 13a, and the write access to the active system memory control unit 12 is made from the CPUs 11-1 to 11-4 after the completion of the writing. Is directly written in the standby memory 13a without being temporarily stored.

  Since write access from the CPUs 11-1 to 11-4 to the active memory 12 a is arbitrarily performed, even after the memory copy via the memory copy bus 15 from the active memory 12 a to the standby memory 13 a is completed, the CPU 11- Write access may be performed from 1 to 11-4 to the operational memory 12a several times.

  In such a state, if the contents to be written are temporarily stored and the data stored in the standby system memory 13a is updated, the standby system memory control unit 13 may not enter the standby state indefinitely (temporary storage). If the storage amount falls below the threshold when the data stored in the temporary storage unit 13c-1 is being discharged, the temporary storage process is stopped and the standby memory All the write contents are written to 13a, and subsequent write accesses are directly written to the standby memory 13a, so that the standby memory control unit 13 is brought into a standby state at an early stage.

Next, a memory copy operation sequence of the communication device 10a will be described. FIG. 6 is a diagram showing a memory copy operation sequence.
[S11] The CPU 11 arbitrarily accesses the operational memory 12a via the common bus 14 for R / W.

[S12] The memory copy unit 13b transmits a memory copy start instruction to the data transfer unit 12b.
[S13] The data transfer unit 12b reads the data at the head address from the active memory 12a.

[S14] The data transfer unit 12b transfers the start address and the data stored at the start address to the memory copy unit 13b via the memory copy bus 15.
[S15] The memory copy unit 13b writes the transferred data into the standby memory 13a and copies the memory (such an operation is performed up to the final address).

  [S16] The write controller 13c monitors the write access made by the CPU 11 to the active memory 12a, and temporarily stores the write contents (write address and data stored in the write address) via the common bus 14. To do.

[S17] The data transfer unit 12b reads the data at the final address from the active memory 12a.
[S18] The data transfer unit 12b transfers the final address and the data stored at the final address to the memory copy unit 13b via the memory copy bus 15.

  [S19] The memory copy unit 13b writes the transferred data to the standby memory 13a and copies the memory. Memory copy from the active memory 12a to the standby memory 13a is completed.

  [S20] When the memory copy from the active memory 12a to the standby memory 13a is completed, the logical connection between the memory copy unit 13b and the standby memory 13a is disconnected, and the write control unit 13c and the standby memory 13a are disconnected. Connect logically.

  [S21] The write control unit 13c writes the temporarily stored write content to the standby memory 13a (if the write content is address A and data a stored in the address A, the write control unit 13c writes the address A in the standby memory 13a. Write data a).

  [S22] While the temporarily stored content is written to the standby memory 13a, if the storage amount of the temporary storage unit 13c-1 is less than or equal to the threshold value (the threshold value is, for example, the accumulated amount for one access) The logical connection between the write control unit 13c and the standby memory 13a is disconnected.

[S23] When the CPU 11 performs a write access, the access is made to both the active memory 12a and the standby memory 13a.
Next, memory contention will be described. The access arbitration unit 12c arbitrates between the access from the CPUs 11-1 to 11-4 to the active memory 12a and the access from the data transfer unit 12b to the active memory 12a, but devise the active memory 12a. As a result, the contention can be further suppressed, and the copy operation while the CPU operation is continued can be more smoothly executed more reliably.

  For one, it can be realized by dividing the operational memory 12a into smaller blocks. That is, the CPU 11-1 to 11-4 and the data transfer unit 12b are arbitrated by dividing into small blocks, so that the address accessed from the CPU 11-1 to 11-4 and the address accessed by the data transfer unit 12b are different. The possibility increases, and the access between the CPUs 11-1 to 11-4 and the data transfer unit 12b can be performed simultaneously.

  If the area of the operational memory 12a is a very large area and is divided into fine blocks, the probability that the CPUs 11-1 to 11-4 and the data transfer unit 12b access the same area is very low. The CPUs 11-1 to 11-4 and the data transfer unit 12 b can simultaneously access the operational memory 12 a, and a more real-time memory copy operation is possible.

  As another method, the operational memory 12a may be a dual port memory element. The write operation from the CPUs 11-1 to 11-4 can be performed from one port, and the read operation of the data transfer unit 12b can be performed simultaneously from the other port.

  Next, the effect of the real-time memory copy operation realized by the communication device 10a will be described. In the communication device 10a, while data is being copied from the active memory 12a to the standby memory 13a, data is written from the CPUs 11-1 to 11-4 to the area of the active memory 12a that has already been copied. In such a case, the data is not sent again from the active memory 12a, but the contents are temporarily stored on the standby memory 13a side, and the standby memory 13a is later updated, so that real-time consistency is achieved. Guarantee.

  In the prior art (Japanese Patent Laid-Open No. 5-265789), a dedicated memory copy bus is simply provided for transfer. Therefore, if access from the CPU occurs continuously, the standby system memory can be used forever. Although there is a problem that copying to 13a does not end, in communication device 10a, in order to reflect write data generated during copying in standby memory 13a, transfer between devices mounted on the same printed circuit board Therefore (temporary storage unit 13c-1 → transfer to standby system memory 13a), it becomes the transfer in nano order which is the device operating speed, rather than writing data from CPU 11-1 to 11-4 to standby system memory 13a. Since data writing from the temporary storage unit 13c-1 to the standby memory 13a is much faster, the temporary storage unit 13c Reflected in the standby memory 13a 1 is a point very advantage to be completed quickly.

  On the other hand, access from the CPUs 11-1 to 11-4 to the temporary storage unit 13c-1 and data writing from the temporary storage unit 13c-1 to the standby memory 13a occur asynchronously. There is no guarantee that it will be empty.

  Therefore, the write control unit 13c provides a threshold value, and when the data is written from the temporary storage unit 13c-1 to the standby memory 13a, the accumulation amount of the temporary storage unit 13c-1 is the threshold. When the value is less than or equal to the value, the connection between the temporary storage unit 13c-1 and the common bus 14 and the connection between the temporary storage unit 13c-1 and the standby memory 13a are disconnected and are currently stored in the temporary storage unit 13c-1. All data is written to the standby memory 13a.

  Thereafter, when there is a write access from the CPUs 11-1 to 11-4, the data flows from the common bus 14 to the standby memory 13a. At the same time, the standby system memory control unit 13 incorporated is switched from the offline mode of copying to the switchable online mode, and shifts to the duplex operation.

  Next, the performance ratio between the prior art and the present invention will be described. 7 and 8 are diagrams for explaining the performance ratio. 7, the conventional device 200 includes CPUs # 1 to # 5, an active memory device 201, a standby memory device 202, and a bus arbitration unit 16, which are connected by a common bus B1.

  8, the communication device 10b according to the present invention includes CPUs # 1 to # 5, an active memory control unit 12, a standby memory control unit 13, and a bus arbitration unit 16, which are connected by a common bus B1 and operated. The system memory control unit 12 and the standby system memory control unit 13 are connected by a memory copy bus B2. The bus arbitration unit 16 arbitrates equally for the memory accesses of the CPUs # 1 to # 5 (round robin method).

  First, the processing capability will be described. In the conventional apparatus 200, it is necessary to access the active memory device 201 from a CPU dedicated to memory copy (referred to as CPU # 1), and the CPU # 1 that performs the memory copy process interrupts the original process. . Accordingly, the number of CPUs that can continue the original process during the memory copy process is reduced by one, and the process is performed by four.

  On the other hand, since the communication device 10b autonomously executes memory copy via the memory copy bus B2, since it is possible to continue processing with five devices even during memory copy, the processing capacity ratio as a system during memory copy 4 to 5 units, that is, 25%, the processing capacity is improved from the conventional one.

  Next, the memory copy time will be described. When the data transfer capabilities of the common bus B1 and the memory copy bus B2 are equal, in the conventional apparatus 200, a certain CPU performs memory copy using the common bus B1, so that it is shared with other CPUs to transfer copy data. The capacity is 1/5 of the transfer capacity of the common bus B1.

  On the other hand, in the communication device 10b, since the dedicated route of the memory copy bus B2 is used, the copy data transfer capability is the transfer capability of the memory copy bus B2 itself, which is five times the transfer capability compared to the conventional configuration. It can be seen that the time is shortened to 1/5.

  As described above, according to the present invention, even when a large amount of data is copied when the standby memory is incorporated, data can be copied at high speed without hindering access from the CPU to the operational memory. Therefore, while maintaining normal operation without degrading the performance of the system, the standby system memory can be quickly switched to a switchable online state, improving performance and reliability. It becomes possible to plan.

(Supplementary note 1) In a communication device having a memory redundancy structure of an active system and a standby system,
A plurality of communication units that perform distributed processing of communication control by connecting to a memory unit on the active system side and a memory unit on the standby system side via a common bus;
A memory copy bus that connects a memory unit on the active side and a memory unit on the standby side;
When recognizing that the active system memory for storing data and the memory unit on the standby system side are mounted, the data stored in the active system memory is read, and the data on the standby system side is read via the memory copy bus. An operation comprised of a data transfer unit for transferring to a memory unit, and an access arbitration unit for arbitrating access from the communication unit to the active memory and access from the data transfer unit to the active memory A system memory control unit;
A standby memory for storing data, a memory copy unit for writing the data transferred from the active memory control unit via the memory copy bus to the standby memory, and performing a memory copy, and a communication unit The write access to the active memory control unit is monitored, and when the memory copy to the standby system memory is being performed, if there is a write to an area that has already been copied, the common bus A standby memory control unit configured to temporarily store the write address and write data that appeared above, and after the memory copy is finished, the write control unit that writes the temporarily stored write content to the standby memory;
A communication apparatus comprising:

  (Additional remark 2) The said write-control part will stop a new temporary storage process, if the content memorize | stored temporarily will be below a threshold value while writing the content memorize | stored temporarily to the said standby | waiting-system memory. All the currently stored contents are written to the standby memory, and when there is a write access from the communication unit to the active memory control unit after the writing is completed, the standby memory is not temporarily stored. The communication device according to appendix 1, wherein the communication device is directly written to the communication device.

  (Supplementary Note 3) The data storage area of the operational memory is small so that contention between access from the communication unit to the operational memory and access from the data transfer unit to the operational memory is reduced. The communication device according to appendix 1, wherein the communication device is divided into blocks.

(Supplementary Note 4) In a memory device having both functions of an active system and a standby system and performing data storage processing,
When recognizing that an active memory for storing data and a memory unit on the standby system side are mounted, the data stored in the active memory is read and the memory unit on the active system side and the standby system side are read. From the data transfer unit that transfers the read data to the memory unit on the standby side via the memory copy bus that connects the memory unit, and the communication unit that performs communication control connected via the common bus to the active memory And an access arbitration unit that arbitrates between access to the operational memory from the data transfer unit, and an operational memory control unit that functions as an operational system when the system is mounted;
A standby memory for storing data, a memory copy unit for writing the data transferred from the active memory control unit via the memory copy bus to the standby memory, and performing a memory copy, and a communication unit The write access to the active memory control unit is monitored, and when the memory copy to the standby system memory is being performed, if there is a write to an area that has already been copied, the common bus A standby function that temporarily stores the write address and write data appearing above, and writes the temporarily stored content to the standby memory after the memory copy is completed, and functions as a standby system when the system is mounted. A system memory control unit;
A memory device comprising:

  (Additional remark 5) The said write-control part will stop a new temporary storage process, if the content temporarily stored becomes less than a threshold value while writing the content temporarily stored to the said standby | waiting-system memory. All the currently stored contents are written to the standby memory, and when there is a write access from the communication unit to the active memory control unit after the writing is completed, the standby memory is not temporarily stored. The memory device according to appendix 4, wherein the data is directly written to the memory.

  (Supplementary Note 6) The data storage area of the operational memory is fine so that contention between access from the communication unit to the operational memory and access from the data transfer unit to the operational memory is reduced. The memory device according to appendix 4, wherein the memory device is divided into blocks.

It is a principle figure of a communication apparatus. It is a figure which shows the structure of a communication apparatus. It is a figure which shows the flow of the memory copy operation | movement of a communication apparatus. It is a figure which shows the flow of the memory copy operation | movement of a communication apparatus. It is a figure which shows the flow of the memory copy operation | movement of a communication apparatus. It is a figure which shows a memory copy operation | movement sequence. It is a figure for demonstrating a performance ratio. It is a figure for demonstrating a performance ratio. It is a figure which shows the structure of an exchange system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Communication apparatus 11-1 to 11-n Communication part 12 Operation system memory control part 12a Operation system memory 12b Data transfer part 12c Access arbitration part 13 Standby system memory control part 13a Standby system memory 13b Memory copy part 13c Write control part 13c- 1 Temporary storage 14 Common bus 15 Memory copy bus

Claims (5)

In communication devices with active and standby memory redundancy structures,
A plurality of communication units that perform distributed processing of communication control by connecting to a memory unit on the active system side and a memory unit on the standby system side via a common bus;
A memory copy bus that connects a memory unit on the active side and a memory unit on the standby side;
When recognizing that the active system memory for storing data and the memory unit on the standby system side are mounted, the data stored in the active system memory is read, and the data on the standby system side is read via the memory copy bus. An operation comprised of a data transfer unit for transferring to a memory unit, and an access arbitration unit for arbitrating access from the communication unit to the active memory and access from the data transfer unit to the active memory A system memory control unit;
A standby memory for storing data, a memory copy unit for writing the data transferred from the active memory control unit via the memory copy bus to the standby memory, and performing a memory copy, and a communication unit The write access to the active memory control unit is monitored, and when the memory copy to the standby system memory is being performed, if there is a write to an area that has already been copied, the common bus A standby memory control unit configured to temporarily store the write address and write data that appeared above, and after the memory copy is finished, the write control unit that writes the temporarily stored write content to the standby memory;
A communication apparatus comprising:   When the content temporarily stored in the standby memory is being written to the threshold value or less when the content stored temporarily falls below a threshold value, the write control unit stops the new temporary storage processing and stores the current stored content. If the write access to the active memory control unit from the communication unit is made after completion of the writing, the content is written directly to the standby memory without being temporarily stored. The communication device according to claim 1.   The data storage area of the active memory is divided into fine blocks so that contention between access from the communication unit to the active memory and access from the data transfer unit to the active memory is reduced. The communication device according to claim 1, wherein: In a memory device that has both active and standby functions and performs data storage processing,
When recognizing that an active memory for storing data and a memory unit on the standby system side are mounted, the data stored in the active memory is read and the memory unit on the active system side and the standby system side are read. From the data transfer unit that transfers the read data to the memory unit on the standby side via the memory copy bus that connects the memory unit, and the communication unit that performs communication control connected via the common bus to the active memory And an access arbitration unit that arbitrates between access to the operational memory from the data transfer unit, and an operational memory control unit that functions when implemented in the system as an operational system,
A standby memory for storing data, a memory copy unit for writing the data transferred from the active memory control unit via the memory copy bus to the standby memory, and performing a memory copy, and a communication unit The write access to the active memory control unit is monitored, and when the memory copy to the standby system memory is being performed, if there is a write to an area that has already been copied, the common bus When the write address and write data that appear above are temporarily stored, and after the memory copy is completed, the write control unit that writes the temporarily stored write contents to the standby system memory is configured, and when the system is implemented as a standby system A functioning standby memory control unit;
A memory device comprising: When the content temporarily stored in the standby memory is being written to the threshold value or less when the content stored temporarily falls below a threshold value, the write control unit stops the new temporary storage processing and stores the current stored content. If the write access to the active memory control unit from the communication unit is made after completion of the writing, the content is written directly to the standby memory without being temporarily stored. The memory device according to claim 4.

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