JPH09305494A - Data transfer control circuit for extended storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a high-reliability extended storage device duplex by software without awareness and to eliminate the overhead of data transfer even when the extended storage device is made duplex. SOLUTION: A master data transfer mechanism 9 accesses a master extension storage device 11 by using the address obtained by adding the high-order address of an extension storage physical address from a master address converting circuit 7 and the low-order address of an extended storage logical address from a duplex address control unit 3 together to arbitrate data transfer between the master extended storage device 11 and a main storage 2. A slave data transfer mechanism 10 accesses a slave extended storage device 12 by using the address obtained by adding the high-order address of an extended storage physical address from a slave address converting circuit 8 and the low-order address of the extension storage logical address from the doubled address controller 3 to arbitrate data transfer between the slave extended storage device 12 and main storage 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control circuit for an extended storage device, and more particularly to dual control of an extended storage device by address conversion.

[0002]

2. Description of the Related Art Conventionally, an address control system of a data transfer control circuit of an extended storage device is disclosed in, for example, Japanese Patent Laid-Open No. 3-25614.
As shown in Japanese Patent Publication No. 7, an address conversion table for converting an extended storage logical address into one extended storage physical address has been used.

FIG. 4 is a block diagram showing an example of a data transfer control circuit of a conventional expansion storage device. The data transfer control circuit of this extended storage device is a CPU (Central).
Processing Unit) 41 and main memory 4
2, the data transfer circuit 43, the address conversion table 44 of the expansion storage device 45, the expansion storage device 45, the address conversion table 46 of the expansion storage device 47, and the expansion storage device 47.

An address conversion table 44 is prepared in the extended storage device 45 for address conversion. The software stores the extended storage logical address (E) in the address conversion table 44 for each physical address (EMUA) of the extended storage device 45.
AN) is set.

When data is transferred between the main memory 42 and the expansion memory device 45, the main memory address, EAN and transfer length are designated by software.

The CPU 41 has an address conversion table 44.
EA specified as a logical address entry
A place where N is equal is selected, and the EMUA of the entry of the corresponding physical address is read. The CPU 41 uses the EMUA, main memory address and transfer length to instruct the data transfer circuit 43 to transfer data between the main memory 42 and the extended memory device 45.

In addition, as a method of using the extended storage device,
A control program such as an operating system (OS) stores important data, etc., and it is often the case that the extended storage device is duplicated to manage data for high reliability.

An address conversion table 46 is prepared for the address conversion in the expansion storage device 47 for duplication of the expansion storage device 45. The software uses the address translation table 46 to store the physical address (EMU
An extended storage logical address (EAN) different from the address conversion table 44 is set for each A).

Extended storage device 4 duplicated from main storage 42
In the case of transferring the data to 5 and 47, the transfer instruction was issued twice by the software, and the same data was transferred to the extended storage device 45 and the extended storage device 47 in a divided manner to realize the duplication. .

[0010]

The first problem of the prior art is that when the expansion storage device is duplicated, an overhead occurs in data transfer between the main storage and the expansion storage device. The reason is that when data is transferred from the main memory to the extended storage device, the CPU issues a data transfer instruction twice and the data transfer from the main memory to the extended storage device is performed twice.

The second problem is that when the extended storage device is used in a duplicated manner, the software must be programmed in consideration of the duplicatedness. The reason is that in order to make two different extended storage areas look like one extended storage area, it is necessary to always create a program while paying attention to address double management and data transfer dualization.

An object of the present invention is to realize highly reliable extension of an extended storage device without the software being aware of it, to eliminate the overhead of data transfer even when the extension storage device is duplicated, and to improve characteristics and performance (high speed). To provide a data transfer control circuit for an extended storage device.

[0013]

A data transfer control circuit of an extended storage device according to the present invention comprises means for converting one extended storage logical address into two extended storage physical addresses and two extended storage physical address locations. And means for simultaneously transferring data while synchronizing with the transfer of data from the main memory.

Further, the data transfer control circuit of the extended storage device of the present invention has fault information of the extended storage device, and has means for selecting a normal extended storage device for data transfer at the time of data transfer.

Further, the data transfer control circuit of the extended storage device of the present invention has means for changing whether the extended storage device is used in duplicate or as two extended storage devices.

Furthermore, the data transfer control circuit of the extended storage device of the present invention includes a master extended storage device including a master address conversion circuit and a master data transfer mechanism, and a slave extended storage device including a slave address conversion circuit and a slave data transfer mechanism. A master address having a device and an address conversion table for performing address conversion from an upper address of the extended storage logical address to an upper address of the extended storage physical address, and passing the upper address of the extended storage physical address to the master data transfer mechanism. The slave having a conversion circuit and an address conversion table for performing address conversion from an upper address of the extended storage logical address to an upper address of the extended storage physical address, and passing the upper address of the extended storage physical address to the slave data transfer mechanism. address The master extended storage device is accessed by using a replacement circuit and an address obtained by adding the upper address of the extended storage physical address given by the master address conversion circuit and the lower address of the extended storage logical address given by the dual address control device. A master data transfer mechanism for arbitrating data transfer between the master extended storage device and the main storage, an upper address of an extended storage physical address given from the slave address conversion circuit, and an extended storage given from the dual address control device. A slave data transfer mechanism for accessing the slave extended storage device by using an address obtained by adding a lower address of a logical address to arbitrate data transfer between the slave extended storage device and a main storage; and the master address conversion circuit. And the slave address conversion times To the master data transfer mechanism and the slave data transfer mechanism, the lower address of the extended storage logical address, the main storage address and the transfer length, and the dual address control device for issuing the data transfer instruction. Have.

Further, the data transfer control circuit of the extended storage device according to the present invention notifies the dual address control device of a failure when the master data transfer mechanism fails in the master extended storage device, and the slave data transfer device When a failure occurs in the slave extended storage device, the transfer mechanism notifies the dual address control device of the failure, and the dual address control device selects a normal extended storage device for data transfer and transfers the data.

Further, the data transfer control circuit of the extended storage device of the present invention is a logical address for setting an address for converting the extended storage logical address to the extended storage physical address in the master address conversion circuit and the slave address conversion circuit. The logical address setting means and the dual address control are used to determine whether the setting means, the master extended storage device and the slave extended storage device are duplicated and used as substantially one extended storage device or as independent extended storage devices. And a duplexing selection switch that communicates with the device.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data transfer control circuit of an extended storage device according to an embodiment of the present invention. The data transfer control circuit of the extended storage device according to the present embodiment includes a CPU 1, a main memory 2, a redundant address control device 3, a logical address setting means 5, a redundant selection switch 6, and a master address conversion circuit 7. A slave address conversion circuit 8, a master data transfer mechanism 9, a slave data transfer mechanism 10, and a master extended storage device 11.
And the slave extended storage device 12 constitute a main part thereof.

The master extension storage device 11 includes a master address conversion circuit 7 and a master data transfer mechanism 9, and the slave extension storage device 12 includes a slave address conversion circuit 8 and a slave data transfer mechanism 10.

The duplication selection switch 6 determines whether the master extended storage device 11 and the slave extended storage device 12 are duplicated and used as substantially one extended storage device or as independent extended storage devices. Information is transmitted to the logical address setting means 5 and the duplicated address control device 3.

The logical address setting means 5 sets an address for converting the extended storage logical address into the extended storage physical address in the master address conversion circuit 7 and the slave address conversion circuit 8.

At the time of data transfer between the main memory 2 and the extended storage device, the CPU 1 informs the dual address control device 3 of the extended storage logical address, the main storage address and the transfer length, and the data transfer instruction.

The duplicated address control device 3 has fault information 4 of the extended storage device and duplicated information 13 which is the information of the duplicated selection switch 6, and the two pieces of information and the upper address of the extended storage logical address are stored. An address translation instruction is issued to the master address translation circuit 7 and the slave address translation circuit 8, and the lower address of the extended storage logical address, the main storage address and the transfer length are sent to the master data transfer mechanism 9 and the slave data transfer mechanism 10. , Issue data transfer instructions.

The master address conversion circuit 7 and the slave address conversion circuit 8 have an address conversion table for performing address conversion from the upper address of the extended storage logical address to the upper address of the extended storage physical address, and the obtained extended storage physical address is obtained. The upper address of the address is passed to the master data transfer mechanism 9 and the slave data transfer mechanism 10, respectively.

The address conversion table of the master address conversion circuit 7 uses the upper address EA of the extended storage logical address.
It is shown that the address is converted to the start address EMUA20 of the storage area EMUB30 in the master extended storage device 11 as a higher address of the extended storage physical address with respect to N0, and EAN1 is changed to EMUA21 for other addresses as well.
EAN2 is converted into EMUA22, and EAN3 is converted into EMUA23.

The address conversion table of the slave address conversion circuit 8 is the upper address E of the extended storage logical address.
A storage area EMUB5 in the slave extended storage device 12 as an upper address of the extended storage physical address with respect to AN0.
It is shown that the leading address EMUA40 of 0 is converted, and EAN1 becomes EMUA41 for other addresses as well.
EAN2 is converted into EMUA42, and EAN3 is converted into EMUA43.

The master data transfer mechanism 9 and the slave data transfer mechanism 10 respectively have a higher address of the extended storage physical address given from the master address conversion circuit 7 and the slave address conversion circuit 8 and an extended storage logic provided from the duplicated address controller 3. The master extended storage device 11 and the slave extended storage device 12 are accessed using an address obtained by adding the lower address of the address,
It arbitrates the data transfer between each extended storage device and the main storage 2. When a failure occurs in the master extended storage device 11 and the slave extended storage device 12, the master data transfer mechanism 9 and the slave data transfer mechanism 10 are
Failure information 4 is notified to the duplicated address control device 3.

Referring to FIG. 2, the control flow when the duplicated address control device 3 transfers data from the main memory 2 to the extended storage device is the duplicated selection switch-on determination step 200 and the extended storage device failure determination step 201.
An abnormal end notification step 202, a logical address setting completion determination step 203, and an abnormal end notification step 20
4, the extended storage device single system failure determination step 205, the physical address translation and data transfer instruction output step 20
6, a physical address conversion and data transfer instruction output step 207, and a logical address setting completion determination step 20
8, an abnormal end notification step 209, a logical address setting extended storage device failure status determination step 210, an abnormal end notification step 211, and a physical address translation and data transfer instruction output step 212.

Referring to FIG. 3, the control flow when the duplicated address controller 3 transfers data from the extended storage device to the main memory 2 is as follows: a duplicated selection switch-on determination step 300 and an extended storage device failure determination step 301.
Abnormal termination notification step 302, logical address setting completion determination step 303, abnormal termination notification step 30
4, the extended storage device single system failure determination step 305, the physical address translation and data transfer instruction output step 30
6, physical address conversion and data transfer instruction output step 307, and logical address setting completion determination step 30
8, an abnormal end notification step 309, a logical address setting expanded storage device failure status determination step 310, an abnormal end notification step 311, and a physical address translation and data transfer instruction output step 312.

Next, the operation of the data transfer control circuit of the extended storage device according to the present embodiment configured as described above will be described.

(1) Setting of the duplex selection switch 6

The redundancy selection switch 6 is set by the hardware or software at the time of startup to determine the control method of the master extended storage device 11 and the slave extended storage device 12. When the duplication selection switch 6 is turned on, the master extended storage device 11 and the slave extended storage device 12 are duplicated so that one extended storage logical address can access two extended storage physical addresses. When the duplication selection switch 6 is off, one extended storage logical address can be used to access one extended storage physical address as before.

(2) Setting of address conversion circuit

The software allocates a logical address to a higher address of the extended storage physical address for each storage area of the extended storage device before transferring data to the extended storage device.

When the duplication selection switch 6 is turned on, the logical address setting means 5 uses the upper address of one extended storage logical address and the upper address of two extended storage physical addresses provided by the software as the master address conversion circuit 7 And the slave address conversion circuit 8 is simultaneously set.

The storage area EMUB30 of the master extended storage device 11 and the slave extended storage device 1 are controlled by software.
When address allocation is performed with the upper address EAN0 of the same extended storage logical address as the second extended storage area EMUB50, the upper address EAN0 is assigned to the logical address entry of the master address conversion circuit 7, and the storage area is assigned to the corresponding physical address entry. The start address EMUA20 of the EMUB30 is set, and the slave address conversion circuit 8
The upper address EAN0 is included in the logical address entry of
However, the entry of the corresponding physical address has a storage area EM
The start address EMUA40 of the UB50 is set.

When the duplication selection switch 6 is off, the logical address setting means 5 uses the upper address of one extended storage logical address and the upper address of one extended storage physical address provided by the software as the master address conversion circuit 7 And the slave address conversion circuit 8 are set separately.

When the storage area EMUB30 of the master extended storage device 11 is assigned by the software at the higher address EAN0 of the extended storage logical address,
The higher address EAN0 is set in the entry of the logical address of the master address conversion circuit 7, and the start address EMUA20 of the storage area EMUB30 is set in the corresponding physical address entry.

Storage area EM of slave extended storage device 12
When addressing the UB 50 with the extended storage logical address, the storage area EMUB of the master extended storage device 11
It must be set at a higher logical address different from 30.

(3) Data transfer from main memory 2 to expansion memory

When the software transfers data from the main memory 2 to the extended storage device, the CPU 1 sends the extended storage logical address, the main storage address and the transfer length to the duplicated address control device 3, and the main storage 2 to the extended storage device. And give data transfer instructions to.

The duplicated address control device 3 includes the duplicated information 13, which is the state of the above-mentioned duplicated selection switch 6, the master data transfer mechanism 9 and the slave data transfer mechanism 10.
Has fault information 4 of a fault detected during data transfer,
Based on these information, the control shown in FIG. 2 is performed.

First, the duplex address control device 3 determines whether the duplex selection switch 6 is on or off based on the duplex information 13 (step 200).

If the duplication selection switch 6 is turned on, the duplication address control device 3 determines whether or not both the master extended storage device 11 and the slave extended storage device 12 are in the fault state based on the fault information 4 (step 201). . When both the master extended storage device 11 and the slave extended storage device 12 are in a failure state, the duplicated address control device 3 returns an abnormal reply to the CPU 1 because the data transfer is impossible, notifies the software of the abnormal condition, and terminates ( Step 202).

If at least one of the master extended storage device 11 and the slave extended storage device 12 is not in a failure state, the dual address control device 3 determines whether the upper address of the given extended storage logical address is set by the address conversion circuit. It is determined (step 203). If not set, the redundant address control device 3
Since the extension storage physical address cannot be converted, an abnormal reply is returned to the CPU 1, the software is notified of the abnormality, and the process ends (step 204).

If the upper address of the given extended storage logical address is set in the address conversion circuit, the duplicated address control device 3 judges whether or not the one-sided extended storage device is in the fault state (step 205). When one of the extended storage devices is in a failure state, the normal address of the extended storage is specified by instructing the address conversion circuit on the normal extended storage device side to convert the extended storage physical address to the upper address of the extended storage logical address. The lower address of the extended storage logical address, the main storage address and the transfer length and the data transfer instruction from the main storage 2 to the extended storage device are issued to the data transfer mechanism on the device side (step 206).

If both systems are normal, the dual address control device 3 instructs the master address conversion circuit 7 and the slave address conversion circuit 8 to convert the extended storage logical address to the higher address of the extended storage physical address. Then, the lower address of the extended storage logical address, the main storage address and the transfer length, and the dual data transfer instruction from the main storage 2 to the extended storage device are issued to the master data transfer mechanism 9 and the slave data transfer mechanism 10 ( Step 207).

On the other hand, if the duplication selection switch 6 is off, the duplication address control device 3 determines whether or not the upper address of the supplied extended storage logical address is set by the address conversion circuit (step 208). If not set, the redundant address control device 3
Since the extension storage physical address cannot be converted, an abnormal reply is returned to the CPU 1, the software is notified of the abnormality, and the process ends (step 209).

If the upper address of the supplied extended storage logical address is set by the address conversion circuit, the dual address control device 3 sets the upper address of the supplied extended storage logical address by the address conversion circuit. It is determined whether or not the extended storage device is in a failure state (step 210). In the case of a failure state, since data transfer is impossible, an abnormal reply is returned to the CPU 1, the software is notified of the abnormality, and the processing ends (step 211). ).

If the extended storage device whose upper address of the given extended storage logical address is set in the address conversion circuit is not in the fault state, the dual address control device 3
Indicates to the address conversion circuit on the side of the extended storage device, in which the upper address of the given extended storage logical address is set, the conversion of the extended storage physical address to the upper address with the higher address of the extended storage logical address. The lower address of the extended storage logical address, the main storage address and the transfer length, and the data transfer instruction from the main storage 2 to the extended storage device are issued to the data transfer mechanism on the side of the extended storage device (step 212).

When the master data transfer mechanism 9 and the slave data transfer mechanism 10 receive the lower address of the extended storage logical address, the main storage address and the transfer length, and the dual data transfer instruction from the dual address control device 3, respectively. An upper address of the extended storage physical address is received from each of the corresponding master address conversion circuit 7 and slave address conversion circuit 8, and an address obtained by adding the upper address of each extended storage physical address and the lower address of the extended storage logical address is extended storage As an access address, data transfer is simultaneously performed while synchronizing with a given transfer length from a given address in the main memory 2.

When the master data transfer mechanism 9 and the slave data transfer mechanism 10 receive the lower address of the extended storage logical address, the main storage address and the transfer length, and the normal data transfer instruction from the duplicated address control device 3, respectively. An upper address of the extended storage physical address is received from the corresponding address conversion circuit, and an address obtained by adding the upper address of each extended storage physical address and the lower address of the extended storage logical address is used as an access address of the extended storage device as the main storage. Data transfer is independently executed from the given address of 2 by the given transfer length.

When a failure occurs in the master extended storage device 11 or the slave extended storage device 12 during data transfer, the master data transfer mechanism 9 or the slave data transfer mechanism 10 notifies the duplicated address control device 3 of the failure. Then, the fault information 4 is updated.

When the duplication selection switch 6 is turned on and the one-sided extended storage device has a failure, the duplication address control device 3 makes the software appear to have normally terminated. If the redundant selection switch 6 is on and both of the extended storage devices have failed during data transfer, and if the redundant selection switch 6 is off, the redundant address control device 3
Notifies the software of the abnormal termination.

(4) Data transfer from the expanded storage device to the main memory 2

When the software transfers data from the extended storage device to the main memory 2, the CPU 1 sends the extended storage logical address, the main storage address and the transfer length to the duplicated address control device 3, and the extended storage device to the main storage 2. And give data transfer instructions to.

The duplicated address control device 3 includes the duplicated information 13, which is the state of the duplicated selection switch 6, the master data transfer mechanism 9 and the slave data transfer mechanism 10.
Has fault information 4 of a fault detected during data transfer,
Based on these information, the control shown in FIG. 3 is performed.

First, the duplicated address control device 3 determines whether the duplicated selection switch 6 is on or off based on the duplicated information 13 (step 300).

If the duplication selection switch 6 is turned on, the duplication address control device 3 determines whether or not both the master extended storage device 11 and the slave extended storage device 12 are in the fault state based on the fault information 4 (step 301). . When both the master extended storage device 11 and the slave extended storage device 12 are in a failure state, the duplicated address control device 3 returns an abnormal reply to the CPU 1 because the data transfer is impossible, notifies the software of the abnormal condition, and terminates ( Step 302).

If at least one of the master extended storage device 11 and the slave extended storage device 12 is not in a failure state, the dual address control device 3 determines whether the upper address of the given extended storage logical address is set by the address conversion circuit. It is determined (step 303). If not set, the redundant address control device 3
Since the extension storage physical address cannot be converted, an abnormal reply is returned to the CPU 1, the abnormality is notified to the software, and the process ends (step 304).

If the upper address of the given extended storage logical address is set in the address conversion circuit, the duplicated address control device 3 determines whether or not one of the extended storage devices is in the fault state (step 305). When one of the extended storage devices is in a failure state, the normal address of the extended storage is specified by instructing the address conversion circuit on the normal extended storage device side to convert the extended storage physical address to the upper address of the extended storage logical address. The lower address of the extended storage logical address, the main storage address and the transfer length, and the data transfer instruction from the extended storage device to the main storage 2 are issued to the data transfer mechanism on the device side (step 306).

When both systems are normal, the duplicated address control device 3 uses the higher address of the extended storage logical address in the extended storage physical address in the address conversion circuit of either the master extended storage device 11 or the slave extended storage device 12. An address conversion instruction is issued to the corresponding data transfer mechanism, and a lower address of the extended storage logical address, a main storage address and a transfer length, and a data transfer instruction from the extended storage device to the main storage 2 are issued. (Step 307).

On the other hand, if the duplication selection switch 6 is off, the duplication address control device 3 determines whether or not the upper address of the supplied extended storage logical address is set by the address conversion circuit (step 308). If not set, the redundant address control device 3
Since the extension storage physical address cannot be converted, an abnormal reply is returned to the CPU 1, the abnormality is notified to the software, and the process ends (step 309).

If the upper address of the supplied extended storage logical address is set by the address conversion circuit, the dual address control device 3 sets the upper address of the supplied extended storage logical address by the address conversion circuit. It is determined whether or not the expansion storage device is in the failure state (step 310). In the case of the failure state, since data transfer is impossible, an abnormal reply is returned to the CPU 1, and the software is notified of the abnormality and the processing ends (step 311). ).

If the extended storage device in which the higher address of the given extended storage logical address is set in the address conversion circuit is not in the fault state, the dual address control device 3
Indicates to the address conversion circuit on the side of the extended storage device, in which the upper address of the given extended storage logical address is set, the conversion of the extended storage physical address to the upper address with the higher address of the extended storage logical address. The lower address of the extended storage logical address, the main storage address and the transfer length, and the data transfer instruction from the extended storage to the main storage 2 are issued to the data transfer mechanism on the side of the extended storage (step 312).

When the master data transfer mechanism 9 and the slave data transfer mechanism 10 receive the lower address of the extended storage logical address, the main storage address and the transfer length, and the normal data transfer instruction from the dual address control device 3, respectively. An upper address of the extended storage physical address is received from the corresponding address conversion circuit, and an address obtained by adding the upper address of each extended storage physical address and the lower address of the extended storage logical address is used as an access address of the extended storage device as the main storage. Data transfer is independently executed from the given address of 2 by the given transfer length.

When a failure occurs in the master extended storage device 11 or the slave extended storage device 12 during data transfer, the master data transfer mechanism 9 and the slave data transfer mechanism 10 notify the duplicated address control device 3 of the failure. Then, the fault information 4 is updated.

After that, when the duplication selection switch 6 is turned on and the one-sided extended storage device fails, the duplicated address control device 3 operates in the other normal extended storage device, so that the faulty one does not occur. Retry the address conversion circuit and the data transfer mechanism. When the duplication selection switch 6 is on and both expansion storage devices have failed, and when the duplication selection switch 6 is off, the duplication address control device 3 notifies the software of abnormal termination.

[0071]

As described above, the first effect of the present invention is to realize high-speed data transfer from the main memory to the extended storage device when the extended storage device is duplicated. The reason is to have a means for converting one extended storage logical address into two extended storage physical addresses, and to simultaneously transfer data while transferring data from the main storage to two extended storage physical address locations. By having a means for transferring the data, it is possible to shorten the transfer time because the data transfer need only be performed twice for the data transfer.

The second effect is that a highly reliable extended storage device can be easily used. The reason is,
In order to make two different extended storage areas look like one extended storage area, conventionally, programming must be performed with consideration of address double management, double data transfer, and processing when one of the extended storage devices fails. This is because, according to the present invention, it is only necessary to access one extended storage device without being aware of duplication, and a highly reliable duplicated extension storage device can be easily realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer circuit of an extension storage device according to an embodiment of the present invention.

FIG. 2 is a control flow when the dual address control device in FIG. 1 transfers data from a main memory to an extended storage device.

FIG. 3 is a control flow when the dual address control device in FIG. 1 transfers data from an extended storage device to a main memory.

FIG. 4 is a block diagram showing an example of a data transfer control circuit of a conventional extended storage device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main memory 3 Duplication address control device 4 Fault information 5 Logical address setting means 6 Duplication selection switch 7 Master address conversion circuit 8 Slave address conversion circuit 9 Master data transfer mechanism 10 Slave data transfer mechanism 11 Master expansion storage device 12 Slave expansion Storage device 13 Redundant information

Claims (6)

[Claims] 1. A means for converting from one extended storage logical address into two extended storage physical addresses, and simultaneously transferring data in synchronization with the transfer of data from the main storage to the two extended storage physical address locations. And a data transfer control circuit for an extension storage device. 2. The data of the extended storage device according to claim 1, further comprising means for holding fault information of the extended storage device and selecting a normal extended storage device for data transfer at the time of data transfer. Transfer control circuit. 3. A data transfer control circuit for an extended storage device according to claim 1, further comprising means for changing whether to use the extended storage device in a duplicated manner or as two extended storage devices. . 4. A master extended storage device including a master address conversion circuit and a master data transfer mechanism, a slave extended storage device including a slave address conversion circuit and a slave data transfer mechanism, and an extended storage physical address from an upper address of an extended storage logical address. An address conversion table for performing address conversion to an upper address of an address, the master address conversion circuit that transfers the upper address of an extended storage physical address to the master data transfer mechanism, and an extended storage from an upper address of an extended storage logical address It is provided from the slave address conversion circuit that has an address conversion table for performing address conversion to the higher address of the physical address, and passes the higher address of the extended storage physical address to the slave data transfer mechanism, and the master address conversion circuit. Between the master extended storage device and the main storage by accessing the master extended storage device using an address obtained by adding the upper address of the extended storage physical address and the lower address of the extended storage logical address given from the dual address control device. A master data transfer mechanism that arbitrates the data transfer, and an address obtained by adding the upper address of the extended storage physical address given by the slave address conversion circuit and the lower address of the extended storage logical address given by the dual address controller. A slave data transfer mechanism for accessing the slave extended storage device to arbitrate data transfer between the slave extended storage device and the main memory; and an address translation instruction to the master address translation circuit and the slave address translation circuit. The master data transfer Mechanism and the slave data transfer mechanism having a lower address of an extended storage logical address, a main storage address and a transfer length, and the dual address control device for issuing a data transfer instruction. circuit. 5. The master data transfer mechanism notifies the dual address control device of a failure when a failure occurs in the master extended storage device, and the slave data transfer mechanism fails in the slave extended storage device. 5. The data transfer control circuit for an extended storage device according to claim 4, wherein a notification is given to the dual address control device of a failure, and the dual address control device selects a normal extended storage device for data transfer when data is transferred. 6. A logical address setting means for setting an address for converting an extended storage logical address to an extended storage physical address in the master address conversion circuit and the slave address conversion circuit, the master extension storage device and the slave extension. 5. A duplication selection switch for transmitting to the logical address setting means and the duplication address control device whether the storage device is duplicated and used as substantially one extension storage device or each independent extension storage device. Transfer control circuit of the extended storage device.