JPH07244634A - External storage control unit and bus switching control method - Google Patents

Abstract

PURPOSE:To improve the performance and to reduce the cost of a storage system by providing both a bus for data transfer and a bus for control informa tion transfer together in the storage system and obtaining bus constitution which is most suitable to the access pattern of a host computer with an indica tion made of a maintainance personnel, etc. CONSTITUTION:This device has buses (a), (b), and (c) which perform data transfer between a channel adapter CHA3 and a disk adapter DKA5, and a cache memory 2 and a common memory 6. The bus (a) is a bus for data transfer which is connected to the cache memory 2, the bus (c) is a bus for control information transfer which is connected to the common memory 6, and the bus (b) is a bus connected to the both and can transfer both the signals. The purposes of use of the bus (b) can be switched based on the switching indication irrelevantly to whether or not the storage system is in operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage system in an information processing device, and more particularly to a bus switching method in an external storage control device.

[0002]

2. Description of the Related Art In recent years, a multiprocessor architecture has been actively adopted for the purpose of high performance and high reliability of storage devices. In this case, by using a plurality of common buses, not only the system function can be highly expanded but also the reliability can be improved. For example, FUJITSU 42,1, pp12-20 (19
The file control device described in 91) divides the function exercised by the control device into a plurality of modules, arranges a microprocessor in each module, and realizes mutual communication through a common bus.

[0003]

Generally, when a data signal and a control signal in a certain storage control device are transferred by only one common bus, control signals are exchanged by other modules while a large amount of data is transferred. Will be delayed.
On the contrary, if the data transfer and the control signal transfer are completely separated and performed by different bus systems, hardware that meets the peak capacity of the required performance of each is required. In general, the number of control signals issued is relatively reduced when sequential access is performed with a large amount of data transfer, and conversely the total amount of transferred data is often reduced during random access in which commands occur frequently. , Even if one of the bus systems operates at the limit performance, the other bus system becomes empty.

Although the techniques described in the above-mentioned conventional documents multiplex each module and a common bus as a countermeasure against a failure, they do not solve the problem of the bus configuration due to the difference in the purpose of using the bus.

In view of the above problems, the present invention is capable of switching buses according to an instruction and dynamically changing a bus configuration most suitable for an access pattern of a host computer even while the apparatus is in operation. An apparatus and a bus switching method are provided.

[0006]

In order to achieve the above object, a bus switching control method according to the present invention comprises a first storage device for storing data, a second storage device for storing control information, and In a storage system having three or more sets of buses for accessing the first and second storage devices, at least one set of the three or more sets of transfer buses is used for either data transfer or control information transfer Structure, and whether or not the storage system is in operation,
The at least one set of transfer buses is switched to be used for any one of the applications based on a switching instruction.

In this method, when the use of the at least one set of buses is switched during the operation of the storage system, the use of the at least one set of buses is prohibited until the processing for the switching is completed. It is desirable to be able to continue using other buses.

An external storage control device according to the present invention is connected to an external storage device, a cache memory for temporarily storing input / output data to / from the external storage device, and the second and third buses, and at least the external storage device. A shared memory for storing control information including management information of data stored in the cache memory; channel adapter means for controlling transfer of data between the host device and the cache memory using contents of the shared memory; A disk adapter means for controlling the transfer of data between the external storage device and the cache memory using the contents of the shared memory; and the channel adapter means, the disk adapter means, and the cache memory, which are connected to each other. 1 bus, the channel adapter means, the disk adapter means, the cache memory , And a second bus interconnecting the shared memory, and a third bus interconnecting the disk adapter means, the channel adapter means, and the shared memory, the channel adapter means and the disk The adapter means is characterized in that the second bus is selectively used by switching between the cache memory access and the shared memory access.

In this device, the second bus is used for the cache memory access during the sequential access in which the data transfer amount is larger than the control information transfer amount or in the frequent use thereof, and conversely, the second bus is used as the shared memory. It is preferable to use for access at the time of random access in which the transfer amount of control information is larger than the transfer amount of data or at the time of heavy use thereof.

Each of the first to third buses is provided with an arbiter that arbitrates when the bus usage right requests from a plurality of adapter means conflict.

The instruction to switch the usage of the second bus is issued by monitoring the operating information of the storage system from an external input means, or by monitoring the operating information of the storage system main body and determining the obtained value. It can be automatically performed by making a determination such as a value determination.

The second bus may operate on behalf of the first or third bus even if the first or third bus is unavailable due to a failure or other causes.

[0013]

The present invention enables a plurality of transfer buses to be selectively used for data transfer or control information transfer in a storage system. For example, from monitoring and predicting the access pattern of the host computer,
It is possible to switch to a bus configuration with a high data transfer capacity when the access data amount is large, and to a configuration with a large number of control information transfer buses when performing multiple operations in parallel, reducing the total number of buses and reducing costs. It is effective in realizing the performance improvement by maximizing the transfer capability of the bus.

That is, rather than providing the data access bus and the control bus completely separately, at least one set of buses can be switched and used for both purposes. For example, random access with high multiplicity can be used. In this case, even if the load on the control bus is large and the access data amount is small, bus resources can be effectively used by switching the bus configuration.

At the time of switching the bus configuration, the transfer method is changed so as to operate on the remaining buses without issuing a new transfer instruction for the corresponding buses, and the hardware for switching is set for the buses to be switched. Switch the software from. By providing a transitional degenerate state in the switching process, it is not necessary to suspend the operation of the entire system during the bus switching operation. That is,
Without interrupting the access request from the host device,
Since the above-mentioned bus switching can be realized, it can be used in a non-stop system.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a storage system to which the present invention is applied. An ESCON (Enterprise System CONnection) cable connection system 1 connected to a host computer (not shown), a cache memory 2 also serving as a buffer for temporarily storing input / output data, between the host side and the cache memory 2 respectively. Multiple CHA (C) that are adapters with a processor (CPU) to control data transfer
Hanel Adapter) 3, disk array 4 which is an external storage device, a plurality of DKA (Disk Adapter) 5 which is an adapter with a processor for controlling data transfer between the cache memory 2 and the disk array 4, and management of the cache memory 2 The shared memory 6 stores control information including directory information and communication information between processors of each CHA 3 and DKA 5, and a bus system 7 for accessing the cache memory 2 or the shared memory 6 from each CHA 3 and DKA 5. The bus system 7 is composed of three buses that can operate independently in this embodiment.

FIG. 2 shows the details of the main part of FIG. 1 centering on the bus system 7. The three systems of the bus system 7 are referred to as a bus a, a bus b, and a bus c, respectively, here. Three buses a,
Both b and c are connected to each CHA3 and each DKA5. Further, the bus a and the bus b are the cache memory 2
(The control unit 21 thereof), and the buses b and c are connected to (the control unit 61) of the shared memory 6. Therefore, read / write access to the cache memory 2 is possible from any processor via the bus a or bus b, and read / write to the shared memory 6 is possible via the bus b or bus c. That is, the bus a is used exclusively for accessing the cache memory 2, and the bus c
Is used exclusively for accessing the shared memory 6, whereas
The bus b can be used by switching to both accesses. The functions of the CHA 3 are roughly divided into a host connection system control unit, a cache memory control unit, and a shared memory control unit, and the CPU 31 controls these. CHA
3 has bus adapters BSAa and BSAb corresponding to the buses a, b and c, respectively, and a shared memory port SMP. BSAa belongs to the cache memory control unit, SM
P belongs to the shared memory controller and BSAb belongs to both controllers. The functions of the DKA 5 are roughly classified into a disk connection system control unit, a cache memory control unit, and a shared memory control unit, and the CPU 51 manages these controls. DKA5
Also a bus adapter B for each of buses a, b, and c
It has SAa, BSAb, and SMP. BSAa belongs to the cache memory controller, SMP belongs to the shared memory controller, and BSAb belongs to both controllers. Both BSAs and SMPs have a requestor 75 requesting the right to use the corresponding bus.

In addition to the input / output bus lines 71 (71a, 71b, 71c) for transferring data and the like, each system has a request line 72 (72a, 72b, 72c) and a grant ID line 73 (73a, 73b). , 73c), and hardware called a bus arbiter 74 (74a, 74b, 74c) for arbitrating bus access rights. Each arbiter 74 is connected to the requesters 75 in all CHA3 and DKA5 through two signal lines, receives a plurality of bus usage right requests, and determines the priority order of bus usage. The bus a, the bus b, and the bus c have arbiters 74a, 74b, and 74c respectively, but the bus a and the bus b can be collectively arbitrated and managed by the same arbiter 74a as one resource.

The shared memory 6 includes management directory information of the cache memory 2 (hierarchical table for searching cache segments and status of each segment), and inter-processor communication messages of each CHA 3 and DKA 5 (inter-processor). Communication information for cooperation, synchronization, etc.), switching statistical information, system configuration information (CHA, DKA mounting status, blocked status, system configuration common information, cache memory 2 capacity, disk array disk) (Including number).

In FIG. 6, each of CHA3 and DKA5,
That is, the internal structure common to the adapter with a processor is shown. Each processor adapter is BSAa, BSAb
And including SMP is as described above. BSA
a is a buffer 77 for temporarily storing transfer data, I / F control units 78 and 79 for controlling interfaces with the internal CPU and the bus, a requester 80 for issuing a bus use right request, and a mode switching mode described later. Has an internal register 76 for setting. BSAb is
It has the same configuration as BSAa. The configuration of the SMP is the same, but the internal register 76 for mode switching is unnecessary and is not incorporated.

The BSA has the following mode setting function.

(1) Setting of Sequential Mode In this mode, the requester of BSAa or BSAb is set.
Use only one of the requesters. However, always use a requester that belongs to the same bus system as the enabled arbiter. If the sequential mode is set, the bus system a and the bus system b are managed together as one resource, and the usage right can be secured in both bus systems at the same time by one request.

When setting the sequential mode,
Furthermore, depending on the software settings, the following three bus modes can be used.

(I) Two-bus mode: Simultaneous transfer by bus a and bus b (128-bit transfer) (ii) System transfer by only bus a (64-bit transfer) when bus b fails (iii) Bus a failure At times, etc., system transfer using only bus b (64-bit transfer) (2) Setting of transaction mode In this mode, both the requester of BSAa and the requester of BSAb are valid. When switching the bus b for shared memory access (32-bit transfer) for random access, the bus a and the bus b work differently, so it is necessary to switch both BSAs to the transaction mode. In this case, the buses a and b are managed as separate resources.

Next, SMP will be described. As described above, the SMP is hardware connected to the bus c in each adapter. The bus c is an independent resource that is always used for control information access (32-bit transfer), and does not use mode switching as in BSA.

Now, a specific procedure for actual transfer in response to a bus request will be described below.

An adapter (CHA
3 or DKA 5) is the applicable request line 72 first.
To output the bus request to the corresponding bus arbiter 74. At this time, if a plurality of requests conflict with each other, the arbiter 74 outputs the ID number of the adapter with the highest priority to the grant ID line 72 according to a predetermined priority determination algorithm, and at this time, outputs its own ID number. The confirmed processor gets the right to use the bus. When the right to use the bus is obtained, if it is a write to the cache memory 2 or the shared memory 4, the address, command and data are output on the transfer bus in time series, and the operation is performed by receiving the error phase (transfer completion status). finish. In the case of reading to the cache memory 2 or the shared memory 4, the address and command are output, and the read data and the error phase (transfer completion status) sent are received. The memory control unit 21 or 61
When an error is detected by, the information is transferred in the error phase.

Next, a data transfer processing procedure will be briefly described by taking as an example the case where the stored data is read from the disk array 4 of the present embodiment and transferred to the host computer.

One CH receiving a read command from the host
A3 first accesses the cache management information in the shared memory 6 to determine whether or not the data to be read exists in the cache memory 2, and if the data is already loaded in the cache memory 2, the data is read. Is directly transferred to the upper level. If the corresponding data is not in the cache memory 2, inter-processor communication using the shared memory 6 requests the DKA 5 to read from the disk array 4. The DKA 5 receiving this request calculates which part of the disk array 4 the read data is in,
The relevant data is transferred to the cache memory 2. that time,
After transferring data for each fixed block length, the shared memory 6
The upper management information area is accessed to indicate that the corresponding data block has been established in the cache memory 2. Simultaneously with the data transfer between the disk array 4 and the cache memory 2, the CHA 3 polls the shared memory 6 and transfers the established data block from the cache memory 2 to the upper channel connection system 1.

As described above, the read / write to the cache memory 2 or the shared memory 6 is performed a plurality of times within the processing for one command. Also shared memory 6
The access amount to the cache memory 2 is substantially proportional to the number of I / Os, whereas the access amount to the cache memory 2 corresponds to the actual transfer data amount, and is not necessarily proportional to the number of I / Os. That is, in the case of sequential access for collectively reading and writing long data, the amount of data transferred to and from the cache memory 2 is large, and in the case of random access in which a large number of reading and writing of short data are issued in parallel, the access amount to the shared memory 6 is Relatively more.

In this storage system, the bus a has a transfer width of 64 bits and is used only for accessing the cache memory 2. The bus c has a transfer width of 32 bits and is used only for accessing the shared memory 6. On the other hand, the bus b has the same data transfer capacity (64 bits) as the bus a and is connected to both the cache memory 2 and the shared memory 6, so that the use can be switched by changing the mode setting. Is possible. The mode is set by an instruction from a maintenance service terminal personal computer (not shown) connected by a local area network LAN connected to the CPUs 31 and 35 in each adapter.

The switching procedure will be described below by taking as an example the case where the bus b set for the cache memory 2 access is changed to the shared memory 6 access.

When the bus b is set for the cache memory 2, the read / write to the shared memory 6 is performed by the bus c.
Read / write to the cache memory 2 is performed by using both the bus a and the bus b at the same time. Since the address and command system of this system is made up of 64 bits, the same address and command are duplicated when the bus a and the bus b are simultaneously transferred.
However, for the data, 12 for bus a and bus b combined
The transfer time is shortened by transferring with 8-bit width.

Reference will be made to the flow chart of FIG.
First, one adapter (CHA3 or D) that received an instruction to switch the bus mode from the maintenance service personal computer
The processor (switching processor) in KA5) first sets a degeneration instruction not using the bus b in the communication area (not shown) of the shared memory 6 (S1). The other adapters (slaves) regularly share the shared memory 6 even during operation.
(S21), the reception report is set in the shared memory 6 when the degeneration instruction for bus switching is received (S22), and only the bus a is used for subsequent access to the cache memory 2. To do. The switching decision processor checks the communication area of the shared memory 6, and if all the receipt reports from other adapters can be confirmed (S2), the hardware for switching is set (S).
3). In this hardware setting, the mode of the internal register 76 and the on / off setting of an internal register (not shown) for setting the operation enable / disable information of the arbiters 74a and 74b are performed. Then, an instruction to change the bus b for the shared memory 6 is set in the communication area (S4). The other adapter that has confirmed this instruction switches its access mode (S23). In this access mode switching, the mode of the internal register 76 of its own is set. The I / F control units 78 and 79 of BSAa and BSAb in each adapter operate according to the mode set in the internal register 76. As a result, the bus b can be used from the next access to the shared memory 6.

It should be noted that, contrary to the procedure of FIG.
When changing from the access for the shared memory 6 to the access for the cache memory 2, the switching can be performed by the same procedure.

As shown in FIG. 5 (b), the bus b is used for cache access. The bus b is temporarily disabled from the cache memory state.
Via the degenerate state, the state of the bus b is changed to the state of the shared memory of the bus b which is used for accessing the shared memory. By this method, switching of bus applications can be realized without stopping the operation of the system.

The flow of information on each bus in the bus b cache memory mode will be described with reference to FIG.
In this mode, the bus b is used for cache memory access, and all 64 bits are used.

First, in the case of read access, the read address is first issued in the address phase (ADR) and then the read command is issued in the command phase (CMD) on each bus from the adapter (CHA / DKA) side. The address for accessing the cache memory is
The same address is double-transferred simultaneously in the two systems of bus a and bus b. The command is similar. In response to this, each memory transfers data of 128-bit width to the adapter in both the bus a and the bus b in the data phase (DATA).
After the data transfer is completed, status information (transfer completion or error) is returned to the adapter in the error phase (ERR). Even in this error phase, the same status is duplicated in both buses a and b.

Next, in the case of write access, the adapter issues a write address in the address phase on each bus and then transfers the write data in the data phase. In response to this, the status is returned from the memory to the adapter in the error phase. As in the case of read access, data is transferred with a 128-bit width.

Note that in FIG. 3, for convenience of description, the bus c is shown to be accessed at the same time as the buses a and b, but the memory access via the bus c is the memory access via the buses a and b. Is independent of.

The flow of information on each bus in the shared memory mode for the bus b will be described with reference to FIG. In this mode, the three bus systems transfer independently. Unlike the case of FIG. 3, the bus b is used for shared memory access, and the 64-bit bus uses only half of 32 bits. In the read access, different addresses are transferred in parallel to the shared memory in the address phase on the bus b and the bus c. In the command phase, different addresses are transferred in parallel on the buses b and c. Even in the data phase and the error phase, separate data and status are transferred on each bus. The same applies to write access.

For convenience of explanation, in FIG.
Commands with the same b and c at the same time (read or write)
The memory access of buses a, b, and c is independent of each other.

As described above, when the access data from the host computer is large and the number of reads / writes to the cache memory is large, the bus b is switched to the cache memory, and conversely, if it can be determined that parallel random access frequently occurs, the bus b is switched. By switching for shared memory, it is possible to maximize the overall bus limit performance.

In the storage controller of this embodiment, bus switching is also used as a countermeasure against a bus system failure. For example, if the bus a becomes inoperable due to a failure, the bus b is switched to the cache memory 2 so that the operation of the system can be continued even if the performance is slightly lowered. Similarly, bus b,
Even if either one of the buses c becomes a failure, by appropriately switching the bus configuration, the read / write to both the cache memory 2 and the shared memory 6 can be continued, and the operation until the maintenance personnel rushes can be guaranteed. In a system having a plurality of buses having the same function as the bus b,
Even in this degenerate operation, the above switching method can be realized as long as three or more bus systems operate normally. In the above-described embodiment, only a part of the transfer bus has a structure that can be used by switching between data transfer and control information transfer, but it is also possible to perform switching for all buses.

Although the switching operation start timing in the above-mentioned embodiment is the instruction of the maintenance staff via the maintenance service personal computer, the operation status of the storage control device is monitored in the maintenance service personal computer, and the threshold value is set. It is also conceivable to judge and issue the corresponding instruction to the storage controller. For example, the data amount of sequential access is detected based on the size of the transfer data within a fixed time, and if the data amount is larger than a predetermined amount, the sequential mode is set. If this logic is provided in the main body of the storage controller,
A storage control device capable of automatically switching the bus suitable for the access pattern of the host is also conceivable.

[0047]

According to the present invention, it is possible to switch a specific bus for data access or control information access in response to an instruction from the maintenance service panel or a terminal personal computer therefor. As a result, the transfer bus possessed by the system can be reconfigured into a desired system, the bus can be used efficiently, and the marginal performance can be improved by averaging the load on each bus. For example, in an operating environment where the ratio of online processing is high, high response performance can be achieved by prioritizing communication of control information, and in an operating environment where the ratio of sequential processing is high, priority can be given to data transfer capability. Becomes

Further, it is possible to construct a bus system according to the purpose of the system without interrupting the access processing from the host.

[Brief description of drawings]

FIG. 1 is a block diagram of a storage control device to which the present invention is applied.

FIG. 2 is a block diagram showing a bus system configuration of a main part of FIG.

FIG. 3 is an explanatory diagram of an operation when the bus b is used for cache memory access in the device of FIG.

FIG. 4 is an explanatory diagram of an operation when the bus b is used for shared memory access in the device of FIG.

5 is a flow chart showing a bus switching procedure in the device of FIG. 1 and an explanatory diagram of the operation of the bus switching process.

FIG. 6 is a block diagram showing the internal configuration of the adapter of FIG.

[Explanation of symbols]

1: Host connection hardware, 2: Cache memory,
3: CHA (channel adapter), 4: disk array, 5: DKA (disk adapter), 6: shared memory, 7: shared transfer bus, 75: requester, BSA: bus adapter, SMP: shared memory port

Front page continuation (72) Inventor Hisao Honma 2880, Kozu, Odawara, Kanagawa, Ltd., Hitachi Storage Systems Division Department

Claims (3)

[Claims] 1. A storage device having a first storage device for storing data, a second storage device for storing control information, and three or more sets of buses for accessing the first and second storage devices. In the system, at least one of the three or more transfer buses has a structure that can be used for either data transfer or control information transfer, and a switching instruction is given regardless of whether the storage system is in operation. On the basis of the above, the at least one set of transfer buses is switched to any one of the above-mentioned applications and used. 2. When switching the use of the at least one set of buses while the storage system is operating, the use of the at least one set of buses is prohibited until the processing for the switching is completed, and the like. 2. The bus switching control method according to claim 1, wherein the bus is used to continue the operation. 3. An external storage device, a cache memory for temporarily storing input / output data to / from the external storage device, and at least data stored in the cache memory connected to the second and third buses. Shared memory for storing control information including management information; channel adapter means for controlling data transfer between the host device and the cache memory by using the contents of the shared memory; and contents of the shared memory A disk adapter means for controlling data transfer between the external storage device and the cache memory, and a first interconnecting means for interconnecting the channel adapter means, the disk adapter means, and the cache memory.
And a second bus interconnecting the channel adapter means, the disk adapter means, the cache memory, and the shared memory with each other, and the disk adapter means, the channel adapter means, and the shared memory with each other. A third bus for connection, wherein the channel adapter means and the disk adapter means selectively use the second bus by switching between the cache memory access and the shared memory access. External storage controller.