KR20030068663A - Apparatus and method for synchronization of non-volatile memory information between duplexing board - Google Patents

Abstract

PURPOSE: A device and method for synchronizing nonvolatile memory information between duplex boards is provided to synchronize data of a nonvolatile area for storing environment of a system for operating a duplex board in the same environment as a board which was operated in an active area when the duplex board is changed from a standby state to an active state. CONSTITUTION: CPUs(201,211) are operated independently in each board and access to a nonvolatile memory with a predetermined privilege. In an access request of the CPUs(201,211), bus control units(203,213) check an abbreviated alert, and control and read/write a bus access request in accordance with a use of the abbreviated alert. Data of nonvolatile memory(205,215) are synchronized according as the CPUs(201,211) are accessed to an identical area through the bus control units(203,213). The device for synchronizing nonvolatile memory information transmits and receives abbreviated alert between the bus control units(203,213), and informs other CPU an access to the nonvolatile memory(205,215).

Description

Apparatus and method for synchronization of non-volatile memory information between duplexing board}

The present invention relates to an apparatus and method for synchronizing nonvolatile memory data that stores operating environment information of each redundant board (active board and standby board) in a redundant system.

In general, in the case of electronic communication systems, processor boards such as CPU boards, which cause a fatal failure in the overall system operation, such as CPU boards, are configured in a redundant structure having two states of active / standby. Doing.

One of the redundant processor boards operates normally in the active state, the other standby in the standby state, and then switches to the active state when there is an error in the active board so that the system can operate normally.

The changeover of the redundancy system is largely divided into the change by the demand of hardware and the change by the demand of software. Hardware requirements typically arise in the case of temperature failures, power failures, resets, and hardware watchdogs, while software requirements arise from software resets and hotswap. ), Memory overflow, and other system requirements.

In general, the bus controller divides redundancy information between the active and standby boards. The redundancy signals operate differently depending on the design. The standby board may check the state of the active board (read the value of the register) at regular intervals to cause a changeover, or when the changeover situation occurs, the active board may request a transfer to the standby board using an interrupt signal.

1 is a configuration diagram of a general redundancy system.

Referring to FIG. 1, the active board 100 and the standby board 110 each include a central processing unit 101, 111, and bus control units 103 and 113, and through the bus control units 103 and 113. Redundancy operation is performed by sending and receiving redundancy signals. That is, the central processing unit 101 of the active board 100 transmits the redundancy signal and the transfer request signal to the standby board 110 through the bus control unit 103, thereby active in the central processing unit 113 of the standby board 110. Will operate in mode.

However, the duplication board 100 and 110 must be consistent with the environment information of each memory for duplication at all times, so the duplication operation is efficiently performed.

And, the redundant signals are operated differently depending on the design. The standby board checks the status of the active board at regular intervals, that is, it may cause a transfer after reading a register value, or when the changeover situation occurs, the active board may request a transfer to the standby board using an interrupt signal. have.

However, when switching the software, the standby board does not know which switching cause requires the switching, so it is difficult to know the error management of the system and the main switching cause. Therefore, it is difficult to stabilize the system by analyzing frequent switching causes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and the environment of a system so that a redundant board is changed from standby to an active state to operate in the same environment as the board operating in the active state when providing a service. It is an object of the present invention to provide an apparatus and method for synchronizing nonvolatile memory information between redundant boards to synchronize data in a nonvolatile region for storing information.

1 is a configuration diagram of a conventional redundant system.

Figure 2 is a block diagram showing an environment information synchronization device between each board in a redundancy system according to the present invention.

3 is a flowchart illustrating a method for synchronizing environmental information between boards in a redundant system according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200 ... active board 210 ... standby board

201,211 ... Central Processing Unit203,213 ... Bus Control Unit

Non-volatile Memory

In order to achieve the above object, a non-volatile memory data synchronization device between redundant boards according to the present invention,

In the active and standby board initialized to active or standby in accordance with the system policy upon initialization; A central processing unit which requests access to a nonvolatile memory with a predetermined authority during an active operation in the board, and a bus controller which controls a bus access request according to whether a busy signal is used after checking a busy signal when accessing the central processor; And a nonvolatile memory for generating a signal in use by the central processing unit and synchronizing data by access of an area by a bus controller.

Preferably, the bus control unit transmits a busy signal to each other to inform the counterpart central processing unit of the access to the nonvolatile memory.

Preferably, the central processing unit simultaneously accesses the same address through one hardware connection path when accessing the nonvolatile memory.

The nonvolatile memory data synchronization method according to the present invention may include: initializing an active or standby state according to a system policy and operating with a predetermined access right in an area of the nonvolatile memory; Checking the busy signal upon access to the nonvolatile memory from the central processing unit and controlling access to the nonvolatile memory according to the result; Generating a busy signal and performing access to a nonvolatile memory in a central processing unit if the busy signal is allowed to be used; And performing, by the central processing unit, a write command for the nonvolatile memory to the same area of each nonvolatile memory through a hardware path by the bus controller to synchronize data.

Preferably, the checking of the busy signal may enable the central processing unit to inform the counterpart central processing unit of the access to the nonvolatile memory using the busy signal.

Preferably, after the initialization process, an active central processing unit records all areas of its own nonvolatile memory and writes them to the other party's nonvolatile memory to prevent information mismatch between two boards. .

Preferably, the central processing unit operating in a standby state, in the event of an error or error in the active central processing unit reads information from its own non-volatile memory is initialized to be active and operating as an active.

The apparatus and method for synchronizing nonvolatile memory data between redundant boards according to an exemplary embodiment of the present invention as described above will be described with reference to the accompanying drawings.

The active board 200 and the standby board 210 include central processing units (CPUs) 201 and 211, bus control units 203 and 213, and non-volatile memory (NVRAM) 205 and 215, respectively. The 201 and 211 operate independently on each board, and access the nonvolatile memories 205 and 215 and operate with predetermined rights.

The bus controller 230 accesses the nonvolatile memories 205 and 215 to perform a read / write command, and the bus controllers 203 and 213 are in use by the counterpart central processing unit 201 and 211 when the memory area is accessed. In this case, the access rights of the nonvolatile memories 205 and 215 are determined according to the signal. In other words, the busy signal 220 is operated by each of the central processing units 201 and 211 independently and has one hardware connection path 230 to each of the nonvolatile memories 205 and 215. Access to volatile memories 205 and 215 can be communicated to the relative central processing unit.

The nonvolatile memories 203 and 213 are memory regions for storing environmental information of the system, and the information is maintained even when there is no power supply. The nonvolatile memories 203 and 213 may not know which central processing unit 201 or 211 requests access.

In addition, the hardware path 230 is a physical connection used to access the nonvolatile memories 205 and 215 through the bus controllers 203 and 213. The hardware path 230 is connected to the nonvolatile memories through the bus controllers 203 and 213 in the central processing unit 201 and 211. In order to access 203 and 213, two nonvolatile memories 203 and 213 are simultaneously accessed to the same address.

Each of these redundant boards 200 and 210 is initialized to active or standby according to system policy upon initialization. The active board 200 performs a service and operates with read / write rights to the areas of the nonvolatile memories 205 and 215.

The standby board 210 serves as a backup of the active board 200, and acts as an active board during abnormal operation of the active board 200, and operates only with a read right to the nonvolatile memory area.

The data synchronization of the nonvolatile memories 205 and 215 and the independent access operations of the nonvolatile memory regions of the central processing units 201 and 211 will be described below.

First, each redundant board is initialized to an active or standby mode according to a system policy at initialization (S101). At this time, the active board performs a service and operates with read / write authority to a nonvolatile memory area. The board acts as a backup of the active and operates in an active state during the abnormal operation of the active and operates only with a read right to the nonvolatile memory area (S102 and S103).

When the system operates (S104), the central processing unit 201,211 requests access to the nonvolatile memory through the bus controllers 203,213 (S105). At this time, the central processing unit 201, 211 checks the busy signal (S106). This informs the counterpart central processing unit 201, 211 of the access to the nonvolatile memories 205 and 215 using the busy signal to check whether the busy signal is used. That is, when the central processor wants to access the nonvolatile memories 205 and 215, the bus controller 203 and 213 transmit the busy signal 220 from the counterpart central processor to determine whether the signal is used. If it is not used, it can be used, which generates a busy signal.

In this case, if the busy signal is in a yes state, the CPU generates a busy signal and accesses the nonvolatile memory 205 and 215. If the busy signal is not available (no), the other central processing unit is approaching the nonvolatile memory (S107), and thus waits for the nonvolatile memory access to the central processing unit 201 and 211 to the nonvolatile memory 205. Notify that 215 is not accessible.

Then, the central processing unit 201 of the active board 200 executes a write command to the nonvolatile memories 205 and 215. Each of the nonvolatile memories is performed by the bus controller 203 through the hardware path 230. The same information is stored and synchronized in the same area at the same time in the (205) and 215 areas. In addition, since the information of the nonvolatile memory 205 (215) does not change during the read command, it is not necessary to synchronize.

The active central processing unit 201 reads and writes all areas of the nonvolatile memories 205 and 215 after the initialization process is completed to prevent information mismatch between the two boards 200 and 210 that may occur initially.

The central processing unit 211 operating as a standby reads information from its nonvolatile memory 215 when an error or an error occurs in the active central processing unit 201, initializes the active board, and operates in the active mode.

As described above, according to the apparatus and method for synchronizing nonvolatile memory information between redundant boards according to the present invention, the non-volatile memory information synchronization can be performed by using a physical hardware path to reduce software burden, and By using the signal, there is an effect of preventing simultaneous access to the nonvolatile memory of each central processing unit.

Synchronizing nonvolatile information between different boards can be easily achieved by reading and writing all nonvolatile memory information in the active state. In addition, since the nonvolatile memory can be accessed by referring to the busy signal in the standby state, more operations can be performed in the standby state, thereby simplifying the redundant system configuration.

Claims (7)

In the active and standby board initialized to active or standby in accordance with the system policy at initialization; A central processing unit that operates independently on each board and accesses a nonvolatile memory with a predetermined authority, and checks a busy signal when the central processor access request and controls a bus access request according to whether the busy signal is used or not. And a non-volatile memory in which data is synchronized in accordance with the access of the same area through the bus controller in the central processing unit. The method of claim 1, And transmitting and receiving a busy signal between the bus controllers to notify each other's central processing unit of access to the nonvolatile memory. The method of claim 1, And the central processing unit simultaneously accesses the same address through one hardware connection path when accessing the nonvolatile memory. Initiating active or standby according to a system policy to operate with a predetermined access right to an area of the nonvolatile memory; Checking the busy signal when the CPU accesses the nonvolatile memory and controlling access to the nonvolatile memory according to the result; Generating a busy signal and performing access to a nonvolatile memory in a central processing unit if the busy signal is allowed to be used; Non-volatile memory information between the redundant boards, wherein the central processing unit simultaneously performs a write command for the nonvolatile memory to the same region of each nonvolatile memory through a hardware path by a bus controller to synchronize data. Sync method The method of claim 4, wherein The checking of the busy signal enables the central processing unit to inform a counterpart central processing unit of the access to the nonvolatile memory using the busy signal. The method of claim 4, wherein After the initialization process, the active central processing unit records all areas of its own nonvolatile memory and writes them to the other party's nonvolatile memory to prevent information inconsistency between the two boards that may initially occur. How to synchronize nonvolatile memory information. The method of claim 4, wherein And synchronizing nonvolatile memory information between the redundant boards by reading information from the nonvolatile memory of the active central processing unit in the standby mode and operating as an active unit. Way.