JPH0764938A - Device for starting multiple cpu system - Google Patents

Abstract

PURPOSE:To provide a system for which the need of increasing ROMs is eliminated even when the number of CPUs increases by turning the ROM of a main CPU and a sub CPU to a shared memory. CONSTITUTION:An IPL program is stored in the ROM 5, the program is loaded from an auxiliary storage device 3 to a RAM 2 after the initial setting of the main CPU 1 and control is transferred to the program of the RAM 2. Thereafter, the address of the ROM 5 is switched to the side of the sub CPU 8, the reset of the sub CPU 8 is cancelled by reset instruction signals 10, the program of the sub CPU 8 is loaded from the auxiliary storage device 3 to the RAM 5 which is the shared memory and the sub CPU 8 is instructed of loading completion. The sub CPU 8 waits for the loading completion instruction from the main CPU 1 after the initial setting and transfers the control to the down-loaded program on a second shared memory 6 when loading completion instruction signals 9 are outputted from the main CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a start-up device for a multi-CPU system, and more particularly to a ROM (Read Only M
emory) as a shared memory and each CPU can be booted from the same ROM.

[0002]

2. Description of the Related Art There are various types of multi-CPU systems, one of which is a main CPU and a sub CPU.
There is a method consisting of. FIG. 3 is a block diagram of a conventional CPU system start-up device, in which 21 is a main CPU.
(Central processing unit), 22 is ROM, 23 is RAM (Random
m Access Memory), 24 an auxiliary storage device, 25 a common bus (main CPU), 26 a shared memory, 27 a sub CPU, 28 a ROM, 29 a load end instruction signal, 3
Reference numeral 0 is a common bus (sub CPU). 4 (a),
(B) is a flowchart showing a conventional method of starting a CPU system. FIG. 7A is a flowchart showing a main CPU starting method, and FIG. 9B is a flowchart showing a sub CPU starting method. Hereinafter, each step will be described in order.

The operation when the program is first started, such as when the power is turned on, will be described. When the power is turned on, the main CPU2
1 is activated to execute the program in the ROM 22. R
The OM 22 stores an IPL program, and after the initial setting of the main CPU 21 (S1), the auxiliary storage device 24
Loads the program into the RAM 23 via the common bus 25 (S2), and transfers control to the program in the RAM 23. Then, the program of the sub CPU 27 is loaded from the auxiliary storage device 24 into the shared memory 26 via the common bus 25 (S3), and the sub CPU 27 is instructed to end the loading (S4). The ROM 28 is activated by turning on the power supply or the like in the same manner as the main CPU 21. After the initial setting (S5), the sub CPU 27 waits for a load end instruction from the main CPU 21 (S6). When it is output, the download ends. After that, the sub CPU executes the downloaded program on the shared memory.

[0004]

As described above, in the conventional CPU system start-up device, both the main CPU and the sub CPU need to have an IPL ROM, and as many ROMs as the number of CPUs are required. Became. This does not cause any particular problem when it is composed of one main CPU and one sub CPU, but when it is composed of a plurality of sub CPUs, a plurality of ROMs having the same contents are required. There was a problem that the more wasted, the more wasted.

The present invention has been made in view of the above circumstances, and by using the ROM of the main CPU and the sub CPU as a shared memory, even if the number of CPUs increases, R
Multi-C system that does not need to increase OM
It is intended to provide an activation device for a PU system.

[0006]

In order to achieve the above object, the present invention provides a multi-C system including a plurality of processors.
In a PU system, R for performing IPL of each processor
The OM is used as a shared memory, and a switching means for switching the ROM address and an instruction means for instructing another CPU to reset are provided, and when one CPU finishes the program operation on the ROM, the program on the RAM Transfer control,
After switching the ROM address to the next CPU,
The control of the ROM is switched to the CPU by canceling the reset.

[0007]

[Operation] The main CPU is in the ROM when its own IPL is completed.
Control is transferred to the program on the RAM, the ROM is switched to the address of the sub CPU, and the reset of the sub CPU is released. In the sub CPU, the program on the ROM operates after the reset is released, and in response to the download end instruction from the main CPU, the control is transferred to the program on the RAM and the ROM is disconnected. In this way, one ROM can be shared and used, and there are advantages in cost and mounting space.

[0008]

Embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a multi-CPU system starting device according to the present invention.
Is a main CPU (central processing unit), 2 is a RAM (Random
Access Memory), 3 is an auxiliary storage device, 4 is a common bus (main CPU), 5 is a first common memory (ROM), 6 is a second common memory (RAM), 7 is an address switching circuit,
8 is a sub CPU, 9 is a load end instruction signal, 10 is a reset instruction signal, 11 is an address switching instruction signal, and 12 is R.
OM address, 13 is a common bus (sub CPU).
2 (a) and 2 (b) are flowcharts for explaining the operation procedure of the activation device of the multi-CPU system according to the present invention. Figure (a) is the main CPU, Figure (b) is the sub C
It is a flowchart which shows the operation procedure of PU. Hereinafter, each step will be described in order.

When the power is turned on, the main CPU 1 is activated to execute the program in the ROM 5 which is a shared memory. An IPL program is stored in the ROM 5, and after initializing the main CPU 1 (S1), the program is loaded from the auxiliary storage device 3 to the RAM 2 via the common bus 4 (S2), and control is passed to the program in the RAM 2. (S3). After that, the address of the ROM 5 is set to the sub CPU 8
To the side (S4), the reset instruction signal 10 releases the reset of the sub CPU 8 (S5), and the RAM, which is a shared memory, from the auxiliary storage device 3 via the common bus 4.
Load the program of sub CPU8 into 5 (S6),
The sub CPU 8 is instructed to end loading (S7).

Although the sub CPU 8 is in the reset state when the power is turned on, the program on the ROM 5 is started by the reset release from the main CPU 1, and after the initial setting (S
8) Waiting for the load end instruction from the main CPU 1 (S9), and the load end instruction signal 9 from the main CPU 1
Is output, control is transferred to the downloaded program on the second shared memory 6 (S10). The address switching circuit 7 is a circuit for outputting to the ROM 5 either the ROM address input from the main CPU 1 or the sub CPU 8 in response to an address switching instruction from the main CPU, but by adding an address conversion function,
The ROM can be divided into areas of the main CPU 1 and the sub CPU 8. In this case, IPL programs of different types of CPUs (different machine languages) can be placed in one ROM.

[0011]

As is clear from the above description, according to the present invention, the ROM is used as a shared memory for the main CPU and the sub CPU, and means for switching the address of the ROM is provided.
Since the means for instructing the reset to the sub CPU is provided, the ROMs of a plurality of CPUs can be shared, which is effective in cost and mounting space.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an example of an activation device of a multi-CPU system.

FIG. 2 is a flow chart for explaining an operation procedure of an activation device of a multi CPU system according to the present invention.

FIG. 3 is a configuration diagram of a conventional CPU system activation device.

FIG. 4 is a flowchart for explaining an operation procedure of a conventional CPU system activation device.

[Explanation of symbols]

1 ... Main CPU (Central Processing Unit), 2 ... RAM (Random)
m Access Memory), 3 ... Auxiliary storage device, 4 ... Common bus (main CPU), 5 ... First common memory (ROM),
6 ... Second common memory (RAM), 7 ... Address switching circuit, 8 ... Sub CPU, 9 ... Load end instruction signal, 10 ...
Reset instruction signal, 11 ... Address switching instruction signal, 12
... ROM address, 13 ... Common bus (sub CPU).

Claims (1)

[Claims] 1. A multi-C composed of a plurality of processors.
In a PU system, R for performing IPL of each processor
The OM is used as a shared memory, and a switching means for switching the ROM address and an instruction means for instructing another CPU to reset are provided, and when one CPU finishes the program operation on the ROM, the program on the RAM Transfer control,
After switching the ROM address to the next CPU, the CP
An activation device for a multi-CPU system, wherein control of a ROM is switched to the CPU by releasing the reset of U.