CN115826450A - Logic control device of serial peripheral interface, master-slave system and master-slave switching method thereof - Google Patents
Logic control device of serial peripheral interface, master-slave system and master-slave switching method thereof Download PDFInfo
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Abstract
The invention discloses a logic control device, a master-slave system and a master-slave switching method of a serial peripheral interface, wherein the logic control device is connected between N hosts and M slaves, and defines master-slave connection relations between the hosts and the slaves, each master-slave connection relation is that the hosts and the slaves transmit information one by one at the same time, and the logic control device is connected between the N hosts and the M slaves to form the master-slave system and the master-slave switching method thereof.
Description
Technical Field
The present invention relates to a serial peripheral interface, and more particularly, to a logic control device, a master-slave system and a master-slave switching method for a serial peripheral interface.
Background
According to Serial Peripheral Interface Bus (SPI for short) carried by wikipedia, it is a synchronous Serial communication Interface specification for chip communication, and it is mentioned in the prior art of taiwan patent No. I701555 (hereinafter referred to as "the first patent application"), that Serial Peripheral interfaces are commonly included in mobile devices to provide synchronous Serial communication between a system on a chip (SoC) processor and various Peripheral devices. The SoC acts as an SPI Master device (hereinafter referred to as Master) and each peripheral device acts as a Slave SPI device (hereinafter referred to as Slave).
The SPI bus couples the master to each slave. The host supplies a clock to a clock line in the SPI bus. All serial data exchanges between the master and slave are synchronized with the clock signal. The Master Outputs Slave Input (MOSI) line driving data to the slave via the master. The slaves may each drive data to the master on a common Master Input Slave Output (MISO) line. Since the MISO line is shared by the slaves, the SPI bus also includes a slave select line for each slave to provide access protocols to the shared MISO line.
Each slave has its own slave select line, so the SPI bus at each slave is a four wire bus to accommodate clock, MOSI, MISO, and slave select signaling. But the SPI bus at the master will be the (3+N) wire bus, where N is the number of slaves representing the master connected, also equal to the number of slave select lines. Each wire in the SPI bus is dedicated to its own pin, so that the number of pins at the master increases with the number of slaves it connects.
For example, please refer to fig. 1, which shows a connection state between a master 10 and two slaves 12, wherein the master 10 is connected to the two slaves 12, and thus the master 10 needs to add one slave selection line and have two slave selection lines in total, and so on, and the master 10 is connected to the three slaves 12 and needs to add another slave selection line and have three slave selection lines in total. Furthermore, as shown in fig. 2 and fig. 3, the master 10 can select only one of the slaves 12 for data transmission at a time via the slave select line. In fig. 1, CS1 and CS2 are slave select lines, CLK is a clock line, MOSI is a master-output-slave input line, and MISO is a master-input-slave output line, and since a general slave and a master have the same lines and have the same functions, the lines other than the slave select lines are generally denoted by the same symbols.
In addition, to solve the problem that the number of pins at the master increases with the number of slaves connected to the master, the prior art further discloses that a multiplexer and an Inter-Integrated Circuit (I-I) are respectively added in the master and the slaves 2 C) Interfaces, but doing so in reverseOne of the problems is that the original master and slave are not discarded, which leads to an increase in cost and waste. Another problem is that in order to reduce the number of slave select lines between the master and the slave, an interface between the multiplexer and the embedded ic is added to the internal circuits of the master and the slave, which increases the circuit area inside the master and the slave. A further problem is that more lines are required between the interface between the multiplexer and the embedded integrated circuit, resulting in the need for additional verification of various electrical characteristics of the derived lines by the master or slaves, and yet another problem is that all slaves can only be connected to one master.
To solve the problem, please refer to fig. 4, in which two-to-two multiplexers 14 are used to be butted with each other, one of the two-to-two multiplexers 14 is connected to two masters 10, and the other one-to-two multiplexer 14 is connected to a slave 12, so that a transmission path (as shown in fig. 5 to 8) can be established between one master 10 and one slave 12 at the same time, but this connection method leaves another master 10 and another slave 12 idle at the same time, and does not effectively use all the masters 10 and slaves 12.
In summary, it is an urgent need to solve the above-mentioned problem how to allow each master to be connected to one of different slaves at the same time without using too many multiplexers in the state of connecting the traditional masters and slaves.
Disclosure of Invention
In view of the problems of the prior art, it is an object of the present invention to connect a plurality of masters and a plurality of slaves using a logic control device, and to control the connection state between each master and each slave at the same time.
According to the present invention, a logic control device of a serial peripheral interface includes a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, and a selection unit, wherein the first logic unit is connected between slave selection lines of N masters and slave selection lines of M slaves, N and M are integers greater than or equal to two, the second logic unit is connected between clock lines of the N masters and clock lines of the M slaves, the third logic unit is connected between a master output slave input line of the N masters and a master output slave input line of the M slaves, the fourth logic unit provides a master input slave output line connected between the master input slave output lines of the N masters and a master input slave output line of the M slaves, and the logic relationships of the first logic unit, the second logic unit, the third logic unit, and the fourth logic unit define a master-slave connection relationship between the N masters and the M slaves together, the selection unit connects the first logic unit, the second logic unit, the third logic unit, and the fourth logic unit, and determines to use one of the master-slave connection relationship, and the master-slave connection relationship is different master-slave connection information transmission relationships.
According to another aspect of the present invention, there is provided a master-slave system having a logic control device, including N masters, M slaves and the logic control device, each master and each slave has a slave select line, a clock line, a master output slave input line and a master input slave output line, and each master has only one slave select line, the number of slave select lines of each master does not increase with the number of slaves, the logic control device is connected between each master and each slave, and defines a master-slave connection relationship between each master and each slave, and each master-slave connection relationship is that each master simultaneously transmits information only with one different slave.
According to the object of the present invention, a method for switching a master-slave system with a logic control device is provided, which is applied to the master-slave system with the logic control device, and comprises the following steps of providing N masters and M slaves to be connected with the logic control device, wherein the logical relationships of the first logical unit, the second logical unit, the third logical unit and the fourth logical unit of the logic control device define the master-slave connection relationships between the N masters and the M slaves together, each master-slave connection relationship is that each master simultaneously transmits information only with one different slave, and it is determined which master-slave connection relationship the selection unit selects to use, and the logic control device connects each master to one of the different slaves according to the selected master-slave connection relationship.
The Logic control Device is a Programmable Logic Device (PLD), and further is a Simple Programmable Logic Device (SPLD), and the first Logic unit, the second Logic unit, the third Logic unit, and the fourth Logic unit are a Look-Up Table (Look-Up-Table, LUT) set, a second Look-Up Table set, a third Look-Up Table set, and a fourth Look-Up Table set of the PLD, each Look-Up Table set having S Look-Up tables (LUT), where S is greater than or equal to M.
The first lookup table set, the second lookup table set, the third lookup table set and the fourth lookup table set are respectively provided with two lookup tables, and a first master-slave connection relation and a second master-slave connection relation are defined, wherein the first master-slave connection relation is that the first master transmits data to the first slave, the second master transmits data to the second slave, the second master-slave connection relation is that the first master transmits data to the second slave, and the second master transmits data to the first master.
The logic control device of the serial peripheral interface further comprises a switch unit, wherein the switch unit is connected among the M slaves, the first logic unit, the second logic unit and the third logic unit, and between the N hosts and the fourth logic unit, when the switch unit is in an on state, the logic control device can output signals to the first logic unit, the second logic unit, the third logic unit and the fourth logic unit, and when the switch unit is in an off state, the logic control device can not output signals to the first logic unit, the second logic unit, the third logic unit and the fourth logic unit.
In summary, the present invention utilizes the logic control device to control the host and the slave of the serial peripheral interface bus to transmit data in a one-to-one manner at the same time, thereby completely solving the problems mentioned in the prior art.
Drawings
Fig. 1 is a schematic diagram of a traditional wire connection architecture from a master to two slaves.
Fig. 2 is a schematic diagram of the master machine of fig. 1 connected to one of the slaves.
Fig. 3 is a schematic diagram of the master of fig. 1 connected to another slave.
Fig. 4 is a schematic diagram of a conventional multiplexer connecting two masters and two slaves.
Fig. 5 is a schematic diagram of the master-slave unit of fig. 4.
Fig. 6 is a schematic diagram of the second master connected to the second slave in fig. 4.
Fig. 7 is a schematic diagram of the master-slave connection shown in fig. 4.
Fig. 8 is a schematic diagram of the master-slave unit in fig. 4.
FIG. 9 is a schematic diagram of a master-slave system with a logic control device according to the present invention.
Fig. 10 is a schematic diagram of the first master connected to the first slave and the second master connected to the second slave in fig. 9.
Fig. 11 is a schematic diagram of fig. 9 in which the first master is connected to the second slave and the second master is connected to the first slave.
Fig. 12 is a schematic diagram of the masters and slaves of fig. 9 being completely disconnected.
FIG. 13 is a schematic diagram illustrating a connection state of a first logic unit according to the present invention.
FIG. 14 is a diagram illustrating a connection state of a second logic unit according to the present invention.
FIG. 15 is a diagram illustrating a connection state of a third logic unit according to the present invention.
Fig. 16 is a schematic diagram illustrating a connection state of a fourth logic unit according to the present invention.
FIG. 17 is a schematic diagram illustrating a logical relationship between a first lookup table and a second lookup table according to the present invention.
FIG. 18 is a schematic flow chart of the method of the present invention.
Fig. 19 is a schematic flow chart of switching of the switch unit according to the present invention.
Description of reference numerals: 4. 10-a host machine; 5. 12-a slave; 3-a logic control device; 30-a first logic unit; 32-a second logic unit; 34-a third logic unit; 36-a fourth logic unit; 37-a selection unit; 38-a switching unit; 60-a first host; 62-a second host; 70-a first slave; 72-a second slave; 300-a first look-up table; 302-a second look-up table; 320-a third lookup table; 322-a fourth lookup table; 340-a fifth lookup table; 342-a sixth lookup table; 360-a seventh lookup table; 362-an eighth lookup table; 311-first variant; 312-a second variant; 313-a third variant; 8-master-slave systems; CS1, CS2, MCS 1-MCSN, SCS 1-SCSM-dependent selection lines; CLK, MCLK 1-MCLKn, SCLK 1-SCLK-clock line; MOSI, MMOSI 1-MMOSIN, SMOSI 1-SMOSIM-host output slave input line; MISO, MMISO 1-MMISON, SMISO 1-SMISOM-host input-slave output lines; 14-a one-to-two multiplexer; S101-S103-process steps; S201-S203-flow steps.
Detailed Description
Embodiments of the invention will be further illustrated by the following description in conjunction with the associated drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for simplicity and convenience. It is to be understood that elements not specifically shown in the drawings or described in the specification are in a form known to those skilled in the art. Many variations and modifications may be made by one of ordinary skill in the art in light of the teachings of the present invention.
The description below of "one embodiment" or "an embodiment" refers to a particular element, structure, or feature associated with at least one embodiment. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The present invention is described with respect to the following examples, which are intended to be illustrative only, since various modifications and changes may be made therein by those skilled in the art without departing from the spirit and scope of the present invention, which is defined in the appended claims. Throughout the specification and claims, unless the context clearly dictates otherwise, the words "a" and "an" include the word "a" or "an" and "the" include the element or component. Furthermore, as used herein, the singular articles "a", "an", and "the" include plural referents or components unless the context clearly dictates otherwise. Also, as used in this description and throughout the claims, the meaning of "in" can include "in" and "on" unless the content clearly dictates otherwise. The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in the art, in the disclosure herein and in the specific disclosure herein, unless otherwise indicated. Certain terms used to describe the invention are discussed below or elsewhere in this specification to provide additional guidance to the practitioner (practioner) in describing the invention. The use of examples anywhere throughout this specification, including any examples of words discussed herein, is meant to be illustrative only and certainly not limiting to the scope and meaning of the invention or of any exemplified words. As such, the present invention is not limited to the various embodiments set forth in this specification.
Referring to fig. 9, the present invention is a logic control device of serial peripheral interface, the logic control device 3 includes a first logic unit 30, a second logic unit 32, a third logic unit 34, a fourth logic unit 36, and a selection unit 37, wherein the first logic unit 30 is connected between slave selection lines (MCS 1 to MCSN) of N masters 4 and slave selection lines (SCS 1 to SCSM) of M slaves 5, the second logic unit 32 is connected between clock lines (MCLK 1 to MCLKN) of N masters 4 and clock lines (SCLK 1 to SCLKM) of M slaves 5, and the third logic unit 34 is connected between master output slave input lines (MMOSIN 1 to MMOSIN) of N masters 4 and master output slaves (smisi 1 to SMOSIM) of M slaves 5. The fourth logic unit 36 is connected between the host input slave output lines (MMISO 1 to MMISON) of the N hosts 4 and the host input slave output lines (SMISO 1 to SMISOM) of the M slaves 5, and the selection unit 37 is connected to the first logic unit 30, the second logic unit 32, the third logic unit 34, and the fourth logic unit 36. N and M referred to herein are integers of two or more.
In order to enable the logic control device 3 to switch between the master devices 4 and the slave devices 5 while connecting them one-to-one, it is also possible to select the master devices 4 to switch between the slave devices 5. Therefore, in the present invention, the logical relationship among the first logic unit 30, the second logic unit 32, the third logic unit 34 and the fourth logic unit 36 defines a plurality of master-slave connection relationships between the N masters 4 and the M slaves 5. The selection unit 37 provides an input selection signal to the first logic unit 30, the second logic unit 32, the third logic unit 34 and the fourth logic unit 36 to determine the final logic relationship among the first logic unit 30, the second logic unit 32, the third logic unit 34 and the fourth logic unit 36, so as to complete the selection of one of the master-slave connection relationships, so that the logic control device 3 can simultaneously connect the masters 4 and the slaves 5 in a one-to-one manner, and can select the masters 4 to be respectively connected to different slaves 5.
Referring to fig. 9, the present invention is a master-slave system with a logic control device, the master-slave system 8 includes N masters 4, M slaves 5 and the logic control device 3, the logic control device 3 is connected between each master 4 and each slave 5, and each master 4 and each slave 5 are respectively provided with slave select lines (MCS 1 to MCSN, SCS1 to SCSM), clock lines (MCLK 1 to MCLKN, SCLK1 to SCLKM), master output slave input lines (mmos 1 to MMOSIN, smis 1 to SMOSIM) and master input slave output lines (MMISO 1 to MMISON, SMISO1 to SMISOM). It should be noted that each master 4 of the present invention has only one slave select line (MCS 1 to MCSN), the number of slave select lines (MCS 1 to MCSN) of each master 4 does not increase with the number of slaves 5, and no additional multiplexer or Inter-Integrated Circuit (i.e., i.ic) needs to be added inside each master 4 2 C) And (6) an interface. And the logic control device 3 determinesThe master-slave connection relationship between each master 4 and each slave 5 is defined, and each master-slave connection relationship is that each master 4 is connected with one different slave 5, and is in a one-to-one connection mode.
In the present invention, the logic control device 3 is a programmable logic device, further a simple programmable logic device, and the first logic unit 30, the second logic unit 32, the third logic unit 34 and the fourth logic unit 36 are a Look-Up-Table (LUT) set, a second LUT set, a third LUT set and a fourth LUT set of the programmable logic device or the simple programmable logic device, each of the LUT sets has S LUTs, where S is greater than or equal to M. The logic control device 3 is not limited to this in practical implementation of the present invention, and for example, any electronic device with logic function may be the logic control device 3 referred to in the present invention.
In the present invention, the logic control device 3 further includes a switch unit 38, in fig. 9, triangle symbols indicate that the switch unit 38 is connected to the slave select lines (SCS 1-SCSM), the clock lines (SCLK 1-SCLKM), the master output slave input lines (smsci 1-smosmism) of the M slaves 5, and the master input slave output lines (MMISO 1-MMISON) indicating that the switch unit 38 is connected to the N masters, in fig. 13-15, the slave select lines (SCS 1-SCSM), the clock lines (SCLK 1-SCLKM), the master output slave input lines (smi 1-smosm) of the M slaves 5 are connected to the first logic unit 30, the second logic unit 32, and the third logic unit 34, respectively, and the master input slave output lines (MMISO 1-MMISON) of the N masters are connected to the fourth logic unit 36, in the present invention, the switch unit 38 provides a connection between the M slaves 5 and the first logic unit 30, the second logic unit 32, the third logic unit 34, and provides a connection between the N slaves 4 and the fourth logic unit 36, and when the switch unit 38 is turned on, the third logic unit 32, the switch unit 32, and the switch unit 38 can output a signal when the switch unit 32 is turned off, the switch unit 32, and the switch unit 34 is in the fourth logic unit 32, and the fourth logic unit 32, in the state. However, in practical implementation of the present invention, the present invention is not limited to this, and the switch unit 38 may be provided and connected between the M slaves 5 and the first logic unit 30, the second logic unit 32, the third logic unit 34, and the fourth logic unit 36, or the switch unit 38 may be provided and connected between the N masters 4 and the first logic unit 30, the second logic unit 32, the third logic unit 34, and the fourth logic unit 36, in other words, as long as it is possible to allow or stop the transmission of information between each master 4 and each slave 5.
In an embodiment of the present invention, to further understand the present invention, the logic control device 3 is illustrated as a simple programmable logic device, and further, the quotient Dai Lege semiconductor limited model SLG46537V is taken as an example, and two hosts 4 and two slaves 5 are taken as examples, wherein the two hosts 4 and the two slaves 5 are respectively defined as a first host 60, a second host 62, a first slave 70 and a second slave 72, i.e., N and M are equal to two, and the logic control device 3 has 18 pins, and the slave select lines (MCS 1 to MCSN, SCS1 to SCSM), clock lines (MCLK 1 to MCLKN, SCLK1 to SCLKM), host output slave (mmoss 1 to MMOSIN, smisi 1 to SMOSIs) and host input slave output lines (mmos 1 to mmi, smis 1 to smis) of each host 4 and each slave 5 respectively occupy one of the input lines (so 1 to mmi, smis 1 to smis) and one of the pins occupies one of the last pin 16 as the last pin selection unit 37.
The first lookup table set, the second lookup table set, the third lookup table set, and the fourth lookup table set respectively have two lookup tables, which are respectively first to eighth lookup tables (300, 302, 320, 322, 340, 342, 360, 362), the logical relationships established by the first to eighth lookup tables are all the same, and include a first variable 311, a second variable 312, and a third variable 313, where the first variable 311 corresponds to the potential change of the selection unit 37, the second variable 312 corresponds to the potential change of the first master 60, the third variable 313 corresponds to the potential change of the second master 62 (as shown in fig. 14), each variable of each lookup table represents the potential change by one bit, for example, represents a low potential by 0, and represents a high potential by 1, and whether the first master 60 and the second master 62 transmit information at the same time, when the potential of the first variable 311 is a low potential, the master-slave connection relationship is that the first master 60 and the second slave 72 transmit information, and the second master-slave connection relationship is that the first master 70 transmits information and the second slave 70 transmits the first slave 70, and the slave 311 transmits the second slave 70 transmits information when the potential of the first variable 311 is a low potential.
In the present embodiment, when the switch unit 38 is in the enabled (high) state, no matter what master-slave connection relationship is currently in, the transmission of information between each master 4 and each slave 5 is stopped, and no matter what master-slave connection relationship is currently in. Referring to fig. 15, each lookup table receives a first variable 311, a second variable 312, and a third variable 313, so that each master 4 and each slave 5 are connected in a one-to-one manner, and fig. 15 shows a circuit connection state in detail, which is not described herein again.
Referring to fig. 16, the present invention is a method for switching a master/slave system with a logic control device 3, which is applied to a master/slave system 8 with a logic control device 3, and comprises the following steps:
(S101) providing N masters 4 and M slaves 5 to connect with the logic control device 3, wherein the logical relationships among the first logical unit 30, the second logical unit 32, the third logical unit 34, and the fourth logical unit 36 of the logic control device 3 collectively define a master-slave connection relationship between the N masters 4 and the M slaves 5, and each master-slave connection relationship is that each master 4 is connected to one of the different slaves 5;
(S102) confirming which master-slave connection relationship the selecting unit 37 selects for use;
(S103) the logic control device 3 connects each master 4 to one of the different slaves 5 according to the selected master-slave connection relationship.
In the present invention, the logic control device 3 further includes a switch unit 38, the switch unit 38 is connected between each slave 5 and the first logic unit 30, the second logic unit 32, the third logic unit 34, and between each master 4 and the fourth logic unit 36, and the logic control device 3 performs the following steps:
(S201) determining at any time whether the switch unit 38 is in the off state, performing the step (S202) when the switch unit 38 is in the on state, and performing the step (S203) when the switch unit 38 is in the off state;
(S202) when the switch unit 38 is turned on, the logic control device 3 allows each of the masters 4 to transmit information to each of the slaves 5 through the first logic unit 30, the second logic unit 32 and the third logic unit 34, and allows each of the slaves 5 to transmit information to each of the masters 4 through the fourth logic unit 36;
(S203) when the switch unit 38 is in the off state, the logic control device 3 stops each of the masters 4 from transmitting information to each of the slaves 5 through the first logic unit 30, the second logic unit 32 and the third logic unit 34, and stops each of the slaves 5 from transmitting information to each of the masters 4 through the fourth logic unit 36.
In summary, the present invention utilizes the logic control device 3 to control the data transmission between the masters 4 and slaves 5 of the serial peripheral interface bus in a one-to-one manner at the same time, which not only solves the problem that the conventional master 4 needs to additionally increase the slave selection lines according to the number of slaves, but also solves the problem that any master 4 can be selectively connected to one of the slaves 5 without changing the internal architecture of the master 4 or the slaves. Furthermore, the logic control device 3 does not need to use a plurality of multiplexers, so that any master 4 can be selectively connected to one of the slaves 5, and all the masters 4 can be connected to one of the slaves 5 at the same time, thereby completely solving the problems in the prior art.
Claims (11)
1. A logic control device of a serial peripheral interface is characterized by comprising:
a first logic unit, which is provided and connected between the slave selection lines of the N hosts and the slave selection lines of the M slaves, wherein N and M are integers which are more than or equal to two;
a second logic unit, which is provided and connected between the clock lines of the N hosts and the clock lines of the M slaves;
a third logic unit, which is connected between the input line of the master output slave of the N masters and the input line of the master output slave of the M slaves;
a fourth logic unit, which is provided and connected between the master input and slave output lines of the N masters and the master input and slave output lines of the M slaves; and
a selection unit, which is respectively connected with the first logic unit, the second logic unit, the third logic unit and the fourth logic unit;
the logical relations among the first logical unit, the second logical unit, the third logical unit and the fourth logical unit jointly define a plurality of master-slave connection relations among the N hosts and the M slaves, and the selection unit determines to select one of the master-slave connection relations, wherein each master-slave connection relation is that each master simultaneously and respectively only transmits information with one of the different slaves.
2. The SPI logic control device of claim 1, wherein the logic control device is a programmable logic device or a simple programmable logic device, and the first logic unit, the second logic unit, the third logic unit, and the fourth logic unit are a first set of look-up tables, a second set of look-up tables, a third set of look-up tables, and a fourth set of look-up tables of the programmable logic device or the simple programmable logic device, each set of look-up tables having S look-up tables, wherein S is greater than or equal to M.
3. The device as claimed in claim 2, wherein when N and M are equal to two, the two masters and the two slaves are respectively defined as a first master, a second master, a first slave and a second slave, and the first lookup table set, the second lookup table set, the third lookup table set and the fourth lookup table set respectively have two lookup tables and define a first master-slave connection relationship and a second master-slave connection relationship, the first master-slave connection relationship is that the first master is connected to the first slave, the second master is connected to the second slave, the second master-slave connection relationship is that the first master is connected to the second slave, and the second master is connected to the first slave.
4. The device as claimed in claim 3, further comprising a switch unit, wherein the switch unit is connected between the M slaves and the first, second, and third logic units, and between the N masters and the fourth logic unit, when the switch unit is in an ON state, the logic control device is capable of outputting signals to the first, second, third, and fourth logic units, and when the switch unit is in an OFF state, the logic control device is incapable of outputting signals to the first, second, third, and fourth logic units.
5. A master-slave system having a logic control apparatus, comprising:
n hosts;
m slaves;
the N hosts and the M slaves are respectively provided with a slave selection line, a clock line, a host output slave input line and a host input slave output line, the N hosts respectively only have one slave selection line, and the number of the slave selection lines of the N hosts is not increased along with the number of the M slaves; and
and the logic control device is connected between the N hosts and each M slave machines, and defines a plurality of master-slave connection relations between the N hosts and the M slave machines, wherein each master-slave connection relation is that the N hosts are respectively connected with one different slave machine of the M slave machines.
6. The master-slave system with logic control apparatus as claimed in claim 5, wherein the logic control apparatus comprises:
a first logic unit connected between the slave selection lines of the N hosts and the slave selection lines of the M slaves;
a second logic unit connected between the clock lines of the N hosts and the clock lines of the M slaves;
a third logic unit connected between the master output slave input line of the N masters and the master output slave input line of the M slaves;
the fourth logic unit is connected between the master input and slave output lines of the N masters and the master input and slave output lines of the M slaves; and
a selection unit, which is respectively connected with the first logic unit, the second logic unit, the third logic unit and the fourth logic unit;
the logical relations among the first logical unit, the second logical unit, the third logical unit and the fourth logical unit jointly define each master-slave connection relation among the N hosts and the M slaves, and the selection unit determines to select one of the master-slave connection relations, wherein each master-slave connection relation is that each master simultaneously and respectively transmits information only with one of the slaves which is different.
7. The master-slave system with logic control device according to claim 6, wherein the logic control device is a programmable logic device or a simple programmable logic device, and the first logic unit, the second logic unit, the third logic unit and the fourth logic unit are a first lookup table set, a second lookup table set, a third lookup table set and a fourth lookup table set of the programmable logic device or the simple programmable logic device, each of the lookup table sets has S lookup tables, wherein S is greater than or equal to M.
8. The master-slave system with logic control device according to claim 7, wherein when N and M are equal to two, the two masters and the two slaves are respectively defined as a first master, a second master, a first slave and a second slave, and the first lookup table set, the second lookup table set, the third lookup table set and the fourth lookup table set respectively have two lookup tables, and a first master-slave connection relationship and a second master-slave connection relationship are defined, the first master-slave connection relationship is that the first master is connected to the first slave, and the second master is connected to the second slave, the second master-slave connection relationship is that the first master is connected to the second slave, and the second master is connected to the first slave.
9. The master-slave system with logic control device according to claim 8, wherein the logic control device further comprises a switch unit, the switch unit is provided between the M slaves and the first logic unit, the second logic unit, the third logic unit, and between the N masters and the fourth logic unit, when the switch unit is in an on state, the logic control device is capable of outputting signals to the first logic unit, the second logic unit, the third logic unit, and the fourth logic unit, and when the switch unit is in an off state, the logic control device is incapable of outputting signals to the first logic unit, the second logic unit, the third logic unit, and the fourth logic unit.
10. A switching method of master-slave system with logic control device is characterized by comprising the following steps:
providing N hosts, M slaves and a logic control device for connection, wherein the logic control device is provided with a first logic unit, a second logic unit, a third logic unit and a fourth logic unit for logic relationship, and defining a plurality of master-slave connection relationships between the N hosts and the M slaves together, each master-slave connection relationship is that each host only transmits information with one different slave at the same time, and N and M are integers greater than or equal to two;
a selection unit arranged in the logic control device selects one of the master-slave connection relations; and
the logic control device enables each master machine to simultaneously transmit information with only one different slave machine according to the selected master-slave connection relation.
11. The method as claimed in claim 10, wherein the logic control device further comprises a switch unit connected between the M slaves and the first, second, and third logic units, and between the N masters and the fourth logic unit, and the logic control device processes the following steps:
confirming whether the switch unit is in an on or off state;
when the switch unit is in an on state, the logic control device allows each host to transmit information to each slave through the first logic unit, the second logic unit and the third logic unit, and allows each slave to transmit information to each host through the fourth logic unit; and
when the switch unit is in the off state, the logic control device stops each master from transmitting information to each slave through the first logic unit, the second logic unit and the third logic unit, and stops each slave from transmitting information to each master through the fourth logic unit.
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| CN202211287515.5A CN115826450A (en) | 2022-10-20 | 2022-10-20 | Logic control device of serial peripheral interface, master-slave system and master-slave switching method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116909975A (en) * | 2023-09-12 | 2023-10-20 | 苏州浪潮智能科技有限公司 | Multi-master multi-slave interaction control system of serial bus standard |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116909975A (en) * | 2023-09-12 | 2023-10-20 | 苏州浪潮智能科技有限公司 | Multi-master multi-slave interaction control system of serial bus standard |
| CN116909975B (en) * | 2023-09-12 | 2024-01-26 | 苏州浪潮智能科技有限公司 | Multi-master multi-slave interaction control system of serial bus standard |
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