CN114265731A

CN114265731A - PCIE interface verification board, test system and test method

Info

Publication number: CN114265731A
Application number: CN202111538400.4A
Authority: CN
Inventors: 李晶晶; 杨晓君; 陈浩; 陈杰; 张腾
Original assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2021-12-15
Filing date: 2021-12-15
Publication date: 2022-04-01

Abstract

The invention provides a PCIE interface verification board, a test system and a test method. At least one switching chip is arranged on the circuit board, and each switching chip is connected with the first PCIE connector. The circuit board is also provided with at least two second PCIE plug connectors, and each second PCIE plug connector is connected with one switching chip. And at least two second PCIE connector clips are connected with a plurality of PCIE devices. The plurality of PCIE devices correspond to the plurality of PCIE ports configured on the PCIE interface to be tested one by one, and the at least one switching chip is used for configuring each PCIE device to be in communication connection with the corresponding PCIE port. The method and the device can simultaneously test a plurality of PCIE ports configured by the PCIE interface to be tested under a configuration type, reduce the deviation between test data and practical application, and improve the accuracy and reliability of the test data. The number of testing PCIE ports is reduced, the testing efficiency is improved, and time and labor are saved.

Description

PCIE interface verification board, test system and test method

Technical Field

The invention relates to the technical field of computers, in particular to a PCIE interface verification board, a test system and a test method.

Background

The mainboard is used as an important device in the computer and directly influences the performance of the computer such as calculation, data transmission and the like. A PCIE (Peripheral Component Interconnect Express) slot is usually disposed on the motherboard to plug different PCIE devices. Generally, only one PCIE device can be plugged into one PCIE slot, but when the channel width required by the PCIE device is smaller than the channel width of the PCIE slot, the channel waste phenomenon of the PCIE slot is caused. For this reason, a design manner exists in the prior art in which a plurality of PCIE ports are configured in one PCIE slot, and each PCIE port is connected to one PCIE device, so that a phenomenon of channel waste of the PCIE slot is improved.

At present, when a design manner that a plurality of PCIE ports are configured for one PCIE slot is tested, the prior art still adopts a conventional test manner, and first determines a configuration type that the PCIE slot configures the plurality of PCIE ports, and then tests only one PCIE port at a time, and successively tests all PCIE ports in the configuration type. And then, changing the configuration types of the plurality of PCIE ports configured by the PCIE slot, and testing all the PCIE ports under the new configuration type one by one. Because one PCIE slot has a plurality of configuration types for configuring a plurality of PCIE ports, and each configuration type comprises a plurality of PCIE ports, the times for testing the PCIE ports are increased in geometric multiples, time and labor are consumed, the plurality of PCIE ports configured in the whole PCIE slot cannot be tested simultaneously, the test data has deviation with the actual application effect, and the accuracy and the reliability of the test data are reduced.

Disclosure of Invention

The invention provides a PCIE interface verification board, a test system and a test method, which are used for reducing the number of testing PCIE ports, improving the test efficiency and saving time and labor; and a plurality of PCIE ports configured on the whole PCIE interface can be tested simultaneously, so that the deviation between the test data and the actual application effect is reduced, and the accuracy and the reliability of the test data are improved.

In a first aspect, the present invention provides a PCIE interface verification board, where the PCIE interface verification board is used to test a single PCIE interface configured as multiple PCIE ports. The PCIE interface verification board comprises a circuit board and a first PCIE connector arranged on the circuit board, wherein the first PCIE connector is used for being connected with a PCIE interface to be tested in an inserting mode. At least one switching chip is arranged on the circuit board, and each switching chip is connected with the first PCIE connector. The circuit board is also provided with at least two second PCIE plug connectors, each second PCIE plug connector is connected with one switching chip, and each switching chip is connected with at least one second PCIE plug connector. The at least two second PCIE connector assemblies are used for being connected with a plurality of PCIE devices in an inserting mode, each PCIE device is connected to one second PCIE connector assembly in an inserting mode, and at most one PCIE device is connected to each second PCIE connector assembly in an inserting mode. The plurality of PCIE devices correspond to the plurality of PCIE ports configured on the PCIE interface to be tested one by one, and the at least one switching chip is used for configuring each PCIE device to be in communication connection with the corresponding PCIE port.

In the above scheme, one PCIE interface verification board is designed as a switching device connected between a PCIE interface to be tested and a plurality of PCIE devices, so that at least one switching chip configures each PCIE device for communication connection with a corresponding PCIE port by controlling on/off between the first PCIE plug connector and each second PCIE plug connector, thereby simultaneously testing a plurality of PCIE ports configured by the PCIE interface to be tested in one configuration type, making a test scenario very close to an actual application scenario, thereby reducing a deviation between the test data and the actual application effect, and improving accuracy and reliability of the test data. And because a plurality of PCIE ports under the same configuration type can be tested at the same time, the testing of single PCIE ports under the same configuration type is not needed one by one, the times of testing the PCIE ports are reduced, the testing efficiency is improved, and the time and the labor are saved.

In a specific embodiment, the channel width of the first PCIE connector is equal to the channel width of the PCIE interface to be tested, so that the channel width of the first PCIE connector can completely cover the channel width of the PCIE interface to be tested, and the channel width of the first PCIE connector is not wasted. The width of the channels of the at least two second PCIE connectors is equal, so that when the PCIE equipment is connected to the at least two second PCIE connectors, each PCIE equipment can be connected to one second PCIE connector at will, and communication connection between each PCIE equipment and the corresponding PCIE port can be completed only by identifying and matching the switching chips, so that extra connection limitation is not required.

In a specific embodiment, the channel width of each second PCIE connector is equal to the channel width of the PCIE interface to be tested. Or the channel width of each second PCIE connector is half of the channel width of the PCIE interface to be tested. And the second PCIE connector can test the PCIE interfaces to be tested under all the configuration types.

In a specific embodiment, the channel width of the PCIE interface to be tested is X4, X8, or X16. The lane width of each second PCIE jack is X2, X4, X8, or X16. So as to meet the requirement of testing common types of PCIE interfaces.

In a specific embodiment, the circuit board is further provided with a first interface and a storage module connected with each switching chip. The first interface is used for receiving the configuration firmware and writing the configuration firmware into the storage module. Each switching chip is used for operating the configuration firmware in the storage module, controlling the connection or disconnection of the first PCIE plug connector and each second PCIE plug connector, and configuring each PCIE device to be in communication connection with the corresponding PCIE port. In order to save and run different types of configuration firmware.

In one embodiment, the memory module is a flash read-only programmer to increase the read speed of the configuration firmware and improve the test efficiency.

In one embodiment, a complex programmable logic device is also disposed on the circuit board. The complex programmable logic device is connected with each exchange chip to control the power-on, error alarm, on-site detection or reset of each exchange chip. So as to power on the exchange chip, give an alarm by mistake, detect or reset in place, etc.

In a specific implementation manner, the circuit board is further provided with a second interface and a JTAG (Joint Test Action Group, an international standard Test protocol) interface, both of which are connected to the complex programmable logic device, wherein the second interface is used for connecting with a substrate management controller on the motherboard to enable the substrate management controller to perform information interaction with the complex programmable logic device.

In a specific embodiment, a clock buffer and a third interface connected with the clock buffer are further arranged on the circuit board. The third interface is used for receiving a clock signal generated by a central processing unit connected with the PCIE interface to be tested. And a clock buffer is connected to each switch chip to transmit a clock signal to each switch chip. A plurality of PCIE equipment connected to the second PCIE connector clip adopt the design of the same source clock, and are closer to the practical application scene, so that the deviation between the test data and the practical application effect is further reduced, and the accuracy and the reliability of the test data are further improved.

In a second aspect, the present invention further provides a PCIE interface test system. The PCIE interface test system comprises a mainboard, a central processing unit located on the mainboard and at least one PCIE interface to be tested located on the mainboard and connected with the central processing unit, wherein each PCIE interface to be tested is supported and configured to be a plurality of PCIE ports. The PCIE interface testing system also comprises any one of the PCIE interface verification boards and a plurality of PCIE devices which are plugged in at least two second PCIE plug-in components.

In a third aspect, the present invention further provides a PCIE interface test method based on any one of the PCIE interface verification boards described above, where the test method is used to test a single PCIE interface supporting configuration as multiple PCIE ports. The test method comprises the following steps: inserting a PCIE interface to be tested into a first PCIE connector; a plurality of PCIE devices are connected with at least two second PCIE connectors in an inserting mode; and at least one switching chip configures each PCIE device to be in communication connection with a corresponding PCIE port.

Drawings

Fig. 1 is an overall topology block diagram of a PCIE interface verification board according to an embodiment of the present invention;

fig. 2 is an overall topology block diagram of another PCIE interface verification board according to the embodiment of the present invention;

fig. 3 is a topology diagram of a connection manner of a switch chip according to an embodiment of the present invention;

fig. 4 is a topology diagram of a connection manner of a complex programmable logic device according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a clock buffer according to an embodiment of the present invention;

fig. 6 is a schematic configuration diagram of configuring a plurality of PCIE ports for a PCIE interface to be tested according to an embodiment of the present invention.

Reference numerals:

10-circuit board 11-first PCIE connector 12-second PCIE connector

20-exchange chip 21-first interface 22-storage module

30-complex programmable logic device 31-second interface 32-JTAG interface

40-clock buffer 41-third interface 50-baseboard management controller

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To facilitate understanding of the PCIE interface verification board provided in the embodiment of the present invention, an application scenario of the PCIE interface verification board provided in the embodiment of the present invention is described below, where the PCIE interface verification board is used to test a single PCIE interface configured as multiple PCIE ports, the PCIE interface to be tested is located on a motherboard and connected to a central processing unit on the motherboard, and the central processing unit configures the PCIE interface to be tested into multiple PCIE ports. The PCIE interface verification board is described in detail below with reference to the accompanying drawings.

Referring to fig. 1 and fig. 2, a PCIE interface verification board provided in the embodiment of the present invention includes a circuit board 10 and a first PCIE plug connector 11 disposed on the circuit board 10, where the first PCIE plug connector 11 is used to be plugged into a PCIE interface to be tested. At least one switching chip 20 is disposed on the circuit board 10, and each switching chip 20 is connected to the first PCIE connector 11. At least two second PCIE connectors 12 are further disposed on the circuit board 10, each second PCIE connector 12 is connected to one switch chip 20, and each switch chip 20 is connected to at least one second PCIE connector 12. At least two second PCIE plug connectors 12 are used to plug a plurality of PCIE devices, each PCIE device is plugged into one second PCIE plug connector 12, and at most one PCIE device is plugged into each second PCIE plug connector 12. The plurality of PCIE devices correspond to the plurality of PCIE ports configured on the PCIE interface to be tested one to one, and the at least one switch chip 20 is configured to configure each PCIE device to be in communication connection with the corresponding PCIE port.

In the above scheme, one PCIE interface verification board is designed as a switching device for connecting between a PCIE interface to be tested and a plurality of PCIE devices, so that at least one switching chip 20 configures each PCIE device to be in communication connection with a corresponding PCIE port by controlling on/off between the first PCIE plug connector 11 and each second PCIE plug connector 12, thereby simultaneously testing a plurality of PCIE ports configured by the PCIE interface to be tested in a configuration type, making a test scenario very close to an actual application scenario, thereby reducing a deviation between test data and an actual application effect, and improving accuracy and reliability of the test data. And because a plurality of PCIE ports under the same configuration type can be tested at the same time, the testing of single PCIE ports under the same configuration type is not needed one by one, the times of testing the PCIE ports are reduced, the testing efficiency is improved, and the time and the labor are saved. The above-described respective structures will be described in detail with reference to the accompanying drawings.

When the circuit board 10 is disposed, referring to fig. 1, the circuit board 10 serves as a supporting and interconnecting structure for disposing devices such as PCIE plug connectors and the switching chip 20, and the printed circuit board 10 may be employed as the circuit board 10, and the devices such as PCIE plug connectors and the switching chip 20 are disposed on the circuit board 10 and interconnected through traces and vias on the circuit board 10 or in the circuit board 10.

As shown in fig. 1 and fig. 2, a first PCIE connector 11 is disposed on a circuit board 10, and the first PCIE connector 11 is used for being connected to a PCIE interface to be tested in an inserting manner, so as to implement connection between a PCIE interface verification board and a PCIE to be tested. The channel width of the PCIE interface to be tested may be X4, X8, or X16, or the like. When determining the channel width of the first PCIE connector 11, it is necessary to ensure that the channel width of the first PCIE connector 11 can completely cover the channel width of the PCIE interface to be tested. For example, the channel width of the first PCIE connector 11 may be equal to the channel width of the PCIE interface to be tested, so as not to waste the channel width of the first PCIE connector 11. For example, as shown in fig. 1, the channel width of the first PCIE connector 11 is X16, and the channel width of the PCIE interface to be tested is also X16. Of course, the channel width of the first PCIE connector 11 may also be greater than the channel width of the PCIE interface to be tested, so as to ensure that the channel width of the first PCIE connector 11 can completely cover the channel width of the PCIE interface to be tested.

Referring to fig. 1, at least one switching chip 20 is disposed on a circuit board 10, and each switching chip 20 is connected to a first PCIE connector 11, so as to implement connection with a PCIE interface to be tested through the first PCIE connector 11. The circuit board 10 shown in fig. 1 is provided with a switching chip 20; two switching chips 20 are provided on the circuit board 10 as shown in fig. 2. It should be understood that the number of the switch chips 20 is not limited to 1 or 2, and besides, the number of the switch chips 20 may be any value not less than 3, such as 3, 4, etc. As shown in fig. 1 and fig. 2, at least two second PCIE connectors 12 are further disposed on the circuit board 10, each second PCIE connector 12 is connected to one switch chip 20, and each switch chip 20 is connected to at least one second PCIE connector 12. That is, the number of each switch chip 20 connected to the second PCIE connector 12 may be one, or may be any value not less than two, such as two, three, four, and the like. However, each second PCIE connector 12 is connected to only one switch chip 20, and is not connected to other switch chips 20. When determining the number of the second PCIE connectors 12, the number of the second PCIE connectors 12 may be any value not less than 2, such as 2, 3, 4, 5, 6, 7, 8, 9, or 10.

When determining the channel widths of the at least two second PCIE plug connectors 12, the channel widths of the at least two second PCIE plug connectors 12 may be equal, so that when a PCIE device is plugged into the at least two second PCIE plug connectors 12, each PCIE device may be plugged into one second PCIE plug connector 12 at will, and only the exchange chip 20 needs to identify and pair, so as to complete the communication connection between each PCIE device and the corresponding PCIE port, thereby avoiding the need of additional plugging restriction. Of course, the channel widths of the at least two second PCIE connectors 12 are not limited to the same arrangement, and other arrangements may be adopted. For example, the channel widths of part of the second PCIE plug 12 may be equal, and the channel widths of part of the second PCIE plug 12 are not equal; or the lane widths of all the second PCIE connectors 12 are not equal.

In addition, the channel width of each second PCIE connector 12 may be equal to the channel width of the PCIE interface to be tested, so as to ensure that the PCIE device can be plugged into each second PCIE connector 12. Of course, the channel width of each second PCIE connector 12 may also be half of the channel width of the PCIE interface to be tested. The second PCIE connector 12 can test PCIE interfaces to be tested in all configuration types. The channel width of each second PCIE connector 12 may be X2, X4, X8, or X16. So as to meet the requirement of testing common types of PCIE interfaces. It should be understood that the arrangement of the channel width of the second PCIE connector 12 is not limited to the above-described arrangement, and other arrangements may be adopted.

The number of the second PCIE connectors 12 is specifically related to the number of the largest PCIE ports that can be configured for the PCIE interface to be tested, of the central processing units connected to the PCIE interface to be tested. In an optimal implementation manner, the number of the second PCIE connectors 12 needs to be at least not less than the maximum number of PCIE ports that can be configured by the central processing unit to the PCIE interface to be tested. The central processing unit directly determines the number of the PCIE ports of the PCIE interface to be tested, wherein the number of the PCIE ports of the PCIE interface to be tested can be configured. The channel width of the PCIE interface to be tested shown in fig. 6 is X16. The PCIE port types configured by the central processing unit for the PCIE interface to be tested may be X8, X4, X2, X1, and the like. As shown in fig. 6, 3 PCIE ports with a channel width of X4 and 2 PCIE ports with a channel width of X2 are configured for the PCIE interface to be tested. For a PCIE interface to be tested with a channel width of n, if the minimum channel width of a PCIE port that can be configured by the central processing unit for the PCIE interface to be tested is X2, the PCIE interface to be tested can be configured with n/2 PCIE ports at most, and it is necessary to ensure that the number of the second PCIE plug connectors 12 is more than n/2 as far as possible. If the minimum channel width of the PCIE port that can be configured by the central processing for the PCIE interface to be tested is X1, the PCIE interface to be tested can be configured with n PCIE ports at most, and it is necessary to ensure that the number of the second PCIE plug connectors 12 is more than n as much as possible.

The number of the switch chips 20 is specifically related to the maximum number of PCIE ports that can be configured for the PCIE interface to be tested, according to the central processing unit that is also connected to the PCIE interface to be tested. When the PCIE interface to be tested can be configured with more PCIE ports by the central processing unit, the number of the switch chips 20 needs to be set more; when the PCIE interface to be tested can be configured with fewer PCIE ports by the central processing unit, the number of the switch chips 20 may be less. The number of the switch chips 20 is also related to the maximum number of ports supported by each switch chip 20, for example, the number of the downlink PCIE ports supported by some switch chips 20 is 4, and the number of the downlink PCIE ports supported by some switch chips 20 is 8. However, under the same PCIE interface to be tested, since the number of downlink PCIE ports supported by different switch chips 20 is different, the number of the switch chips 20 used is also different.

During specific testing, at least two second PCIE plug connectors 12 are plugged with a plurality of PCIE devices, each PCIE device is plugged into one second PCIE plug connector 12, and at most one PCIE device is plugged into each second PCIE plug connector 12. The plurality of PCIE devices correspond to the plurality of PCIE ports configured on the PCIE interface to be tested one to one, and the at least one switch chip 20 configures each PCIE device to be in communication connection with the corresponding PCIE port. Through designing a PCIE interface verification board as the switching equipment for connecting the PCIE interface to be tested and a plurality of PCIE devices, at least one switching chip 20 is enabled to configure each PCIE device and the corresponding PCIE port for communication connection by controlling the connection or disconnection between the first PCIE connector 11 and each second PCIE connector 12, so that a plurality of PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, a test scene is very close to an actual application scene, the deviation existing between the test data and the actual application effect is reduced, and the accuracy and the reliability of the test data are improved. And because a plurality of PCIE ports under the same configuration type can be tested at the same time, the testing of single PCIE ports under the same configuration type is not needed one by one, the times of testing the PCIE ports are reduced, the testing efficiency is improved, and the time and the labor are saved.

In the following, by taking the channel width of the PCIE interface to be tested shown in fig. 2 as X16, two switch chips 20 are disposed on the circuit board 10, and each switch chip 20 is connected to four second PCIE plug connectors 12 with the channel width of X16, as an example, several configuration schemes are shown.

In example 1, the central processing unit can configure 4 PCIE ports with channel widths of X4 for the PCIE interface to be tested in fig. 2. At this time, the number of the PCIE devices plugged into the second PCIE plug 12 is also four, and the channel width of each PCIE device is also X4, and obviously, the PCIE device of X4 can be plugged into the second PCIE plug 12 of X16. At this time, it is sufficient that four PCIE devices are all plugged into four second PCIE plug connectors 12 under any one of the switch chips 20, so that the requirement of simultaneously testing 4X 4 PCIE ports configured on the PCIE interface to be tested can be met. Certainly, two PCIE devices may also be plugged into any two second PCIE connectors 12 under one of the switch chips 20, and two other PCIE devices may also be plugged into any two second PCIE connectors 12 under another switch chip 20, so as to meet the requirement of simultaneously testing 4 PCIE ports of X4 configured on a PCIE interface to be tested.

In example 2, the central processing unit can configure 1 PCIE port whose channel width is X4 and 6 PCIE ports whose channel width is X2 for the PCIE interface to be tested shown in fig. 2. At this time, the number of the PCIE devices plugged into the second PCIE connector 12 is seven, the channel width of one PCIE device among the seven PCIE devices is X4, and the channel widths of the other six PCIE devices are all X2, and obviously, the PCIE device of X4 or X2 can be plugged into the second PCIE connector 12 of X16. At this time, four PCIE devices of X2 may be plugged into four second PCIE connectors 12 under one of the switch chips 20, and another two PCIE devices of X2 and one PCIE device of X4 may be plugged into any three second PCIE connectors 12 under another one of the switch chips 20, so as to meet the requirement of testing the PCIE ports of 6X 2 and 1X 4 configured on the PCIE interface to be tested at the same time.

Referring to fig. 1, 2 and 3, a first interface 21 and a memory module 22 connected to each switching chip 20 may be further provided on the circuit board 10. The first interface 21 is configured to receive the configuration firmware and write the configuration firmware into the storage module 22. Each switch chip 20 is configured to run configuration firmware in the storage module 22, and control the on/off of the first PCIE connector 11 and each second PCIE connector 12, so as to configure each PCIE device to be in communication connection with a corresponding PCIE port. In order to save and run different types of configuration firmware. When determining the memory module 22, a flash read-only programmer may be used as the memory module 22 to increase the operation reading speed of the configuration firmware and improve the test efficiency. It should be understood that the memory module 22 is not limited to the use of a flash read-only programmer, and other types of storage media may be used as the memory module 22. Referring to fig. 1, the switch chip 20 may be connected to the memory module 22 through an Interface such as, but not limited to, an SPI (Serial Peripheral Interface) Interface. With continued reference to fig. 1, the first interface 21 may be an interface type such as, but not limited to, an SDB (Smart Deep Buffer) interface, a UART (Universal Asynchronous Receiver/Transmitter) interface, and the like.

Referring to fig. 1 and 4, a complex programmable logic device 30 may be further disposed on the circuit board 10, and the complex programmable logic device 30 is connected to each switch chip 20 to control functions of powering on, false alarm, on-site detection or reset of each switch chip 20. Specifically, referring to fig. 1, PWR _ PGD represents a power ground signal, PEX _ ERROR _ N represents an ERROR alarm signal of the nth switch chip 20, PRESENT _ SLOT _ N represents an in-place detection signal of the nth second PCIE plug 12, PWEON _ RST _ PEX _ N represents a restart power-up signal of the nth switch chip 20, and RST _ SLOT _ N represents a reset signal of the nth second PCIE plug 12. To power up the switch chip 20, to alarm for errors, to detect or reset in place, etc. In addition, as shown in fig. 1 and 4, a second interface 31 and a JTAG interface 32 connected to both the complex programmable logic device 30 may be further provided on the circuit board 10. The second interface 31 is used for connecting with a baseboard management controller 50 on the motherboard, so that the baseboard management controller 50 and the complex programmable logic device 30 perform information interaction. The second interface 31 may employ a communication interface such as, but not limited to, an I2C interface. JTAG interface 32 is used to update firmware within complex programmable logic device 30. When a JTAG interface is reserved on the motherboard, the JTAG interface 32 on the motherboard can be connected to the JTAG interface 32 on the PCIE interface verification board, so that the firmware in the complex programmable logic device 30 can be updated through the substrate management controller 50 on the motherboard. Through the above manner, information interaction can be performed with the baseboard management controller 50 on the motherboard in the testing process, and meanwhile, updating of firmware in the complex programmable logic device 30 is facilitated.

Referring to fig. 1 and 5, a clock buffer 40 and a third interface 41 connected to the clock buffer 40 may be further provided on the circuit board 10. The third interface 41 is configured to receive a clock signal generated by a central processing unit connected to the PCIE interface to be tested. As shown in fig. 1, CLK _100M (a clock signal) output from the first interface 41 is transmitted to the clock buffer 40. And a clock buffer 40 is connected to each of the switch chips 20 to transmit a clock signal to each of the switch chips 20. That is, the switching chip 20 on the circuit board 10 and the PCIE devices connected to the downlink port of the switching chip 20 adopt a same source clock design, so that the CPU differential clock signal of the central processing unit is connected to the clock buffer 40 sequentially through the traces on the motherboard, the third interface 41, and the traces on the circuit board 10, and the various types of CLK _100M pushed out by the clock buffer 40 are connected to the switching chip 20 and each second PCIE plug 12, thereby realizing that a same source clock signal is adopted between the switching chip 20 and the PCIE devices. Specifically, the various types of CLK _100M pushed out from the clock buffer 40 may be CLK _100M _ SLOT 0-n (respectively representing clock signals transmitted to different second PCIE connectors 12) and CLK _100M _ PEX (representing clock signals transmitted to the switch chip 20) as shown in fig. 1.

The plurality of PCIE devices connected to the second PCIE plug connector 12 adopt a homologous clock design, and are closer to an actual application scenario, so that the deviation between the test data and the actual application effect is further reduced, and the accuracy and reliability of the test data are further improved.

Through designing a PCIE interface verification board as the switching equipment for connecting the PCIE interface to be tested and a plurality of PCIE devices, at least one switching chip 20 is enabled to configure each PCIE device and the corresponding PCIE port for communication connection by controlling the connection or disconnection between the first PCIE connector 11 and each second PCIE connector 12, so that a plurality of PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, a test scene is very close to an actual application scene, the deviation existing between the test data and the actual application effect is reduced, and the accuracy and the reliability of the test data are improved. And because a plurality of PCIE ports under the same configuration type can be tested at the same time, the testing of single PCIE ports under the same configuration type is not needed one by one, the times of testing the PCIE ports are reduced, the testing efficiency is improved, and the time and the labor are saved.

In addition, the embodiment of the invention also provides a PCIE interface test system. The PCIE interface test system comprises a mainboard, a central processing unit positioned on the mainboard and at least one PCIE interface to be tested, which is positioned on the mainboard and is connected with the central processing unit. Specifically, the number of the PCIE interfaces to be tested that can be included in the motherboard can be any number, such as 1, 2, 3, 4, and each PCIE interface to be tested supports configuration as multiple PCIE ports. Referring to fig. 1 and fig. 2, the PCIE interface test system further includes any one of the PCIE interface verification boards described above, and a plurality of PCIE devices plugged in at least two second PCIE plug connectors 12. Through designing a PCIE interface verification board as the switching equipment for connecting the PCIE interface to be tested and a plurality of PCIE devices, at least one switching chip 20 is enabled to configure each PCIE device and the corresponding PCIE port for communication connection by controlling the connection or disconnection between the first PCIE connector 11 and each second PCIE connector 12, so that a plurality of PCIE ports configured by the PCIE interface to be tested under a configuration type can be tested simultaneously, a test scene is very close to an actual application scene, the deviation existing between the test data and the actual application effect is reduced, and the accuracy and the reliability of the test data are improved. And because a plurality of PCIE ports under the same configuration type can be tested at the same time, the testing of single PCIE ports under the same configuration type is not needed one by one, the times of testing the PCIE ports are reduced, the testing efficiency is improved, and the time and the labor are saved.

In addition, as described in the foregoing PCIE interface verification board portion, referring to fig. 1 and fig. 4, a baseboard management controller 50 may be further disposed on the motherboard, and the baseboard management controller 50 may be connected to the complex programmable logic device 30 on the circuit board 10 through the second interface 31 on the circuit board 10, so that the baseboard management controller 50 and the complex programmable logic device 30 perform information interaction.

Moreover, the invention also provides a PCIE interface testing method based on any one of the PCIE interface verification boards, and the testing method is used for testing a single PCIE interface supporting configuration as a plurality of PCIE ports. Referring to fig. 1 and 2, the testing method includes:

the PCIE interface to be tested is connected with a first PCIE connector 11 in an inserting mode;

a plurality of PCIE devices are connected to the at least two second PCIE connectors 12;

at least one switch chip 20 configures each PCIE device to be in communication connection with a corresponding PCIE port. For a specific implementation manner of configuring each PCIE device to be in communication connection with a corresponding PCIE port, reference is made to the description about the PCIE interface verification board portion, which is not described herein again.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A PCIE interface verification board is used for testing a single PCIE interface which supports configuration as multiple PCIE ports, and is characterized by comprising:

a circuit board;

the first PCIE connector is arranged on the circuit board and used for being connected with a PCIE interface to be tested in an inserting mode;

at least one switching chip disposed on the circuit board; each switching chip is connected with the first PCIE connector;

the switching chip comprises at least two second PCIE plug connectors arranged on the circuit board, wherein each second PCIE plug connector is connected with one switching chip, and each switching chip is connected with at least one second PCIE plug connector;

the at least two second PCIE connector components are used for inserting a plurality of PCIE devices, each PCIE device is inserted on one second PCIE connector component, and each second PCIE connector component is inserted with one PCIE device at most;

the plurality of PCIE devices correspond to the plurality of PCIE ports configured on the PCIE interface to be tested one by one, and the at least one switching chip is used for configuring each PCIE device to be in communication connection with the corresponding PCIE port.

2. The PCIE interface verification board of claim 1, wherein the channel width of the first PCIE plug connector is equal to the channel width of the PCIE interface to be tested; the channel widths of the at least two second PCIE plug connectors are equal.

3. The PCIE interface verification board of claim 2, wherein the channel width of each second PCIE plug connector is equal to the channel width of the PCIE interface to be tested; or the like, or, alternatively,

and the channel width of each second PCIE connector is half of the channel width of the PCIE interface to be tested.

4. The PCIE verification board of claim 1, wherein the channel width of the PCIE interface to be tested is X4, X8, or X16;

the lane width of each second PCIE jack is X2, X4, X8, or X16.

5. The PCIE interface verification board of claim 1, wherein the circuit board is further provided with a first interface and a storage module connected to each switch chip;

the first interface is used for receiving configuration firmware and writing the configuration firmware into the storage module;

each switching chip is used for operating the configuration firmware in the storage module, and controlling the connection or disconnection of the first PCIE plug connector and each second PCIE plug connector so as to configure each PCIE device to be in communication connection with the corresponding PCIE port.

6. The PCIE interface verification board of claim 5, wherein the memory module is a flash read-only programmer.

7. The PCIE interface verification board of claim 1, wherein the circuit board is further provided with a complex programmable logic device;

the complex programmable logic device is connected with each switching chip to control the power-on, error alarm, in-place detection or reset of each switching chip.

8. The PCIE interface verification board of claim 7, wherein the circuit board is further provided with a second interface and a JTAG interface both connected to the complex programmable logic device;

the second interface is used for being connected with a substrate management controller on a mainboard, so that the substrate management controller and the complex programmable logic device carry out information interaction;

the JTAG interface is used for updating the firmware in the complex programmable logic device.

9. The PCIE interface verification board of claim 1, wherein the circuit board is further provided with a clock buffer and a third interface connected to the clock buffer;

the third interface is used for receiving a clock signal generated by a central processing unit connected with the PCIE interface to be tested;

and the clock buffer is connected with each switching chip to transmit the clock signal to each switching chip.

10. A PCIE interface test system is characterized by comprising:

a main board;

a central processing unit located on the motherboard;

the system comprises at least one PCIE interface to be tested, a central processing unit and a plurality of PCIE ports, wherein the PCIE interfaces to be tested are positioned on the mainboard and are connected with the central processing unit, and each PCIE interface to be tested supports configuration as a plurality of PCIE ports;

the PCIE interface verification board of any one of claims 1 to 9;

and the plurality of PCIE equipment is spliced on the at least two second PCIE connectors.

11. A PCIE interface test method based on the PCIE interface verification board according to any one of claims 1 to 9, configured to test a single PCIE interface configured as a multiple PCIE port, including:

inserting a PCIE interface to be tested into a first PCIE connector;

a plurality of PCIE devices are connected with at least two second PCIE connectors in an inserting mode;

and at least one switching chip configures each PCIE device to be in communication connection with a corresponding PCIE port.