CN112951315A - NVME \ AHCI compatible dual-protocol hard disk testing device and method - Google Patents
NVME \ AHCI compatible dual-protocol hard disk testing device and method Download PDFInfo
- Publication number
- CN112951315A CN112951315A CN202110220895.XA CN202110220895A CN112951315A CN 112951315 A CN112951315 A CN 112951315A CN 202110220895 A CN202110220895 A CN 202110220895A CN 112951315 A CN112951315 A CN 112951315A
- Authority
- CN
- China
- Prior art keywords
- hard disk
- protocol type
- type hard
- protocol
- nvme
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims description 12
- 238000004891 communication Methods 0.000 claims description 26
- 238000012545 processing Methods 0.000 claims description 13
- 230000009977 dual effect Effects 0.000 claims description 5
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 3
- 230000009131 signaling function Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
Abstract
The invention provides a double-protocol hard disk testing device compatible with NVME \ AHCI, which comprises: the device comprises a controller, a first hard disk connector, a second hard disk connector and a protocol switching module, wherein the first hard disk connector is connected with a first protocol type hard disk, and the second hard disk connector is connected with a second protocol type hard disk; the controller judges whether the current first protocol type hard disk is set to be in a working state or not according to the RST signal level of the first protocol type hard disk, and controls the working switching of the first protocol type hard disk and the second protocol type hard disk through the protocol switching module.
Description
Technical Field
The invention relates to the field of hard disk testers, in particular to a device and a method for testing a dual-protocol hard disk compatible with NVME \ AHCI.
Background
Under the conditions of more and more powerful requirements on functions of the server and higher and more integration level, along with the rapid development of social informatization, the data volume is also larger and larger, the requirements of enterprises on storage capacity and flexibility of storage are more and more prominent, high-end storage is more and more on paper, and the hard disk compatible with the hard disk backplanes of different protocols are more and more applied to the industry of the server. Among them, NVME (Non-Volatile Memory) and SATA (Serial Advanced Technology Attachment) hard disks, which are mainstream applications for storage medium communication, are widely used in storage media of servers, and each hard disk has its own communication interface protocol, and under different communication interface protocols, each hard disk has different communication data transmission modes. PCIE (peripheral component interconnect express, which is a high-speed serial computer expansion bus standard) is the latest bus and interface standard, and belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, connected devices allocate independent channel bandwidth, do not share bus bandwidth, and PCIE bus frequency is increased: the data transmission rate of each serial line is doubled from 2.5Gbps to 5Gbps, and the bandwidth is doubled accordingly. PCIE is actually a channel protocol and is directly connected with a PCIE interface on a mainboard, so that almost no delay exists, the PCIE is a good partner of an NVME standard, an NVME hard disk is a hard disk based on a nonvolatile memory, the solid state hard disk interface is directly connected with a CPU bus, the transmission rate of the solid state hard disk is improved, the transmission loss is greatly reduced, and the NVME is a general solution for the performance of a high-end flagship in the current solid state hard disk industry. SATA is a physical Interface type, and an executed AHCI (Advanced Host Controller Interface) protocol standard, is the cheapest and common solid state disk Interface at present, and is also a most direct and most convenient storage implementation method for a plurality of compatibilities of a client.
Aiming at the test principle that the server industry supports both NVME and SATA hard disk backplanes, function realization and detection under multiple modes of NVEM and SATA are required to be covered, but the current test realization principle is that firstly, an NVME hard disk is accessed under an NVME protocol, a system is started to enter a test program, and all functions under the NVME protocol are detected. And (3) powering off the hard disk with the AHCI protocol replaced, powering on again, executing the test program in the SATA mode again in the SATA mode, and realizing all functions in the SATA mode again, thereby completing the test scheme of the hard disk backboard with multiple protocols and multiple compatibility.
The testing scheme greatly increases the testing time, causes a plurality of repeated startup and shutdown actions, increases a plurality of tool consumption, reduces the testing efficiency of a factory end, and increases the time cost, the labor cost and the expense cost.
Disclosure of Invention
In order to solve the problems in the prior art, the invention innovatively provides the NVME \ AHCI compatible dual-protocol hard disk test device and method, so that the test time and the labor cost are reduced, the repeated startup and shutdown is avoided, and the test efficiency is improved.
The invention provides a NVME \ AHCI compatible dual-protocol hard disk testing device in a first aspect, which comprises: the device comprises a controller, a first hard disk connector, a second hard disk connector and a protocol switching module, wherein the first hard disk connector is connected with a first protocol type hard disk, and the second hard disk connector is connected with a second protocol type hard disk; the controller is respectively in communication connection with the first hard disk connector and the second hard disk connector and is used for judging whether the current first protocol type hard disk is set to be in a working state or not according to the RST signal level of the first protocol type hard disk, and controlling the first protocol type hard disk and the second protocol type hard disk to work and switch through the protocol switching module, wherein the first protocol type hard disk is an NVME hard disk, and the second protocol type hard disk is an SATA hard disk.
Optionally, the NVME \ AHCI compatible dual-protocol hard disk test device is in communication connection with the motherboard through a third hard disk connector, a male head of the first hard disk connector is respectively connected to the second hard disk connector and the third hard disk connector, and a female head of the first hard disk connector is in communication connection with the motherboard.
Optionally, the controller includes a communication module, a processing module, and a control module, where the communication module is configured to receive a signal of the first protocol type hard disk and a signal of the second protocol type hard disk; the processing module is connected with the communication module, judges whether the current first protocol type hard disk is set to be in a working state or not according to the received RST signal level of the first protocol type hard disk, and outputs a control corresponding command; the control module is in communication connection with the processing module and controls the protocol switching module to switch the work of the first protocol type hard disk and the second protocol type hard disk according to the received control command of the processing module.
Further, if the RST signal level of the first protocol type hard disk is low level, setting the current first protocol type hard disk to be in a working state, and setting the second protocol type hard disk to be in a non-working state; and if the RST signal level of the first protocol type hard disk is high level, setting the current first protocol type hard disk to be in an inoperative state, and setting the second protocol type hard disk to be in an operative state.
Optionally, the protocol switching module includes a relay and a clock chip, an input end of the relay is connected to the controller, and an output end of the relay is connected to the first hard disk connector and the second hard disk connector, respectively, and is configured to control, according to a control command of the controller, a level of a signal other than the RST signal of the first protocol type hard disk and a level of the RST signal of the second protocol type hard disk; the input end of the clock chip is connected with the controller, the output end of the clock chip is connected with the first hard disk connector, and the clock chip is used for controlling the work switching of the first protocol type hard disk and the second protocol type hard disk according to the control command of the controller.
Further, when the first protocol type hard disk is set to be in a working state, the clock chip opens the check clock signal; when the first protocol type hard disk is set to be in an inoperative state and the second protocol type hard disk is set to be in an operative state, the clock chip is closed to forbid checking the clock signal.
Optionally, the controller is a PSOC controller.
The second aspect of the present invention provides a method for testing a hard disk compatible with NVME \ AHCI dual protocol, which is implemented based on the testing device compatible with NVME \ AHCI dual protocol, and comprises:
the controller receives the RST signal level of the first protocol type hard disk and judges whether the current first protocol type hard disk is set to be in a working state or not according to the RST signal level of the first protocol type hard disk;
if the current first protocol type hard disk is set to be in a working state, the controller controls the protocol switching module to enable other signals of the first protocol type hard disk except the RST signal to be in the working state, the first protocol type hard disk starts to work, and the second protocol type hard disk does not work;
if the current first protocol type hard disk is set to be in the non-working state, the controller controls the protocol switching module to enable other signals of the first protocol type hard disk except the RST signal to be in the non-working state, the first protocol type hard disk does not work, and the second protocol type hard disk starts to work.
Optionally, if the RST signal level of the first protocol type hard disk is a low level, setting the current first protocol type hard disk to be in an operating state, and setting the second protocol type hard disk to be in an inoperative state; and if the RST signal level of the first protocol type hard disk is high level, setting the current first protocol type hard disk to be in an inoperative state, and setting the second protocol type hard disk to be in the inoperative state.
Further, when the first protocol type hard disk is set to be in a working state, the clock chip opens the check clock signal, the relay controls the level of other signals except the RST signal of the first protocol type hard disk to be high level and the level of the RST signal of the second protocol type hard disk to be low level according to the control command of the controller; when the first protocol type hard disk is set to be in an inoperative state and the second protocol type hard disk is set to be in an operative state, the clock chip switch prohibits checking and dividing the clock signal, the relay controls the level of other signals except the RST signal of the first protocol type hard disk to be low level and the level of the RST signal of the second protocol type hard disk to be high level according to the control command of the controller.
The technical scheme adopted by the invention comprises the following technical effects:
1. the invention controls the working state switching of the NVME hard disk and the SATA hard disk through the controller, the relay and the clock chip, thereby realizing the mutual switching of two hard disk working modes under the condition that the hard disk back plate is not powered off, improving the functional test efficiency of the hard disk back plate in two hard disk modes, reducing the test time and the labor cost and avoiding repeated startup and shutdown.
2. The invention realizes the working state switching of the NVME hard disk and the SATA hard disk through the clock chip and the relay, is simpler and easier to operate compared with the traditional switching mode, and further reduces the test cost.
3. The controller of the invention adopts a PSOC (programmable system on a chip) controller, can be flexibly programmed according to actual needs, and improves the convenience of implementation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without any creative effort.
FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a pin definition of a third hard disk connector according to a first embodiment of the present invention;
FIG. 3 is a schematic flow chart of a second method embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
Example one
As shown in fig. 1, the present invention provides a dual-protocol hard disk test device compatible with NVME \ AHCI, including: the device comprises a controller 1, a first hard disk connector 2, a second hard disk connector 3 and a protocol switching module 4, wherein the first hard disk connector 2 is connected with a first protocol type hard disk 5, and the second hard disk connector 3 is connected with a second protocol type hard disk 6; the controller 1 is in communication connection with the first hard disk connector 2 and the second hard disk connector 3 respectively, and is configured to determine whether to set the current first protocol type hard disk 5 to a working state according to the RST signal level of the first protocol type hard disk 5, and control the first protocol type hard disk 5 and the second protocol type hard disk 6 to work and switch through the protocol switching module 4, where the first protocol type hard disk 5 is an NVME hard disk, and the second protocol type hard disk 6 is an SATA hard disk.
Further, the NVME \ AHCI compatible dual-protocol hard disk test device can be in communication connection with the mainboard 8 through a third hard disk connector 7, a male head of the first hard disk connector 7 is respectively connected with the second hard disk connector 2 and the third hard disk connector 3, and a female head of the first hard disk connector 7 is in communication connection with the mainboard 8; the main board 8 may communicate with the first protocol type hard disk 5 or the second protocol type hard disk 6 through the first hard disk connector 7, and perform read/write operations on the first hard disk connector 7 in the first protocol type hard disk 5 or the second protocol type hard disk 6, respectively.
The third hard disk connector 7 may adopt an U.2 connector, PIN definitions of which may be as shown in fig. 2, and all PINs are defined as NVME hard disk interface signal function and SATA hard disk interface signal function, respectively, so that it supports NVME and SATA hard disks at the same time. The power signal and the ground signal in the circuit are common signals, the NVME hard disk needs to use a 12V power supply, the SATA hard disk needs to use a 12V power supply and a 5V power supply, the NVME with the circuit refers to the signal of the NVME hard disk, and the circuit with the NVME with the circuit comprises a PCIE signal and an I2C signal, wherein TX and RX represent a pair of high-speed differential pairs, and the circuit with the circuit is used for connecting the PCIE signal. TX represents a transmitting terminal for transmitting data signals, RX represents a receiving terminal for receiving data signals, CLK _100M, SCL (serial clock line), SDA (serial data line) are clock signals, and I2C (a simple, bidirectional two-wire synchronous serial bus) is used as a bus. The marks in the circuit diagram, NVME _ SSD0_ TX _ DP0\ NVME _ SSD0_ TX _ DN0 and NVME _ SSD0_ RX _ DP0\ NVME _ SSD0_ RX _ DN0 are a group of PCIE signals of the NVME hard disk, and 4 groups of PCIE signal lines are shared in total. The circuit is marked with SATA and HDD0, and is a signal line of the SATA hard disk, and has PCIE signal and I2C signal, wherein SATA _ P0_ TX _ DP \ SATA _ P0_ TX _ DN and SATA _ P0_ RX _ DP \ SATA _ P0_ RX _ DN are a group of signals of the SATA hard disk, a total of 1 group of PCIE signals, PRSNT (in-place signal) and RDY (ready signal, namely RST signal of the hard disk of the second protocol type in the invention) are common signals, and I2C signal is taken.
Specifically, the controller 1 includes a communication module 11, a processing module 12, and a control module 13, where the communication module 11 is configured to receive a signal of the first protocol type hard disk 5 and a signal of the second protocol type hard disk 6; the processing module 12 is connected to the communication module 11, and determines whether to set the current first protocol type hard disk 5 to a working state according to the level of the received RST signal (hard disk initialization signal) of the first protocol type hard disk 5, and outputs a control command corresponding to the control; the control module 13 is in communication connection with the processing module 12, and controls the protocol switching module 4 to switch the first protocol type hard disk 5 and the second protocol type hard disk 6 according to the received control command of the processing module 12.
Specifically, the communication module 11 is respectively connected to the first hard disk connector, the second hard disk connector, and the first protocol type hard disk 5 and the second protocol type hard disk 6 to obtain and receive the RST signal and the other signals (the first protocol type hard disk 5), the second protocol type hard disk RST signal (RDY signal), and the other signals (the second protocol type hard disk 6) except the RST signal of the first protocol type hard disk 5.
Specifically, if the RST signal level of the first protocol type hard disk 5 is a low level, the current first protocol type hard disk 5 is set to be in an operating state, and the second protocol type hard disk 6 is in an inoperative state; if the RST signal level of the first protocol type hard disk 5 is a high level, the current first protocol type hard disk 5 is set to be in an inoperative state, and the second protocol type hard disk 6 is set to be in an operative state.
The protocol switching module 4 comprises a relay 41 and a clock chip 42, wherein the input end of the relay 41 is connected with the control module 13 of the controller 1, and the output end of the relay 41 is respectively connected with the first hard disk connector 2 and the second hard disk connector 3, and is used for controlling the level of other signals except the RST signal of the first protocol type hard disk 5 and the level of the RST signal of the second protocol type hard disk 6 according to the control command of the controller 1; the input end of the clock chip 42 is connected with the control module 13 of the controller 1, and the output end is connected with the first hard disk connector 2, and is used for controlling the work switching of the first protocol type hard disk 5 and the second protocol type hard disk 6 according to the control command of the controller 1.
Specifically, when the first protocol type hard disk 5 is set to be in the working state, the clock chip 42 turns on the minute clock signal, the relay 41 controls the level of the other signals except the RST signal of the first protocol type hard disk 5 to be the high level and the level of the RST signal of the second protocol type hard disk 6 to be the low level according to the control command of the controller 1; when the first protocol type hard disk 5 is set to be in the non-operating state and the second protocol type hard disk is set to be in the operating state, the clock chip switch prohibits the clock signal from being checked and divided, the relay 41 controls the level of other signals except the RST signal of the first protocol type hard disk 5 to be the low level and the level of the RST signal of the second protocol type hard disk 6 to be the high level according to the control command of the controller 1.
Further, the controller may be a PSOC controller, supporting custom programming.
The invention controls the working state switching of the NVME hard disk and the SATA hard disk through the controller, the relay and the clock chip, thereby realizing the mutual switching of two hard disk working modes under the condition that the hard disk back plate is not powered off, improving the functional test efficiency of the hard disk back plate in two hard disk modes, reducing the test time and the labor cost and avoiding repeated startup and shutdown.
The invention realizes the working state switching of the NVME hard disk and the SATA hard disk through the clock chip and the relay, is simpler and easier to operate compared with the traditional switching mode, and further reduces the test cost.
The controller of the invention adopts a PSOC (programmable system on a chip) controller, can be flexibly programmed according to actual needs, and improves the convenience of implementation.
Example two
As shown in fig. 3, the technical solution of the present invention further provides a method for testing a dual-protocol hard disk compatible with NVME \ AHCI, which is implemented based on the first embodiment, and includes:
s1, the controller receives the RST signal level of the first protocol type hard disk, and judges whether to set the current first protocol type hard disk to be in a working state according to the RST signal level of the first protocol type hard disk; if the judgment result is yes, executing step S2; if the judgment result is no, executing step S3;
s2, the controller makes the first protocol type hard disk in working state except RST signal by controlling the protocol switching module, the first protocol type hard disk starts working, the second protocol type hard disk does not work;
s3, the controller makes the first protocol type hard disk in the non-operation state except RST signal by controlling the protocol switching module, the first protocol type hard disk does not operate, the second protocol type hard disk starts to operate.
In steps S1-S3, if the RST signal level of the first protocol type hard disk is low level, setting the current first protocol type hard disk to be in an operating state, and setting the second protocol type hard disk to be in an inoperative state; and if the RST signal level of the first protocol type hard disk is high level, setting the current first protocol type hard disk to be in an inoperative state, and setting the second protocol type hard disk to be in the inoperative state.
Specifically, when the first protocol type hard disk is set to be in a working state, the clock chip opens the minute clock signal, the relay controls the level of other signals except the RST signal of the first protocol type hard disk to be high level and the level of the RST signal of the second protocol type hard disk to be low level according to the control command of the controller; when the first protocol type hard disk is set to be in an inoperative state and the second protocol type hard disk is set to be in an operative state, the clock chip is turned off to prohibit the clock signal from being checked and divided, the relay controls the level of other signals except the RST signal of the first protocol type hard disk to be low level and the level of the RST signal of the second protocol type hard disk to be high level according to the control command of the controller.
The invention controls the working state switching of the NVME hard disk and the SATA hard disk through the controller, the relay and the clock chip, thereby realizing the mutual switching of two hard disk working modes under the condition that the hard disk back plate is not powered off, improving the functional test efficiency of the hard disk back plate in two hard disk modes, reducing the test time and the labor cost and avoiding repeated startup and shutdown.
The invention realizes the working state switching of the NVME hard disk and the SATA hard disk through the clock chip and the relay, is simpler and easier to operate compared with the traditional switching mode, and further reduces the test cost.
The controller of the invention adopts a PSOC (programmable system on a chip) controller, can be flexibly programmed according to actual needs, and improves the convenience of implementation.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (10)
1. A compatible NVME \ AHCI dual protocol hard disk testing arrangement, characterized by, include: the device comprises a controller, a first hard disk connector, a second hard disk connector and a protocol switching module, wherein the first hard disk connector is connected with a first protocol type hard disk, and the second hard disk connector is connected with a second protocol type hard disk; the controller is respectively in communication connection with the first hard disk connector and the second hard disk connector and is used for judging whether the current first protocol type hard disk is set to be in a working state or not according to the RST signal level of the first protocol type hard disk, and controlling the first protocol type hard disk and the second protocol type hard disk to work and switch through the protocol switching module, wherein the first protocol type hard disk is an NVME hard disk, and the second protocol type hard disk is an SATA hard disk.
2. The NVME \ AHCI compatible dual-protocol hard disk testing device as recited in claim 1, wherein the NVME \ AHCI compatible dual-protocol hard disk testing device is in communication connection with a motherboard through a third hard disk connector, a male head of the first hard disk connector is respectively connected with the second hard disk connector and the third hard disk connector, and a female head of the first hard disk connector is in communication connection with the motherboard.
3. The NVME \ AHCI dual-protocol hard disk testing device compatible as recited in claim 1, wherein the controller comprises a communication module, a processing module and a control module, wherein the communication module is used for receiving signals of a first protocol type hard disk and signals of a second protocol type hard disk; the processing module is connected with the communication module, judges whether the current first protocol type hard disk is set to be in a working state or not according to the received RST signal level of the first protocol type hard disk, and outputs a control corresponding command; the control module is in communication connection with the processing module and controls the protocol switching module to switch the work of the first protocol type hard disk and the second protocol type hard disk according to the received control command of the processing module.
4. The NVME \ AHCI dual-protocol hard disk testing device as recited in claim 3, wherein if the RST signal level of the first protocol type hard disk is low level, the current first protocol type hard disk is set to be in working state, and the second protocol type hard disk is in non-working state; and if the RST signal level of the first protocol type hard disk is high level, setting the current first protocol type hard disk to be in an inoperative state, and setting the second protocol type hard disk to be in an operative state.
5. The NVME \ AHCI dual-protocol hard disk testing device compatible with the claim 1, wherein the protocol switching module comprises a relay and a clock chip, an input end of the relay is connected with the controller, an output end of the relay is respectively connected with the first hard disk connector and the second hard disk connector, and the relay is used for controlling the level of other signals except RST signals of the first protocol type hard disk and the level of RST signals of the second protocol type hard disk according to a control command of the controller; the input end of the clock chip is connected with the controller, the output end of the clock chip is connected with the first hard disk connector, and the clock chip is used for controlling the work switching of the first protocol type hard disk and the second protocol type hard disk according to the control command of the controller.
6. The NVME \ AHCI dual-protocol hard disk testing device compatible as recited in claim 5, wherein when the first protocol type hard disk is set to be in a working state, the clock chip opens the minute clock signal; when the first protocol type hard disk is set to be in an inoperative state and the second protocol type hard disk is set to be in an operative state, the clock chip is closed to forbid checking the clock signal.
7. The NVME \ AHCI dual-protocol-compatible hard disk test device as claimed in any one of claims 1 to 6, wherein the controller is a PSOC controller.
8. A method for testing a hard disk compatible with NVME \ AHCI dual protocols is realized on the basis of the device for testing the hard disk compatible with the NVME \ AHCI dual protocols as set forth in any one of claims 1 to 7, and comprises the following steps:
the controller receives the RST signal level of the first protocol type hard disk and judges whether the current first protocol type hard disk is set to be in a working state or not according to the RST signal level of the first protocol type hard disk;
if the current first protocol type hard disk is set to be in a working state, the controller controls the protocol switching module to enable other signals of the first protocol type hard disk except the RST signal to be in the working state, the first protocol type hard disk starts to work, and the second protocol type hard disk does not work;
if the current first protocol type hard disk is set to be in the non-working state, the controller controls the protocol switching module to enable other signals of the first protocol type hard disk except the RST signal to be in the non-working state, the first protocol type hard disk does not work, and the second protocol type hard disk starts to work.
9. The method for testing the NVME \ AHCI dual-protocol hard disk compatible as claimed in claim 8, wherein if the RST signal level of the first protocol type hard disk is low level, the current first protocol type hard disk is set to be in working state, and the second protocol type hard disk is set to be in non-working state; and if the RST signal level of the first protocol type hard disk is high level, setting the current first protocol type hard disk to be in an inoperative state, and setting the second protocol type hard disk to be in the inoperative state.
10. The NVME \ AHCI dual-protocol hard disk test device according to claim 9, wherein when the first protocol type hard disk is set to a working state, the clock chip turns on the minute clock signal, the relay controls the level of the other signals of the first protocol type hard disk except the RST signal to be a high level and the level of the RST signal of the second protocol type hard disk to be a low level according to the control command of the controller; when the first protocol type hard disk is set to be in an inoperative state and the second protocol type hard disk is set to be in an operative state, the clock chip switch prohibits checking and dividing the clock signal, the relay controls the level of other signals except the RST signal of the first protocol type hard disk to be low level and the level of the RST signal of the second protocol type hard disk to be high level according to the control command of the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110220895.XA CN112951315A (en) | 2021-02-26 | 2021-02-26 | NVME \ AHCI compatible dual-protocol hard disk testing device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110220895.XA CN112951315A (en) | 2021-02-26 | 2021-02-26 | NVME \ AHCI compatible dual-protocol hard disk testing device and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112951315A true CN112951315A (en) | 2021-06-11 |
Family
ID=76246687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110220895.XA Pending CN112951315A (en) | 2021-02-26 | 2021-02-26 | NVME \ AHCI compatible dual-protocol hard disk testing device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112951315A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114461027A (en) * | 2021-12-30 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Hard disk connecting device and server |
| CN114490229A (en) * | 2021-12-23 | 2022-05-13 | 苏州浪潮智能科技有限公司 | Dual-protocol interface testing device and method |
| CN117009162A (en) * | 2023-10-07 | 2023-11-07 | 天津国芯科技有限公司 | Method for identifying hard disk by using triple-mode RAID card chip |
| CN117056146A (en) * | 2023-08-15 | 2023-11-14 | 苏州德伽存储科技有限公司 | Testing device, method and medium compatible with SSD of multiple different protocols simultaneously |
| CN117234313A (en) * | 2023-09-14 | 2023-12-15 | 苏州德伽存储科技有限公司 | Power supply control device, method and storage medium for solid state disk power supply test |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1667583A (en) * | 2004-03-12 | 2005-09-14 | 鸿富锦精密工业（深圳）有限公司 | Motherboard function test board |
| CN101615104A (en) * | 2008-06-25 | 2009-12-30 | 鸿富锦精密工业（深圳）有限公司 | System for switching hard disks and changing method thereof |
| CN207037639U (en) * | 2017-06-05 | 2018-02-23 | 深圳中电长城信息安全系统有限公司 | A kind of hard disk control switching circuit and server |
| CN110377546A (en) * | 2019-06-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of storage expansion board and server storage architecture |
| CN110377956A (en) * | 2019-06-20 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of more hard disk management backboards and method of U.2 interface |
| US20200043565A1 (en) * | 2018-08-02 | 2020-02-06 | Exicon Industrial Joint Rnd Center | Storage protocol matching device and method |
| CN112131149A (en) * | 2020-08-17 | 2020-12-25 | 苏州浪潮智能科技有限公司 | Method and equipment for gating hard disk |
-
2021
- 2021-02-26 CN CN202110220895.XA patent/CN112951315A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1667583A (en) * | 2004-03-12 | 2005-09-14 | 鸿富锦精密工业（深圳）有限公司 | Motherboard function test board |
| CN101615104A (en) * | 2008-06-25 | 2009-12-30 | 鸿富锦精密工业（深圳）有限公司 | System for switching hard disks and changing method thereof |
| CN207037639U (en) * | 2017-06-05 | 2018-02-23 | 深圳中电长城信息安全系统有限公司 | A kind of hard disk control switching circuit and server |
| US20200043565A1 (en) * | 2018-08-02 | 2020-02-06 | Exicon Industrial Joint Rnd Center | Storage protocol matching device and method |
| CN110377956A (en) * | 2019-06-20 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of more hard disk management backboards and method of U.2 interface |
| CN110377546A (en) * | 2019-06-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of storage expansion board and server storage architecture |
| CN112131149A (en) * | 2020-08-17 | 2020-12-25 | 苏州浪潮智能科技有限公司 | Method and equipment for gating hard disk |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114490229A (en) * | 2021-12-23 | 2022-05-13 | 苏州浪潮智能科技有限公司 | Dual-protocol interface testing device and method |
| CN114461027A (en) * | 2021-12-30 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Hard disk connecting device and server |
| CN114461027B (en) * | 2021-12-30 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Hard disk connecting device and server |
| CN117056146A (en) * | 2023-08-15 | 2023-11-14 | 苏州德伽存储科技有限公司 | Testing device, method and medium compatible with SSD of multiple different protocols simultaneously |
| CN117234313A (en) * | 2023-09-14 | 2023-12-15 | 苏州德伽存储科技有限公司 | Power supply control device, method and storage medium for solid state disk power supply test |
| CN117009162A (en) * | 2023-10-07 | 2023-11-07 | 天津国芯科技有限公司 | Method for identifying hard disk by using triple-mode RAID card chip |
| CN117009162B (en) * | 2023-10-07 | 2023-12-15 | 天津国芯科技有限公司 | Method for identifying hard disk by using triple-mode RAID card chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112951315A (en) | NVME \ AHCI compatible dual-protocol hard disk testing device and method | |
| US7194593B2 (en) | Memory hub with integrated non-volatile memory | |
| US9081705B2 (en) | Methods and apparatus for reliable detection and enumeration of devices | |
| CN111459854B (en) | Method for securing digital card, flash memory controller and electronic device | |
| US7209995B2 (en) | Efficient connection between modules of removable electronic circuit cards | |
| JP2013515992A (en) | USB3.0 support on mobile platforms with USB2.0 interface | |
| CN101919169A (en) | Mobile terminal for supporting UART communication and USB communication using single connector and operating method for same | |
| US20220292035A1 (en) | Equalization Time Configuration Method, Chip, and Communications System | |
| US10346340B1 (en) | Hot swap control circuit and related storage server system | |
| TWI754183B (en) | Hdd backplane management device | |
| CN101599050B (en) | Adaptable pci express controller core and method | |
| CN100414526C (en) | Method and device for automatically adjusting bus width | |
| CN109815169B (en) | Storage device and storage link self-adaption method thereof | |
| TWI613586B (en) | Single input/output cell with multiple bond pads and/or transmitters | |
| CN216388068U (en) | PCIE interface verification board and test system | |
| CN213365381U (en) | Main board | |
| CN114265731A (en) | PCIE interface verification board, test system and test method | |
| CN101853231B (en) | Mainboard, computer and storage device | |
| CN114385527A (en) | Hard disk compatible platform, mainboard and control method | |
| CN107704403B (en) | Device and method for optimizing signal transmission of main back plate | |
| CN110047550B (en) | Data storage device, memory control circuit and monitoring method thereof | |
| US9465765B2 (en) | All-in-one SATA interface storage device | |
| CN115017083A (en) | Data transmission system, data transmission device, and data transmission method | |
| CN115422110B (en) | Port configuration method of electronic equipment and PCIE Switch chip | |
| CN106844113B (en) | Server fault recovery system and method adopting redundant PCH |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210611 |